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7334ffa373
* Format all handwritten asm and document some * Use c preprocessor for constants * Fix * Fix PI_STATUS_ERROR, some label improvements * Avoid hi/lo for constants * Some more comments * Properly mark functions as functions and their sizes * Fix merge * Improvements * Review suggestions, rework procedure start/end macros to be more like libreultra * Move IPL3 symbol definitions into ipl3.s * Fix undefined_syms, add include and language guards to asm.h and fix the comment in gbi.h * Consistent hex capitalization, add some MIPS builtin defines to CC_CHECK to behave properly * Add -no-pad-sections assembler option and clean up alignment in gu files and bzero * Further suggestions and improvements * Matrix conversion function clarifications * Fix passing AVOID_UB to gcc * Suggestions * Suggestions, global interrupt mask improvements * Further suggestions, interrupt mask comments * Comments fixes, rdb.h * Switch from # comments to // comments, remove unnecesary .set gp=64 directives * Further review suggestions * Missed one
95 lines
2.6 KiB
ArmAsm
95 lines
2.6 KiB
ArmAsm
#include "ultra64/asm.h"
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#include "ultra64/r4300.h"
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.set noat
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.set noreorder
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.section .text
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.balign 16
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/**
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* void osInvalDCache(void* vaddr, s32 nbytes);
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*
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* Invalidates the CPU Data Cache for `nbytes` at `vaddr`.
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* The cache is not automatically synced with physical memory, so cache
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* lines must be invalidated to ensure old data is not used in place of
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* newly available data supplied by an external agent in a DMA operation.
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*
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* If `vaddr` is not aligned to a cache line boundary, or nbytes is not a
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* multiple of the data cache line size (16 bytes) a larger region is
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* invalidated.
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*
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* If the amount to invalidate is at least the data cache size (DCACHE_SIZE),
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* the entire data cache is invalidated.
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*/
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LEAF(osInvalDCache)
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// If the amount to invalidate is less than or equal to 0, return immediately
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blez $a1, 3f
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nop
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// If the amount to invalidate is as large as or larger than
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// the data cache size, invalidate all
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li $t3, DCACHE_SIZE
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sltu $at, $a1, $t3
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beqz $at, 4f
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nop
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// Ensure end address doesn't wrap around and end up smaller
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// than the start address
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move $t0, $a0
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addu $t1, $a0, $a1
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sltu $at, $t0, $t1
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beqz $at, 3f
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nop
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// Mask start with cache line
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andi $t2, $t0, DCACHE_LINEMASK
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// If mask is not zero, the start is not cache aligned
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beqz $t2, 1f
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addiu $t1, $t1, -DCACHE_LINESIZE
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// Subtract mask result to align to cache line
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subu $t0, $t0, $t2
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// Hit-Writeback-Invalidate unaligned part
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cache (CACH_PD | C_HWBINV), ($t0)
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sltu $at, $t0, $t1
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// If that's all there is to do, return early
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beqz $at, 3f
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nop
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addiu $t0, $t0, DCACHE_LINESIZE
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1:
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// Mask end with cache line
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andi $t2, $t1, DCACHE_LINEMASK
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// If mask is not zero, the end is not cache aligned
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beqz $t2, 1f
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nop
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// Subtract mask result to align to cache line
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subu $t1, $t1, $t2
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// Hit-Writeback-Invalidate unaligned part
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cache (CACH_PD | C_HWBINV), DCACHE_LINESIZE($t1)
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sltu $at, $t1, $t0
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// If that's all there is to do, return early
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bnez $at, 3f
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nop
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// Invalidate the rest
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1:
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// Hit-Invalidate
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cache (CACH_PD | C_HINV), ($t0)
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sltu $at, $t0, $t1
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bnez $at, 1b
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addiu $t0, $t0, DCACHE_LINESIZE
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3:
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jr $ra
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nop
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4:
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li $t0, K0BASE
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addu $t1, $t0, $t3
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addiu $t1, $t1, -DCACHE_LINESIZE
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5:
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// Index-Writeback-Invalidate
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cache (CACH_PD | C_IWBINV), ($t0)
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sltu $at, $t0, $t1
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bnez $at, 5b
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addiu $t0, DCACHE_LINESIZE
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jr $ra
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nop
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END(osInvalDCache)
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