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Merge pull request #88 from X0rg/master

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Update CPUs database
This commit is contained in:
Veselin Georgiev 2017-03-15 12:23:24 +00:00 • committed by GitHub
commit 037245032e
4 changed files with 99 additions and 70 deletions
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4
libcpuid/intel_code_t.h
View file

@ -80,4 +80,6 @@
CODE(CORE_SKYLAKE3), /* 14nm Core-iX, Skylake */
CODE(CORE_SKYLAKE5),
CODE(CORE_SKYLAKE7),
CODE(CORE_SKYLAKEM3),
CODE(CORE_SKYLAKEM5),
CODE(CORE_SKYLAKEM7),

107
libcpuid/recog_amd.c
View file

@ -184,8 +184,8 @@ const struct match_entry_t cpudb_amd[] = {
{ 15, -1, -1, 15, 0x68, 2, 512, -1, TURION_X2 , 0, "Turion X2 (Tyler/512K)" },
{ 15, -1, -1, 17, 3, 2, 512, -1, TURION_X2 , 0, "Turion X2 (Griffin/512K)" },
{ 15, -1, -1, 17, 3, 2, 1024, -1, TURION_X2 , 0, "Turion X2 (Griffin/1024K)" },
/* K9 Architecture */
/* K10 Architecture (2007) */
{ 15, -1, -1, 16, -1, 1, -1, -1, PHENOM , 0, "Unknown AMD Phenom" },
{ 15, 2, -1, 16, -1, 1, -1, -1, PHENOM , 0, "Phenom" },
{ 15, 2, -1, 16, -1, 3, -1, -1, PHENOM , 0, "Phenom X3 (Toliman)" },
@ -206,66 +206,65 @@ const struct match_entry_t cpudb_amd[] = {
{ 15, 5, -1, 16, 5, 4, 512, -1, PHENOM2 , 0, "Phenom II X4 (Deneb)" },
{ 15, 4, -1, 16, 10, 4, 512, -1, PHENOM2 , 0, "Phenom II X4 (Zosma)" },
{ 15, 4, -1, 16, 10, 6, 512, -1, PHENOM2 , 0, "Phenom II X6 (Thuban)" },
/* Athlon II derivates: */
{ 15, 6, -1, 16, 6, 2, 512, -1, ATHLON , 0, "Athlon II (Champlain)" },
{ 15, 6, -1, 16, 6, 2, 512, -1, ATHLON_64_X2 , 0, "Athlon II X2 (Regor)" },
{ 15, 6, -1, 16, 6, 2, 1024, -1, ATHLON_64_X2 , 0, "Athlon II X2 (Regor)" },
{ 15, 5, -1, 16, 5, 3, 512, -1, ATHLON_64_X3 , 0, "Athlon II X3 (Rana)" },
{ 15, 5, -1, 16, 5, 4, 512, -1, ATHLON_64_X4 , 0, "Athlon II X4 (Propus)" },
/* Llano APUs (2011): */
{ 15, 1, -1, 18, 1, 2, -1, -1, FUSION_EA , 0, "Llano X2" },
{ 15, 1, -1, 18, 1, 3, -1, -1, FUSION_EA , 0, "Llano X3" },
{ 15, 1, -1, 18, 1, 4, -1, -1, FUSION_EA , 0, "Llano X4" },
/* Family 14h: Bobcat Architecture (2011) */
{ 15, 2, -1, 20, -1, 1, -1, -1, FUSION_C , 0, "Brazos Ontario" },
{ 15, 2, -1, 20, -1, 2, -1, -1, FUSION_C , 0, "Brazos Ontario (Dual-core)" },
{ 15, 1, -1, 20, -1, 1, -1, -1, FUSION_E , 0, "Brazos Zacate" },
{ 15, 1, -1, 20, -1, 2, -1, -1, FUSION_E , 0, "Brazos Zacate (Dual-core)" },
{ 15, 2, -1, 20, -1, 2, -1, -1, FUSION_Z , 0, "Brazos Desna (Dual-core)" },
/* Family 15h: Bulldozer Architecture (2011) */
{ 15, -1, -1, 21, 0, 4, -1, -1, NO_CODE , 0, "Bulldozer X2" },
{ 15, -1, -1, 21, 1, 4, -1, -1, NO_CODE , 0, "Bulldozer X2" },
{ 15, -1, -1, 21, 1, 6, -1, -1, NO_CODE , 0, "Bulldozer X3" },
{ 15, -1, -1, 21, 1, 8, -1, -1, NO_CODE , 0, "Bulldozer X4" },
/* 2nd-gen, Piledriver core (2012): */
{ 15, -1, -1, 21, 2, 4, -1, -1, NO_CODE , 0, "Vishera X2" },
{ 15, -1, -1, 21, 2, 6, -1, -1, NO_CODE , 0, "Vishera X3" },
{ 15, -1, -1, 21, 2, 8, -1, -1, NO_CODE , 0, "Vishera X4" },
{ 15, 0, -1, 21, 16, 2, -1, -1, FUSION_A , 0, "Trinity X2" },
{ 15, 0, -1, 21, 16, 4, -1, -1, FUSION_A , 0, "Trinity X4" },
{ 15, 3, -1, 21, 19, 2, -1, -1, FUSION_A , 0, "Richland X2" },
{ 15, 3, -1, 21, 19, 4, -1, -1, FUSION_A , 0, "Richland X4" },
/* 3rd-gen, Steamroller core (2014): */
{ 15, 0, -1, 21, 48, 2, -1, -1, FUSION_A , 0, "Kaveri X2" },
{ 15, 0, -1, 21, 48, 4, -1, -1, FUSION_A , 0, "Kaveri X4" },
{ 15, 8, -1, 21, 56, 4, -1, -1, FUSION_A , 0, "Godavari X4" },
/* 4th-gen, Excavator core (2015): */
{ 15, 1, -1, 21, 96, 2, -1, -1, FUSION_A , 0, "Carrizo X2" },
{ 15, 1, -1, 21, 96, 4, -1, -1, FUSION_A , 0, "Carrizo X4" },
{ 15, 5, -1, 21, 101, 2, -1, -1, FUSION_A , 0, "Bristol Ridge X2" },
{ 15, 5, -1, 21, 101, 4, -1, -1, FUSION_A , 0, "Bristol Ridge X4" },
{ 15, 0, -1, 21, 112, 2, -1, -1, FUSION_A , 0, "Stoney Ridge X2" },
{ 15, 0, -1, 21, 112, 2, -1, -1, FUSION_E , 0, "Stoney Ridge X2" },
/* Family 16h: Jaguar Architecture (2013) */
{ 15, 0, -1, 22, 0, 2, -1, -1, FUSION_A , 0, "Kabini X2" },
{ 15, 0, -1, 22, 0, 4, -1, -1, FUSION_A , 0, "Kabini X4" },
/* 2nd-gen, Puma core (2013): */
{ 15, 0, -1, 22, 48, 2, -1, -1, FUSION_E , 0, "Mullins X2" },
{ 15, 0, -1, 22, 48, 4, -1, -1, FUSION_A , 0, "Mullins X4" },
/* Family 17h: Zen Architecture (2017) */
//{ 15, -1, -1, 23, 1, 8, -1, -1, NO_CODE , 0, "Ryzen 7" }, //FIXME
//{ 15, -1, -1, 23, 1, 6, -1, -1, NO_CODE , 0, "Ryzen 5" }, //TBA
//{ 15, -1, -1, 23, 1, 4, -1, -1, NO_CODE , 0, "Ryzen 5" }, //TBA
//{ 15, -1, -1, 23, 1, 4, -1, -1, NO_CODE , 0, "Ryzen 3" }, //TBA
//{ 15, -1, -1, 23, 1, 4, -1, -1, NO_CODE , 0, "Raven Ridge" }, //TBA
/* 2011 CPUs: K10 architecture: Llano */
{ 15, 1, -1, 18, 1, 2, 512, -1, FUSION_EA , 0, "Llano X2" },
{ 15, 1, -1, 18, 1, 2, 1024, -1, FUSION_EA , 0, "Llano X2" },
{ 15, 1, -1, 18, 1, 3, 1024, -1, FUSION_EA , 0, "Llano X3" },
{ 15, 1, -1, 18, 1, 4, 1024, -1, FUSION_EA , 0, "Llano X4" },
/* 2011 CPUs: Bobcat architecture: Ontario, Zacate, Desna, Hondo */
{ 15, 2, -1, 20, -1, 1, 512, -1, FUSION_C , 0, "Brazos Ontario" },
{ 15, 2, -1, 20, -1, 2, 512, -1, FUSION_C , 0, "Brazos Ontario (Dual-core)" },
{ 15, 1, -1, 20, -1, 1, 512, -1, FUSION_E , 0, "Brazos Zacate" },
{ 15, 1, -1, 20, -1, 2, 512, -1, FUSION_E , 0, "Brazos Zacate (Dual-core)" },
{ 15, 2, -1, 20, -1, 2, 512, -1, FUSION_Z , 0, "Brazos Desna (Dual-core)" },
/* 2012 CPUs: Piledriver architecture: Trinity and Richland */
{ 15, 0, -1, 21, 10, 2, 1024, -1, FUSION_A , 0, "Trinity X2" },
{ 15, 0, -1, 21, 16, 2, 1024, -1, FUSION_A , 0, "Trinity X2" },
{ 15, 0, -1, 21, 10, 4, 1024, -1, FUSION_A , 0, "Trinity X4" },
{ 15, 0, -1, 21, 16, 4, 1024, -1, FUSION_A , 0, "Trinity X4" },
{ 15, 3, -1, 21, 13, 2, 1024, -1, FUSION_A , 0, "Richland X2" },
{ 15, 3, -1, 21, 13, 4, 1024, -1, FUSION_A , 0, "Richland X4" },
/* 2013 CPUs: Jaguar architecture: Kabini and Temash */
{ 15, 0, -1, 22, 0, 2, 1024, -1, FUSION_A , 0, "Kabini X2" },
{ 15, 0, -1, 22, 0, 4, 1024, -1, FUSION_A , 0, "Kabini X4" },
/* 2014 CPUs: Steamroller architecture: Kaveri */
{ 15, 0, -1, 21, 30, 2, 1024, -1, FUSION_A , 0, "Kaveri X2" },
{ 15, 0, -1, 21, 30, 4, 1024, -1, FUSION_A , 0, "Kaveri X4" },
/* 2014 CPUs: Puma architecture: Beema and Mullins */
{ 15, 0, -1, 22, 30, 2, 1024, -1, FUSION_E , 0, "Mullins X2" },
{ 15, 0, -1, 22, 30, 4, 1024, -1, FUSION_A , 0, "Mullins X4" },
/* 2015 CPUs: Excavator architecture: Carrizo */
{ 15, 1, -1, 21, 60, 2, 1024, -1, FUSION_A , 0, "Carrizo X2" },
{ 15, 1, -1, 21, 60, 4, 1024, -1, FUSION_A , 0, "Carrizo X4" },
/* 2015 CPUs: Steamroller architecture: Godavari */
//TODO
/* 2016 CPUs: Excavator architecture: Bristol Ridge */
//TODO
/* Newer Opterons: */
{ 15, 9, -1, 22, 9, 8, -1, -1, OPTERON_GENERIC , 0, "Magny-Cours Opteron" },
/* Bulldozer CPUs: */
{ 15, -1, -1, 21, 0, 4, 2048, -1, NO_CODE , 0, "Bulldozer X2" },
{ 15, -1, -1, 21, 1, 4, 2048, -1, NO_CODE , 0, "Bulldozer X2" },
{ 15, -1, -1, 21, 1, 6, 2048, -1, NO_CODE , 0, "Bulldozer X3" },
{ 15, -1, -1, 21, 1, 8, 2048, -1, NO_CODE , 0, "Bulldozer X4" },
/* Piledriver CPUs: */
{ 15, -1, -1, 21, 2, 4, 2048, -1, NO_CODE , 0, "Vishera X2" },
{ 15, -1, -1, 21, 2, 6, 2048, -1, NO_CODE , 0, "Vishera X3" },
{ 15, -1, -1, 21, 2, 8, 2048, -1, NO_CODE , 0, "Vishera X4" },
/* Steamroller CPUs: */
//TODO
/* Excavator CPUs: */
//TODO
/* Zen CPUs: */
//TODO
};

56
libcpuid/recog_intel.c
View file

@ -210,7 +210,7 @@ const struct match_entry_t cpudb_intel[] = {
{ 6, 7, -1, -1, 23, 1, -1, -1, CORE_SOLO , 0, "Unknown Core 45nm" },
{ 6, 7, -1, -1, 23, 1, -1, -1, CORE_DUO , 0, "Unknown Core 45nm" },
{ 6, 7, -1, -1, 23, 2, 1024, -1, WOLFDALE , 0, "Celeron Wolfdale 1M" },
{ 6, 7, -1, -1, 23, 2, 1024, -1, WOLFDALE , 0, "Celeron Wolfdale 1M" },
{ 6, 7, -1, -1, 23, 2, 2048, -1, WOLFDALE , 0, "Wolfdale (Core 2 Duo) 2M" },
{ 6, 7, -1, -1, 23, 2, 3072, -1, WOLFDALE , 0, "Wolfdale (Core 2 Duo) 3M" },
{ 6, 7, -1, -1, 23, 2, 6144, -1, WOLFDALE , 0, "Wolfdale (Core 2 Duo) 6M" },
@ -271,9 +271,9 @@ const struct match_entry_t cpudb_intel[] = {
/* Ivy Bridge CPUs (22nm): */
{ 6, 10, -1, -1, 58, -1, -1, -1, XEON , 0, "Ivy Bridge (Xeon)" },
{ 6, 10, -1, -1, 58, 4, -1, -1, CORE_IVY7 , 0, "Ivy Bridge (Core i7)" },
{ 6, 10, -1, -1, 58, 4, -1, -1, CORE_IVY5 , 0, "Ivy Bridge (Core i5)" },
{ 6, 10, -1, -1, 58, 2, -1, -1, CORE_IVY3 , 0, "Ivy Bridge (Core i3)" },
{ 6, 10, -1, -1, 58, 4, -1, -1, CORE_IVY7 , 0, "Ivy Bridge (Core i7)" },
{ 6, 10, -1, -1, 58, 4, -1, -1, CORE_IVY5 , 0, "Ivy Bridge (Core i5)" },
{ 6, 10, -1, -1, 58, 2, -1, -1, CORE_IVY3 , 0, "Ivy Bridge (Core i3)" },
{ 6, 10, -1, -1, 58, 2, -1, -1, PENTIUM , 0, "Ivy Bridge (Pentium)" },
{ 6, 10, -1, -1, 58, 1, -1, -1, CELERON , 0, "Ivy Bridge (Celeron)" },
{ 6, 10, -1, -1, 58, 2, -1, -1, CELERON , 0, "Ivy Bridge (Celeron)" },
@ -281,12 +281,12 @@ const struct match_entry_t cpudb_intel[] = {
/* Haswell CPUs (22nm): */
{ 6, 12, -1, -1, 60, -1, -1, -1, XEON , 0, "Haswell (Xeon)" },
{ 6, 12, -1, -1, 60, 4, -1, -1, CORE_HASWELL7 , 0, "Haswell (Core i7)" },
{ 6, 5, -1, -1, 69, 4, -1, -1, CORE_HASWELL7 , 0, "Haswell (Core i7)" },
{ 6, 12, -1, -1, 60, 4, -1, -1, CORE_HASWELL7 , 0, "Haswell (Core i7)" },
{ 6, 5, -1, -1, 69, 4, -1, -1, CORE_HASWELL7 , 0, "Haswell (Core i7)" },
{ 6, 12, -1, -1, 60, 4, -1, -1, CORE_HASWELL5 , 0, "Haswell (Core i5)" },
{ 6, 5, -1, -1, 69, 4, -1, -1, CORE_HASWELL5 , 0, "Haswell (Core i5)" },
{ 6, 12, -1, -1, 60, 2, -1, -1, CORE_HASWELL3 , 0, "Haswell (Core i3)" },
{ 6, 5, -1, -1, 69, 2, -1, -1, CORE_HASWELL3 , 0, "Haswell (Core i3)" },
{ 6, 5, -1, -1, 69, 2, -1, -1, CORE_HASWELL3 , 0, "Haswell (Core i3)" },
{ 6, 12, -1, -1, 60, 2, -1, -1, PENTIUM , 0, "Haswell (Pentium)" },
{ 6, 12, -1, -1, 60, 2, -1, -1, CELERON , 0, "Haswell (Celeron)" },
{ 6, 12, -1, -1, 60, 1, -1, -1, CELERON , 0, "Haswell (Celeron)" },
@ -302,22 +302,37 @@ const struct match_entry_t cpudb_intel[] = {
{ 6, 13, -1, -1, 61, 2, -1, -1, PENTIUM , 0, "Broadwell-U (Pentium)" },
{ 6, 13, -1, -1, 61, 2, -1, -1, CELERON , 0, "Broadwell-U (Celeron)" },
{ 6, 13, -1, -1, 61, 2, -1, -1, NA , 0, "Broadwell-U (Core M)" },
{ 6, 15, -1, -1, 79, -1, -1, -1, XEON , 0, "Broadwell-E (Xeon)" },
{ 6, 15, -1, -1, 79, 2, -1, -1, CORE_BROADWELL3 , 0, "Broadwell-E (Core i3)" },
{ 6, 15, -1, -1, 79, 2, -1, -1, CORE_BROADWELL5 , 0, "Broadwell-E (Core i5)" },
{ 6, 15, -1, -1, 79, 4, -1, -1, CORE_BROADWELL5 , 0, "Broadwell-E (Core i5)" },
{ 6, 15, -1, -1, 79, 2, -1, -1, CORE_BROADWELL7 , 0, "Broadwell-E (Core i7)" },
{ 6, 15, -1, -1, 79, 4, -1, -1, CORE_BROADWELL7 , 0, "Broadwell-E (Core i7)" },
/* Skylake CPUs (14nm): */
{ 6, 14, -1, -1, 94, -1, -1, -1, XEON , 0, "Skylake (Xeon)" },
{ 6, 14, -1, -1, 94, 4, -1, -1, CORE_BROADWELL7 , 0, "Skylake (Core i7)" },
{ 6, 14, -1, -1, 94, 4, -1, -1, CORE_BROADWELL5 , 0, "Skylake (Core i5)" },
{ 6, 14, -1, -1, 94, 4, -1, -1, CORE_BROADWELL3 , 0, "Skylake (Core i3)" },
{ 6, 14, -1, -1, 94, 4, -1, -1, PENTIUM , 0, "Skylake (Pentium)" },
{ 6, 14, -1, -1, 94, 2, -1, -1, CORE_BROADWELL3 , 0, "Skylake (Core i3)" },
{ 6, 14, -1, -1, 94, 2, -1, -1, PENTIUM , 0, "Skylake (Pentium)" },
{ 6, 14, -1, -1, 78, 2, -1, -1, PENTIUM , 0, "Skylake (Pentium)" },
{ 6, 14, -1, -1, 94, 2, -1, -1, CELERON , 0, "Skylake (Celeron)" },
{ 6, 14, -1, -1, 78, 2, -1, -1, CELERON , 0, "Skylake (Celeron)" },
{ 6, 14, -1, -1, 78, 2, -1, -1, CORE_SKYLAKEM7 , 0, "Skylake (Core m7)" },
{ 6, 14, -1, -1, 78, 2, -1, -1, CORE_SKYLAKEM5 , 0, "Skylake (Core m5)" },
{ 6, 14, -1, -1, 78, 2, -1, -1, CORE_SKYLAKEM3 , 0, "Skylake (Core m3)" },
/* Kaby Lake CPUs (14nm): */
{ 6, 14, -1, -1, 158, 4, -1, -1, CORE_BROADWELL7 , 0, "Kaby Lake (Core i7)" },
{ 6, 14, -1, -1, 158, 4, -1, -1, CORE_BROADWELL5 , 0, "Kaby Lake (Core i5)" },
{ 6, 14, -1, -1, 158, 2, -1, -1, CORE_BROADWELL3 , 0, "Kaby Lake (Core i3)" },
{ 6, 14, -1, -1, 158, 2, -1, -1, PENTIUM , 0, "Kaby Lake (Pentium)" },
{ 6, 14, -1, -1, 158, 2, -1, -1, CELERON , 0, "Kaby Lake (Celeron)" },
{ 6, 14, -1, -1, 158, 2, -1, -1, CORE_SKYLAKEM3 , 0, "Kaby Lake (Core m3)" },
/* Itaniums */
{ 7, -1, -1, -1, -1, 1, -1, -1, NO_CODE , 0, "Itanium" },
{ 15, -1, -1, 16, -1, 1, -1, -1, NO_CODE , 0, "Itanium 2" },
{ 7, -1, -1, -1, -1, 1, -1, -1, NO_CODE , 0, "Itanium" },
{ 15, -1, -1, 16, -1, 1, -1, -1, NO_CODE , 0, "Itanium 2" },
};
@ -654,7 +669,20 @@ static intel_code_t get_brand_code(struct cpu_id_t* data)
/* if it has RTM, then it is at least a Broadwell-E or Skylake */
if (data->flags[CPU_FEATURE_RDSEED])
core_ix_base = CORE_BROADWELL3;
switch (bs[i + 9]) {
case '3': code = core_ix_base + 0; break;
case '5': code = core_ix_base + 1; break;
case '7': code = core_ix_base + 2; break;
}
}
if ((i = match_pattern(bs, "Core(TM) m[357]")) != 0) {
/* Core m3, Core m5 or Core m7 */
need_matchtable = 0;
/* introduced in Skylake: Core m3 6Y30, Core m5 6Y54, Core m5 6Y57 and Core m7 6Y75 */
core_ix_base = CORE_SKYLAKEM3;
switch (bs[i + 9]) {
case '3': code = core_ix_base + 0; break;
case '5': code = core_ix_base + 1; break;

2
tests/run_tests.py
View file

@ -1,4 +1,4 @@
#!/usr/bin/python
#!/usr/bin/env python2.7
from __future__ import with_statement
import os, sys, re, random