mirror/libcpuid
1
0
Fork 0
mirror of https://github.com/anrieff/libcpuid synced 2025-06-07 00:51:40 +00:00
Code Issues Releases Wiki Activity

Add technology_node field to struct cpu_id_t

Browse source
This commit is contained in:
The Tumultuous Unicorn Of Darkness 2025-04-30 21:33:05 +02:00
parent 8ba8465bb1
commit 0ce318ee58
No known key found for this signature in database
GPG key ID: 1E55EE2EFF18BC1A
247 changed files with 1246 additions and 970 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
cpuid_tool/cpuid_tool.c
View file

@ -100,6 +100,7 @@ typedef enum {
NEED_L3_INSTANCES,
NEED_L4_INSTANCES,
NEED_CODENAME,
NEED_TECHNOLOGY,
NEED_FEATURES,
NEED_CLOCK,
NEED_CLOCK_OS,
@ -174,6 +175,7 @@ matchtable[] = {
{ NEED_L3_INSTANCES , "--l3-instances" , 1},
{ NEED_L4_INSTANCES , "--l4-instances" , 1},
{ NEED_CODENAME , "--codename" , 1},
{ NEED_TECHNOLOGY , "--technology" , 1},
{ NEED_FEATURES , "--flags" , 1},
{ NEED_CLOCK , "--clock" , 0},
{ NEED_CLOCK_OS , "--clock-os" , 0},
@ -507,6 +509,9 @@ static void print_info(output_data_switch query, struct cpu_id_t* data)
case NEED_CODENAME:
fprintf(fout, "%s\n", data->cpu_codename);
break;
case NEED_TECHNOLOGY:
fprintf(fout, "%s\n", data->technology_node);
break;
case NEED_FEATURES:
{
for (i = 0; i < NUM_CPU_FEATURES; i++)
@ -828,6 +833,7 @@ int main(int argc, char** argv)
fprintf(fout, " SSE units : %d bits (%s)\n", data.cpu_types[cpu_type_index].x86.sse_size, data.cpu_types[cpu_type_index].detection_hints[CPU_HINT_SSE_SIZE_AUTH] ? "authoritative" : "non-authoritative");
}
fprintf(fout, " code name : `%s'\n", data.cpu_types[cpu_type_index].cpu_codename);
fprintf(fout, " technology : `%s'\n", data.cpu_types[cpu_type_index].technology_node);
fprintf(fout, " features :");
/*
* Here we enumerate all CPU feature bits, and when a feature

3
libcpuid/libcpuid.h
View file

@ -755,6 +755,9 @@ struct cpu_id_t {
/** processor type purpose, relevant in case of hybrid CPU (e.g. PURPOSE_PERFORMANCE) */
cpu_purpose_t purpose;
/** contains the technology node string, e.g. "32 nm" */
char technology_node[TECHNOLOGY_STR_MAX];
};
/**

2
libcpuid/libcpuid_constants.h
View file

@ -35,6 +35,7 @@
#define VENDOR_STR_MAX 16
#define BRAND_STR_MAX 64
#define CODENAME_STR_MAX 64
#define TECHNOLOGY_STR_MAX 16
#define CPU_FLAGS_MAX 384
#define MAX_CPUID_LEVEL 32
#define MAX_EXT_CPUID_LEVEL 32
@ -60,6 +61,7 @@
#define SGX_FLAGS_MAX 14
#define ADDRESS_EXT_CPUID_START 0x80000000
#define ADDRESS_EXT_CPUID_END ADDRESS_EXT_CPUID_START + MAX_EXT_CPUID_LEVEL
#define UNKN_STR "unknown"
typedef enum {
EAX,

3
libcpuid/libcpuid_util.c
View file

@ -136,7 +136,8 @@ int match_cpu_codename(const struct match_entry_t* matchtable, int count, struct
bestindex = i;
}
}
strncpy(data->cpu_codename, matchtable[bestindex].name, CODENAME_STR_MAX);
strncpy(data->cpu_codename, matchtable[bestindex].name, CODENAME_STR_MAX);
strncpy(data->technology_node, matchtable[bestindex].technology, TECHNOLOGY_STR_MAX);
return bestscore;
}

1
libcpuid/libcpuid_util.h
View file

@ -48,6 +48,7 @@ struct match_entry_t {
int score;
} brand;
char name[CODENAME_STR_MAX];
char technology[TECHNOLOGY_STR_MAX];
};
// returns the match score:

559
libcpuid/recog_amd.c
View file

@ -35,346 +35,347 @@
const struct match_entry_t cpudb_amd[] = {
// F M S EF EM #cores L2$ L3$ Pattern Name
{ -1, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown AMD CPU" },
// F M S EF EM #cores L2$ L3$ Pattern Codename Technology
{ -1, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown AMD CPU", UNKN_STR },
/* 486 and the likes */
{ 4, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown AMD 486" },
{ 4, 3, -1, -1, -1, 1, -1, -1, { "", 0 }, "AMD 486DX2" },
{ 4, 7, -1, -1, -1, 1, -1, -1, { "", 0 }, "AMD 486DX2WB" },
{ 4, 8, -1, -1, -1, 1, -1, -1, { "", 0 }, "AMD 486DX4" },
{ 4, 9, -1, -1, -1, 1, -1, -1, { "", 0 }, "AMD 486DX4WB" },
{ 4, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown AMD 486", UNKN_STR },
{ 4, 3, -1, -1, -1, 1, -1, -1, { "", 0 }, "AMD 486DX2", UNKN_STR },
{ 4, 7, -1, -1, -1, 1, -1, -1, { "", 0 }, "AMD 486DX2WB", UNKN_STR },
{ 4, 8, -1, -1, -1, 1, -1, -1, { "", 0 }, "AMD 486DX4", UNKN_STR },
{ 4, 9, -1, -1, -1, 1, -1, -1, { "", 0 }, "AMD 486DX4WB", UNKN_STR },
/* Pentia clones */
{ 5, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown AMD 586" },
{ 5, 0, -1, -1, -1, 1, -1, -1, { "", 0 }, "K5" },
{ 5, 1, -1, -1, -1, 1, -1, -1, { "", 0 }, "K5" },
{ 5, 2, -1, -1, -1, 1, -1, -1, { "", 0 }, "K5" },
{ 5, 3, -1, -1, -1, 1, -1, -1, { "", 0 }, "K5" },
{ 5, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown AMD 586", UNKN_STR },
{ 5, 0, -1, -1, -1, 1, -1, -1, { "", 0 }, "K5", UNKN_STR },
{ 5, 1, -1, -1, -1, 1, -1, -1, { "", 0 }, "K5", UNKN_STR },
{ 5, 2, -1, -1, -1, 1, -1, -1, { "", 0 }, "K5", UNKN_STR },
{ 5, 3, -1, -1, -1, 1, -1, -1, { "", 0 }, "K5", UNKN_STR },
/* The K6 */
{ 5, 6, -1, -1, -1, 1, -1, -1, { "", 0 }, "K6" },
{ 5, 7, -1, -1, -1, 1, -1, -1, { "", 0 }, "K6" },
{ 5, 6, -1, -1, -1, 1, -1, -1, { "", 0 }, "K6", "350 nm" },
{ 5, 7, -1, -1, -1, 1, -1, -1, { "", 0 }, "K6 (Little Foot)", "250 nm" },
{ 5, 8, -1, -1, -1, 1, -1, -1, { "", 0 }, "K6-2" },
{ 5, 9, -1, -1, -1, 1, -1, -1, { "", 0 }, "K6-III" },
{ 5, 10, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown K6" },
{ 5, 11, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown K6" },
{ 5, 12, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown K6" },
{ 5, 13, -1, -1, -1, 1, -1, -1, { "", 0 }, "K6-2+" },
{ 5, 8, 0, -1, -1, 1, -1, -1, { "", 0 }, "K6-2 (Chomper)", "250 nm" },
{ 5, 8, 12, -1, -1, 1, -1, -1, { "", 0 }, "K6-2 (Chomper Extended)", "250 nm" },
{ 5, 9, -1, -1, -1, 1, -1, -1, { "", 0 }, "K6-III (Sharptooth)", "250 nm" },
{ 5, 10, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown K6", UNKN_STR },
{ 5, 11, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown K6", UNKN_STR },
{ 5, 12, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown K6", UNKN_STR },
{ 5, 13, -1, -1, -1, 1, -1, -1, { "", 0 }, "K6-2+", "180 nm" },
/* Athlon et al. */
{ 6, 1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Athlon (Slot-A)" },
{ 6, 2, -1, -1, -1, 1, -1, -1, { "", 0 }, "Athlon (Slot-A)" },
{ 6, 3, -1, -1, -1, 1, -1, -1, { "", 0 }, "Duron (Spitfire)" },
{ 6, 4, -1, -1, -1, 1, -1, -1, { "", 0 }, "Athlon (ThunderBird)" },
{ 6, 1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Athlon (Argon)", "250 nm" },
{ 6, 2, -1, -1, -1, 1, -1, -1, { "", 0 }, "Athlon (Pluto/Orion)", "180 nm" },
{ 6, 3, -1, -1, -1, 1, -1, -1, { "", 0 }, "Duron (Spitfire)", "180 nm" },
{ 6, 4, -1, -1, -1, 1, -1, -1, { "", 0 }, "Athlon (ThunderBird)", "180 nm" },
{ 6, 6, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown Athlon" },
{ 6, 6, -1, -1, -1, 1, -1, -1, { "Athlon", 2 }, "Athlon (Palomino)" },
{ 6, 6, -1, -1, -1, 1, -1, -1, { "Athlon(tm) MP", 4 }, "Athlon MP (Palomino)" },
{ 6, 6, -1, -1, -1, 1, -1, -1, { "Duron(tm)", 2 }, "Duron (Palomino)" },
{ 6, 6, -1, -1, -1, 1, -1, -1, { "Athlon(tm) XP", 4 }, "Athlon XP" },
{ 6, 6, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown Athlon", UNKN_STR },
{ 6, 6, -1, -1, -1, 1, -1, -1, { "Athlon", 2 }, "Athlon (Palomino)", "180 nm" },
{ 6, 6, -1, -1, -1, 1, -1, -1, { "Athlon(tm) MP", 4 }, "Athlon MP (Palomino)", "180 nm" },
{ 6, 6, -1, -1, -1, 1, -1, -1, { "Duron(tm)", 2 }, "Duron (Palomino)", "180 nm" },
{ 6, 6, -1, -1, -1, 1, -1, -1, { "Athlon(tm) XP", 4 }, "Athlon XP", UNKN_STR },
{ 6, 7, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown Athlon XP" },
{ 6, 7, -1, -1, -1, 1, -1, -1, { "Duron(tm)", 2 }, "Duron (Morgan)" },
{ 6, 7, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown Athlon XP", UNKN_STR },
{ 6, 7, -1, -1, -1, 1, -1, -1, { "Duron(tm)", 2 }, "Duron (Morgan)", "180 nm" },
{ 6, 8, -1, -1, -1, 1, -1, -1, { "", 0 }, "Athlon XP" },
{ 6, 8, -1, -1, -1, 1, -1, -1, { "Athlon", 2 }, "Athlon XP (Thoroughbred)" },
{ 6, 8, -1, -1, -1, 1, -1, -1, { "Athlon(tm) XP", 4 }, "Athlon XP (Thoroughbred)" },
{ 6, 8, -1, -1, -1, 1, -1, -1, { "Duron(tm)", 2 }, "Duron (Applebred)" },
{ 6, 8, -1, -1, -1, 1, -1, -1, { "Sempron(tm)", 2 }, "Sempron (Thoroughbred)" },
{ 6, 8, -1, -1, -1, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron (Thoroughbred)" },
{ 6, 8, -1, -1, -1, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron (Thoroughbred)" },
{ 6, 8, -1, -1, -1, 1, -1, -1, { "Athlon(tm) MP", 4 }, "Athlon MP (Thoroughbred)" },
{ 6, 8, -1, -1, -1, 1, -1, -1, { "Athlon(tm) XP-M", 6 }, "Mobile Athlon (T-Bred)" },
{ 6, 8, -1, -1, -1, 1, -1, -1, { "", 0 }, "Athlon XP", "130 nm" },
{ 6, 8, -1, -1, -1, 1, -1, -1, { "Athlon", 2 }, "Athlon XP (Thoroughbred)", "130 nm" },
{ 6, 8, -1, -1, -1, 1, -1, -1, { "Athlon(tm) XP", 4 }, "Athlon XP (Thoroughbred)", "130 nm" },
{ 6, 8, -1, -1, -1, 1, -1, -1, { "Duron(tm)", 2 }, "Duron (Applebred)", "130 nm" },
{ 6, 8, -1, -1, -1, 1, -1, -1, { "Sempron(tm)", 2 }, "Sempron (Thoroughbred)", "130 nm" },
{ 6, 8, -1, -1, -1, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron (Thoroughbred)", "130 nm" },
{ 6, 8, -1, -1, -1, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron (Thoroughbred)", "130 nm" },
{ 6, 8, -1, -1, -1, 1, -1, -1, { "Athlon(tm) MP", 4 }, "Athlon MP (Thoroughbred)", "130 nm" },
{ 6, 8, -1, -1, -1, 1, -1, -1, { "Athlon(tm) XP-M", 6 }, "Mobile Athlon (Thoroughbred)", "130 nm" },
{ 6, 10, -1, -1, -1, 1, -1, -1, { "", 0 }, "Athlon XP (Barton)" },
{ 6, 10, -1, -1, -1, 1, 512, -1, { "Athlon(tm) XP", 4 }, "Athlon XP (Barton)" },
{ 6, 10, -1, -1, -1, 1, 512, -1, { "Sempron(tm)", 2 }, "Sempron (Barton)" },
{ 6, 10, -1, -1, -1, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron (Thorton)" },
{ 6, 10, -1, -1, -1, 1, 256, -1, { "Athlon(tm) XP", 4 }, "Athlon XP (Thorton)" },
{ 6, 10, -1, -1, -1, 1, -1, -1, { "Athlon(tm) MP", 4 }, "Athlon MP (Barton)" },
{ 6, 10, -1, -1, -1, 1, -1, -1, { "Athlon(tm) XP-M", 6 }, "Mobile Athlon (Barton)" },
{ 6, 10, -1, -1, -1, 1, -1, -1, { "", 0 }, "Athlon XP (Barton)", "130 nm" },
{ 6, 10, -1, -1, -1, 1, 512, -1, { "Athlon(tm) XP", 4 }, "Athlon XP (Barton)", "130 nm" },
{ 6, 10, -1, -1, -1, 1, 512, -1, { "Sempron(tm)", 2 }, "Sempron (Barton)", "130 nm" },
{ 6, 10, -1, -1, -1, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron (Thorton)", "130 nm" },
{ 6, 10, -1, -1, -1, 1, 256, -1, { "Athlon(tm) XP", 4 }, "Athlon XP (Thorton)", "130 nm" },
{ 6, 10, -1, -1, -1, 1, -1, -1, { "Athlon(tm) MP", 4 }, "Athlon MP (Barton)", "130 nm" },
{ 6, 10, -1, -1, -1, 1, -1, -1, { "Athlon(tm) XP-M", 6 }, "Mobile Athlon (Barton)", "130 nm" },
/* K8 Architecture */
{ 15, -1, -1, 15, -1, 1, -1, -1, { "", 0 }, "Unknown K8" },
{ 15, -1, -1, 16, -1, 1, -1, -1, { "", 0 }, "Unknown K9" },
{ 15, -1, -1, 15, -1, 1, -1, -1, { "", 0 }, "Unknown K8", UNKN_STR },
{ 15, -1, -1, 16, -1, 1, -1, -1, { "", 0 }, "Unknown K9", UNKN_STR },
{ 15, -1, -1, 15, -1, 1, -1, -1, { "", 0 }, "Unknown A64" },
{ 15, -1, -1, 15, -1, 1, -1, -1, { "Opteron(tm)", 2 }, "Opteron" },
{ 15, -1, -1, 15, -1, 2, -1, -1, { "Dual Core AMD Opteron", 8 }, "Opteron (Dual Core)" },
{ 15, 3, -1, 15, -1, 1, -1, -1, { "Opteron(tm)", 2 }, "Opteron" },
{ 15, 3, -1, 15, -1, 2, -1, -1, { "Dual Core AMD Opteron", 8 }, "Opteron (Dual Core)" },
{ 15, -1, -1, 15, -1, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (512K)" },
{ 15, -1, -1, 15, -1, 1, 1024, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (1024K)" },
{ 15, -1, -1, 15, -1, 1, -1, -1, { "Athlon(tm) FX", 4 }, "Athlon FX" },
{ 15, -1, -1, 15, -1, 1, -1, -1, { "Athlon(tm) 64 FX", 6 }, "Athlon 64 FX" },
{ 15, 3, -1, 15, 35, 2, -1, -1, { "Athlon(tm) 64 FX", 6 }, "Athlon 64 FX X2 (Toledo)" },
{ 15, -1, -1, 15, -1, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (512K)" },
{ 15, -1, -1, 15, -1, 2, 1024, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (1024K)" },
{ 15, -1, -1, 15, -1, 1, 512, -1, { "Turion(tm) 64", 4 }, "Turion 64 (512K)" },
{ 15, -1, -1, 15, -1, 1, 1024, -1, { "Turion(tm) 64", 4 }, "Turion 64 (1024K)" },
{ 15, -1, -1, 15, -1, 2, 512, -1, { "Turion(tm) X2", 4 }, "Turion 64 X2 (512K)" },
{ 15, -1, -1, 15, -1, 2, 1024, -1, { "Turion(tm) X2", 4 }, "Turion 64 X2 (1024K)" },
{ 15, -1, -1, 15, -1, 1, 128, -1, { "Sempron(tm)", 2 }, "A64 Sempron (128K)" },
{ 15, -1, -1, 15, -1, 1, 256, -1, { "Sempron(tm)", 2 }, "A64 Sempron (256K)" },
{ 15, -1, -1, 15, -1, 1, 512, -1, { "Sempron(tm)", 2 }, "A64 Sempron (512K)" },
{ 15, -1, -1, 15, 0x4f, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Orleans/512K)" },
{ 15, -1, -1, 15, 0x5f, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Orleans/512K)" },
{ 15, -1, -1, 15, 0x2f, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Venice/512K)" },
{ 15, -1, -1, 15, 0x2c, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Venice/512K)" },
{ 15, -1, -1, 15, 0x1f, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Winchester/512K)" },
{ 15, -1, -1, 15, 0x0c, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Newcastle/512K)" },
{ 15, -1, -1, 15, 0x27, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (San Diego/512K)" },
{ 15, -1, -1, 15, 0x37, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (San Diego/512K)" },
{ 15, -1, -1, 15, 0x04, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (ClawHammer/512K)" },
{ 15, -1, -1, 15, -1, 1, -1, -1, { "", 0 }, "Unknown A64", UNKN_STR },
{ 15, -1, -1, 15, -1, 1, -1, -1, { "Opteron(tm)", 2 }, "Opteron", UNKN_STR },
{ 15, -1, -1, 15, -1, 2, -1, -1, { "Dual Core AMD Opteron", 8 }, "Opteron (Dual Core)", UNKN_STR },
{ 15, 3, -1, 15, -1, 1, -1, -1, { "Opteron(tm)", 2 }, "Opteron", UNKN_STR },
{ 15, 3, -1, 15, -1, 2, -1, -1, { "Dual Core AMD Opteron", 8 }, "Opteron (Dual Core)", UNKN_STR },
{ 15, -1, -1, 15, -1, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (512K)", UNKN_STR },
{ 15, -1, -1, 15, -1, 1, 1024, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (1024K)", UNKN_STR },
{ 15, -1, -1, 15, -1, 1, -1, -1, { "Athlon(tm) FX", 4 }, "Athlon FX", UNKN_STR },
{ 15, -1, -1, 15, -1, 1, -1, -1, { "Athlon(tm) 64 FX", 6 }, "Athlon 64 FX", UNKN_STR },
{ 15, 3, -1, 15, 35, 2, -1, -1, { "Athlon(tm) 64 FX", 6 }, "Athlon 64 FX X2 (Toledo)", "90 nm" },
{ 15, -1, -1, 15, -1, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (512K)", UNKN_STR },
{ 15, -1, -1, 15, -1, 2, 1024, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (1024K)", UNKN_STR },
{ 15, -1, -1, 15, -1, 1, 512, -1, { "Turion(tm) 64", 4 }, "Turion 64 (512K)", UNKN_STR },
{ 15, -1, -1, 15, -1, 1, 1024, -1, { "Turion(tm) 64", 4 }, "Turion 64 (1024K)", UNKN_STR },
{ 15, -1, -1, 15, -1, 2, 512, -1, { "Turion(tm) X2", 4 }, "Turion 64 X2 (512K)", UNKN_STR },
{ 15, -1, -1, 15, -1, 2, 1024, -1, { "Turion(tm) X2", 4 }, "Turion 64 X2 (1024K)", UNKN_STR },
{ 15, -1, -1, 15, -1, 1, 128, -1, { "Sempron(tm)", 2 }, "A64 Sempron (128K)", UNKN_STR },
{ 15, -1, -1, 15, -1, 1, 256, -1, { "Sempron(tm)", 2 }, "A64 Sempron (256K)", UNKN_STR },
{ 15, -1, -1, 15, -1, 1, 512, -1, { "Sempron(tm)", 2 }, "A64 Sempron (512K)", UNKN_STR },
{ 15, -1, -1, 15, 0x4f, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Orleans/512K)", "90 nm" },
{ 15, -1, -1, 15, 0x5f, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Orleans/512K)", "90 nm" },
{ 15, -1, -1, 15, 0x2f, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Venice/512K)", "90 nm" },
{ 15, -1, -1, 15, 0x2c, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Venice/512K)", "90 nm" },
{ 15, -1, -1, 15, 0x1f, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Winchester/512K)", "90 nm" },
{ 15, -1, -1, 15, 0x0c, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Newcastle/512K)", "130 nm" },
{ 15, -1, -1, 15, 0x27, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (San Diego/512K)", "90 nm" },
{ 15, -1, -1, 15, 0x37, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (San Diego/512K)", "90 nm" },
{ 15, -1, -1, 15, 0x04, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (ClawHammer/512K)", "130 nm" },
{ 15, -1, -1, 15, 0x5f, 1, 1024, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Orleans/1024K)" },
{ 15, -1, -1, 15, 0x27, 1, 1024, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (San Diego/1024K)" },
{ 15, -1, -1, 15, 0x04, 1, 1024, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (ClawHammer/1024K)" },
{ 15, -1, -1, 15, 0x5f, 1, 1024, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Orleans/1024K)", "90 nm" },
{ 15, -1, -1, 15, 0x27, 1, 1024, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (San Diego/1024K)", "90 nm" },
{ 15, -1, -1, 15, 0x04, 1, 1024, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (ClawHammer/1024K)", "130 nm" },
{ 15, -1, -1, 15, 0x4b, 2, 256, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Windsor/256K)" },
{ 15, -1, -1, 15, 0x4b, 2, 256, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Windsor/256K)", "90 nm" },
{ 15, -1, -1, 15, 0x23, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Toledo/512K)" },
{ 15, -1, -1, 15, 0x4b, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Windsor/512K)" },
{ 15, -1, -1, 15, 0x43, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Windsor/512K)" },
{ 15, -1, -1, 15, 0x6b, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Brisbane/512K)" },
{ 15, -1, -1, 15, 0x2b, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Manchester/512K)"},
{ 15, -1, -1, 15, 0x23, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Toledo/512K)", "90 nm" },
{ 15, -1, -1, 15, 0x4b, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Windsor/512K)", "90 nm" },
{ 15, -1, -1, 15, 0x43, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Windsor/512K)", "90 nm" },
{ 15, -1, -1, 15, 0x6b, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Brisbane/512K)", "65 nm" },
{ 15, -1, -1, 15, 0x2b, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Manchester/512K)", "90 nm" },
{ 15, -1, -1, 15, 0x23, 2, 1024, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Toledo/1024K)" },
{ 15, -1, -1, 15, 0x43, 2, 1024, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Windsor/1024K)" },
{ 15, -1, -1, 15, 0x23, 2, 1024, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Toledo/1024K)", "90 nm" },
{ 15, -1, -1, 15, 0x43, 2, 1024, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Windsor/1024K)", "90 nm" },
{ 15, -1, -1, 15, 0x08, 1, 128, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Dublin/128K)"},
{ 15, -1, -1, 15, 0x08, 1, 256, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Dublin/256K)"},
{ 15, -1, -1, 15, 0x0c, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Paris)" },
{ 15, -1, -1, 15, 0x1c, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/128K)" },
{ 15, -1, -1, 15, 0x1c, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/256K)" },
{ 15, -1, -1, 15, 0x1c, 1, 128, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Sonora/128K)"},
{ 15, -1, -1, 15, 0x1c, 1, 256, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Sonora/256K)"},
{ 15, -1, -1, 15, 0x2c, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/128K)" },
{ 15, -1, -1, 15, 0x2c, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/256K)" },
{ 15, -1, -1, 15, 0x2c, 1, 128, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Albany/128K)"},
{ 15, -1, -1, 15, 0x2c, 1, 256, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Albany/256K)"},
{ 15, -1, -1, 15, 0x2f, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/128K)" },
{ 15, -1, -1, 15, 0x2f, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/256K)" },
{ 15, -1, -1, 15, 0x4f, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Manila/128K)" },
{ 15, -1, -1, 15, 0x4f, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Manila/256K)" },
{ 15, -1, -1, 15, 0x5f, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Manila/128K)" },
{ 15, -1, -1, 15, 0x5f, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Manila/256K)" },
{ 15, -1, -1, 15, 0x6b, 2, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 Dual (Sherman/256K)"},
{ 15, -1, -1, 15, 0x6b, 2, 512, -1, { "Sempron(tm)", 2 }, "Sempron 64 Dual (Sherman/512K)"},
{ 15, -1, -1, 15, 0x7c, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Sherman/512K)" },
{ 15, -1, -1, 15, 0x7f, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Sparta/256K)" },
{ 15, -1, -1, 15, 0x7f, 1, 512, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Sparta/512K)" },
{ 15, -1, -1, 15, 0x4c, 1, 256, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Keene/256K)"},
{ 15, -1, -1, 15, 0x4c, 1, 512, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Keene/512K)"},
{ 15, -1, -1, 15, 0x08, 1, 128, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Dublin/128K)", "130 nm" },
{ 15, -1, -1, 15, 0x08, 1, 256, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Dublin/256K)", "130 nm" },
{ 15, -1, -1, 15, 0x0c, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Paris)", "130 nm" },
{ 15, -1, -1, 15, 0x1c, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/128K)", "90 nm" },
{ 15, -1, -1, 15, 0x1c, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/256K)", "90 nm" },
{ 15, -1, -1, 15, 0x1c, 1, 128, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Sonora/128K)", "90 nm" },
{ 15, -1, -1, 15, 0x1c, 1, 256, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Sonora/256K)", "90 nm" },
{ 15, -1, -1, 15, 0x2c, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/128K)", "90 nm" },
{ 15, -1, -1, 15, 0x2c, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/256K)", "90 nm" },
{ 15, -1, -1, 15, 0x2c, 1, 128, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Albany/128K)", "90 nm" },
{ 15, -1, -1, 15, 0x2c, 1, 256, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Albany/256K)", "90 nm" },
{ 15, -1, -1, 15, 0x2f, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/128K)", "90 nm" },
{ 15, -1, -1, 15, 0x2f, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/256K)", "90 nm" },
{ 15, -1, -1, 15, 0x4f, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Manila/128K)", "90 nm" },
{ 15, -1, -1, 15, 0x4f, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Manila/256K)", "90 nm" },
{ 15, -1, -1, 15, 0x5f, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Manila/128K)", "90 nm" },
{ 15, -1, -1, 15, 0x5f, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Manila/256K)", "90 nm" },
{ 15, -1, -1, 15, 0x6b, 2, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 Dual (Sherman/256K)", "65 nm" },
{ 15, -1, -1, 15, 0x6b, 2, 512, -1, { "Sempron(tm)", 2 }, "Sempron 64 Dual (Sherman/512K)", "65 nm" },
{ 15, -1, -1, 15, 0x7c, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Sherman/512K)", "65 nm" },
{ 15, -1, -1, 15, 0x7f, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Sparta/256K)", "65 nm" },
{ 15, -1, -1, 15, 0x7f, 1, 512, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Sparta/512K)", "65 nm" },
{ 15, -1, -1, 15, 0x4c, 1, 256, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Keene/256K)", "90 nm" },
{ 15, -1, -1, 15, 0x4c, 1, 512, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Keene/512K)", "90 nm" },
{ 15, -1, -1, 15, 0x24, 1, 512, -1, { "Turion(tm) 64", 4 }, "Turion 64 (Lancaster/512K)" },
{ 15, -1, -1, 15, 0x24, 1, 1024, -1, { "Turion(tm) 64", 4 }, "Turion 64 (Lancaster/1024K)" },
{ 15, -1, -1, 15, 0x48, 2, 256, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Taylor)" },
{ 15, -1, -1, 15, 0x48, 2, 512, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Trinidad)" },
{ 15, -1, -1, 15, 0x4c, 1, 512, -1, { "Turion(tm) 64", 4 }, "Turion 64 (Richmond)" },
{ 15, -1, -1, 15, 0x68, 2, 256, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Tyler/256K)" },
{ 15, -1, -1, 15, 0x68, 2, 512, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Tyler/512K)" },
{ 15, -1, -1, 17, 3, 2, 512, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Griffin/512K)" },
{ 15, -1, -1, 17, 3, 2, 1024, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Griffin/1024K)" },
{ 15, -1, -1, 15, 0x24, 1, 512, -1, { "Turion(tm) 64", 4 }, "Turion 64 (Lancaster/512K)", "90 nm" },
{ 15, -1, -1, 15, 0x24, 1, 1024, -1, { "Turion(tm) 64", 4 }, "Turion 64 (Lancaster/1024K)", "90 nm" },
{ 15, -1, -1, 15, 0x48, 2, 256, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Taylor)", "90 nm" },
{ 15, -1, -1, 15, 0x48, 2, 512, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Trinidad)", "90 nm" },
{ 15, -1, -1, 15, 0x4c, 1, 512, -1, { "Turion(tm) 64", 4 }, "Turion 64 (Richmond)", "90 nm" },
{ 15, -1, -1, 15, 0x68, 2, 256, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Tyler/256K)", "65 nm" },
{ 15, -1, -1, 15, 0x68, 2, 512, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Tyler/512K)", "65 nm" },
{ 15, -1, -1, 17, 3, 2, 512, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Griffin/512K)", "65 nm" },
{ 15, -1, -1, 17, 3, 2, 1024, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Griffin/1024K)", "65 nm" },
/* K10 Architecture (2007) */
{ 15, 2, -1, 16, -1, 3, -1, -1, { "Phenom(tm)", 2 }, "Phenom X3 (Toliman)" },
{ 15, 2, -1, 16, -1, 4, -1, -1, { "Phenom(tm)", 2 }, "Phenom X4 (Agena)" },
{ 15, 2, -1, 16, -1, 3, 512, -1, { "Phenom(tm)", 2 }, "Phenom X3 (Toliman/256K)" },
{ 15, 2, -1, 16, -1, 3, 512, -1, { "Phenom(tm)", 2 }, "Phenom X3 (Toliman/512K)" },
{ 15, 2, -1, 16, -1, 4, 128, -1, { "Phenom(tm)", 2 }, "Phenom X4 (Agena/128K)" },
{ 15, 2, -1, 16, -1, 4, 256, -1, { "Phenom(tm)", 2 }, "Phenom X4 (Agena/256K)" },
{ 15, 2, -1, 16, -1, 4, 512, -1, { "Phenom(tm)", 2 }, "Phenom X4 (Agena/512K)" },
{ 15, 2, -1, 16, -1, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon X2 (Kuma)" },
{ 15, 2, -1, 16, -1, 3, -1, -1, { "Phenom(tm)", 2 }, "Phenom X3 (Toliman)", "65 nm" },
{ 15, 2, -1, 16, -1, 4, -1, -1, { "Phenom(tm)", 2 }, "Phenom X4 (Agena)", "65 nm" },
{ 15, 2, -1, 16, -1, 3, 512, -1, { "Phenom(tm)", 2 }, "Phenom X3 (Toliman/256K)", "65 nm" },
{ 15, 2, -1, 16, -1, 3, 512, -1, { "Phenom(tm)", 2 }, "Phenom X3 (Toliman/512K)", "65 nm" },
{ 15, 2, -1, 16, -1, 4, 128, -1, { "Phenom(tm)", 2 }, "Phenom X4 (Agena/128K)", "65 nm" },
{ 15, 2, -1, 16, -1, 4, 256, -1, { "Phenom(tm)", 2 }, "Phenom X4 (Agena/256K)", "65 nm" },
{ 15, 2, -1, 16, -1, 4, 512, -1, { "Phenom(tm)", 2 }, "Phenom X4 (Agena/512K)", "65 nm" },
{ 15, 2, -1, 16, -1, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon X2 (Kuma)", "65 nm" },
/* Phenom II derivates: */
{ 15, 4, -1, 16, -1, 1, 1024, -1, { "Sempron(tm)", 2 }, "Sempron (Sargas)" },
{ 15, 4, -1, 16, -1, 2, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X2 (Callisto)" },
{ 15, 4, -1, 16, -1, 3, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X3 (Heka)" },
{ 15, 4, -1, 16, 4, 4, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X4 (Deneb)" },
{ 15, 5, -1, 16, 5, 4, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X4 (Deneb)" },
{ 15, 4, -1, 16, 10, 4, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X4 (Zosma)" },
{ 15, 4, -1, 16, 10, 6, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X6 (Thuban)" },
{ 15, 4, -1, 16, -1, 1, 1024, -1, { "Sempron(tm)", 2 }, "Sempron (Sargas)", "45 nm" },
{ 15, 4, -1, 16, -1, 2, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X2 (Callisto)", "45 nm" },
{ 15, 4, -1, 16, -1, 3, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X3 (Heka)", "45 nm" },
{ 15, 4, -1, 16, 4, 4, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X4 (Deneb)", "45 nm" },
{ 15, 5, -1, 16, 5, 4, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X4 (Deneb)", "45 nm" },
{ 15, 4, -1, 16, 10, 4, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X4 (Zosma)", "45 nm" },
{ 15, 4, -1, 16, 10, 6, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X6 (Thuban)", "45 nm" },
/* Athlon II derivates: */
{ 15, 6, -1, 16, 6, 2, 512, -1, { "Athlon(tm) II", 4 }, "Athlon II (Champlain)" },
{ 15, 6, -1, 16, 6, 2, 512, -1, { "Athlon(tm) II X2", 6 }, "Athlon II X2 (Regor)" },
{ 15, 6, -1, 16, 6, 2, 1024, -1, { "Athlon(tm) II X2", 6 }, "Athlon II X2 (Regor)" },
{ 15, 5, -1, 16, 5, 3, 512, -1, { "Athlon(tm) II X3", 6 }, "Athlon II X3 (Rana)" },
{ 15, 5, -1, 16, 5, 4, 512, -1, { "Athlon(tm) X4", 4 }, "Athlon II X4 (Propus)" },
{ 15, 5, -1, 16, 5, 4, 512, -1, { "Athlon(tm) II X4", 6 }, "Athlon II X4 (Propus)" },
{ 15, 6, -1, 16, 6, 2, 512, -1, { "Athlon(tm) II", 4 }, "Athlon II (Champlain)", "45 nm" },
{ 15, 6, -1, 16, 6, 2, 512, -1, { "Athlon(tm) II X2", 6 }, "Athlon II X2 (Regor)", "45 nm" },
{ 15, 6, -1, 16, 6, 2, 1024, -1, { "Athlon(tm) II X2", 6 }, "Athlon II X2 (Regor)", "45 nm" },
{ 15, 5, -1, 16, 5, 3, 512, -1, { "Athlon(tm) II X3", 6 }, "Athlon II X3 (Rana)", "45 nm" },
{ 15, 5, -1, 16, 5, 4, 512, -1, { "Athlon(tm) X4", 4 }, "Athlon II X4 (Propus)", "45 nm" },
{ 15, 5, -1, 16, 5, 4, 512, -1, { "Athlon(tm) II X4", 6 }, "Athlon II X4 (Propus)", "45 nm" },
/* Opteron derivates: */
{ 15, 9, -1, 22, 9, 8, -1, -1, { "Opteron(tm)", 2 }, "Opteron (Magny-Cours)" },
{ 15, 9, -1, 22, 9, 8, -1, -1, { "Opteron(tm)", 2 }, "Opteron (Magny-Cours)", "45 nm" },
/* Llano APUs (2011): */
{ 15, 1, -1, 18, 1, -1, -1, -1, { "E2-3###", 4 }, "E-Series (Llano)" },
{ 15, 1, -1, 18, 1, -1, -1, -1, { "A[468]-3###", 4 }, "A-Series (Llano)" },
{ 15, 1, -1, 18, 1, -1, -1, -1, { "E2-3###", 4 }, "E-Series (Llano)", "GF 32SHP" },
{ 15, 1, -1, 18, 1, -1, -1, -1, { "A[468]-3###", 4 }, "A-Series (Llano)", "GF 32SHP" },
/* Family 14h: Bobcat Architecture (2011) */
{ 15, 2, -1, 20, -1, -1, -1, -1, { "C([356]#", 4 }, "C-Series (Ontario)" },
{ 15, 1, -1, 20, -1, -1, -1, -1, { "E-[234]##", 4 }, "E-Series (Zacate)" },
{ 15, 2, -1, 20, -1, -1, -1, -1, { "Z-##", 4 }, "Z-Series (Desna)" },
{ 15, 2, -1, 20, -1, -1, -1, -1, { "C([356]#", 4 }, "C-Series (Ontario)", "TSMC N40" },
{ 15, 1, -1, 20, -1, -1, -1, -1, { "E-[234]##", 4 }, "E-Series (Zacate)", "TSMC N40" },
{ 15, 2, -1, 20, -1, -1, -1, -1, { "Z-##", 4 }, "Z-Series (Desna)", "TSMC N40" },
/* Family 15h: Bulldozer Architecture (2011) */
{ 15, -1, -1, 21, 0, -1, -1, -1, { "FX(tm)-[468]###", 4 }, "FX (Zambezi)" },
{ 15, -1, -1, 21, 1, -1, -1, -1, { "FX(tm)-[468]###", 4 }, "FX (Zambezi)" },
{ 15, -1, -1, 21, 1, -1, -1, -1, { "Opteron(tm)", 2 }, "Opteron (Interlagos)" },
{ 15, -1, -1, 21, 0, -1, -1, -1, { "FX(tm)-[468]###", 4 }, "FX (Zambezi)", "GF 32SHP" },
{ 15, -1, -1, 21, 1, -1, -1, -1, { "FX(tm)-[468]###", 4 }, "FX (Zambezi)", "GF 32SHP" },
{ 15, -1, -1, 21, 1, -1, -1, -1, { "Opteron(tm)", 2 }, "Opteron (Interlagos)", "GF 32SHP" },
/* 2nd-gen, Piledriver core (2012): */
{ 15, -1, -1, 21, 2, -1, -1, -1, { "FX(tm)-[4689]###", 4 }, "FX (Vishera)" },
{ 15, 0, -1, 21, 16, -1, -1, -1, { "A[468]-4###", 4 }, "A-Series (Trinity)" },
{ 15, 0, -1, 21, 16, -1, -1, -1, { "A10-4###", 4 }, "A-Series (Trinity)" },
{ 15, 0, -1, 21, 19, -1, -1, -1, { "A[468]-5###", 4 }, "A-Series (Richland)" },
{ 15, 0, -1, 21, 19, -1, -1, -1, { "A10-5###", 4 }, "A-Series (Richland)" },
{ 15, 2, -1, 21, 2, -1, -1, -1, { "Opteron(tm)", 2 }, "Opteron (Abu Dhabi)" },
{ 15, -1, -1, 21, 2, -1, -1, -1, { "FX(tm)-[4689]###", 4 }, "FX (Vishera)", "GF 32SHP" },
{ 15, 0, -1, 21, 16, -1, -1, -1, { "A[468]-4###", 4 }, "A-Series (Trinity)", "GF 32SHP" },
{ 15, 0, -1, 21, 16, -1, -1, -1, { "A10-4###", 4 }, "A-Series (Trinity)", "GF 32SHP" },
{ 15, 0, -1, 21, 19, -1, -1, -1, { "A[468]-5###", 4 }, "A-Series (Richland)", "GF 32SHP" },
{ 15, 0, -1, 21, 19, -1, -1, -1, { "A10-5###", 4 }, "A-Series (Richland)", "GF 32SHP" },
{ 15, 2, -1, 21, 2, -1, -1, -1, { "Opteron(tm)", 2 }, "Opteron (Abu Dhabi)", "GF 32SHP" },
/* 3rd-gen, Steamroller core (2014): */
{ 15, 8, -1, 21, 48, -1, -1, -1, { "A[468-[78]###", 4 }, "A-Series (Kaveri)" },
{ 15, 8, -1, 21, 48, -1, -1, -1, { "A10-[78]###", 4 }, "A-Series (Kaveri)" },
{ 15, 8, -1, 21, 48, 2, -1, -1, { "Athlon(tm) X2", 4 }, "Athlon X2 (Kaveri)" },
{ 15, 8, -1, 21, 48, 4, -1, -1, { "Athlon(tm) X4", 4 }, "Athlon X4 (Kaveri)" },
{ 15, 8, -1, 21, 56, -1, -1, -1, { "A[468-[78]###", 4 }, "A-Series (Godavari)" },
{ 15, 8, -1, 21, 56, -1, -1, -1, { "A10-[78]###", 4 }, "A-Series (Godavari)" },
{ 15, 8, -1, 21, 56, 4, -1, -1, { "Athlon(tm) X4", 4 }, "Athlon X4 (Godavari)" },
{ 15, 0, -1, 21, 48, -1, -1, -1, { "RX-###", 4 }, "R-Series (Bald Eagle)" },
{ 15, 8, -1, 21, 48, -1, -1, -1, { "A[468-[78]###", 4 }, "A-Series (Kaveri)", "TSMC N28" },
{ 15, 8, -1, 21, 48, -1, -1, -1, { "A10-[78]###", 4 }, "A-Series (Kaveri)", "TSMC N28" },
{ 15, 8, -1, 21, 48, 2, -1, -1, { "Athlon(tm) X2", 4 }, "Athlon X2 (Kaveri)", "TSMC N28" },
{ 15, 8, -1, 21, 48, 4, -1, -1, { "Athlon(tm) X4", 4 }, "Athlon X4 (Kaveri)", "TSMC N28" },
{ 15, 8, -1, 21, 56, -1, -1, -1, { "A[468-[78]###", 4 }, "A-Series (Godavari)", "TSMC N28" },
{ 15, 8, -1, 21, 56, -1, -1, -1, { "A10-[78]###", 4 }, "A-Series (Godavari)", "TSMC N28" },
{ 15, 8, -1, 21, 56, 4, -1, -1, { "Athlon(tm) X4", 4 }, "Athlon X4 (Godavari)", "TSMC N28" },
{ 15, 0, -1, 21, 48, -1, -1, -1, { "RX-###", 4 }, "R-Series (Bald Eagle)", "TSMC N28" },
/* 4th-gen, Excavator core (2015): */
{ 15, 1, -1, 21, 96, -1, -1, -1, { "A[68]-8###", 4 }, "A-Series (Carrizo)" },
{ 15, 1, -1, 21, 96, -1, -1, -1, { "A1[02]-8###", 4 }, "A-Series (Carrizo)" },
{ 15, 5, -1, 21, 101, -1, -1, -1, { "A[68]-9###", 4 }, "A-Series (Bristol Ridge)" },
{ 15, 5, -1, 21, 101, -1, -1, -1, { "A1[02]-9###", 4 }, "A-Series (Bristol Ridge)" },
{ 15, 0, -1, 21, 112, 2, -1, -1, { "A[469]-9###", 4 }, "A-Series (Stoney Ridge)" },
{ 15, 0, -1, 21, 112, -1, -1, -1, { "E2-9###", 4 }, "E-Series (Stoney Ridge)" },
{ 15, 1, -1, 21, 96, -1, -1, -1, { "A[68]-8###", 4 }, "A-Series (Carrizo)", "GF 28SHP" },
{ 15, 1, -1, 21, 96, -1, -1, -1, { "A1[02]-8###", 4 }, "A-Series (Carrizo)", "GF 28SHP" },
{ 15, 5, -1, 21, 101, -1, -1, -1, { "A[68]-9###", 4 }, "A-Series (Bristol Ridge)", "GF 28SHP" },
{ 15, 5, -1, 21, 101, -1, -1, -1, { "A1[02]-9###", 4 }, "A-Series (Bristol Ridge)", "GF 28SHP" },
{ 15, 0, -1, 21, 112, 2, -1, -1, { "A[469]-9###", 4 }, "A-Series (Stoney Ridge)", "GF 28SHP" },
{ 15, 0, -1, 21, 112, -1, -1, -1, { "E2-9###", 4 }, "E-Series (Stoney Ridge)", "GF 28SHP" },
/* Family 16h: Jaguar Architecture (2013) */
{ 15, 0, -1, 22, 0, -1, -1, -1, { "E1-2###", 4 }, "E-Series (Kabini)" },
{ 15, 0, -1, 22, 0, -1, -1, -1, { "E2-3###", 4 }, "E-Series (Kabini)" },
{ 15, 0, -1, 22, 0, -1, -1, -1, { "A[46]-5###", 4 }, "A-Series (Kabini)" },
{ 15, 0, -1, 22, 0, -1, -1, -1, { "A4 PRO-3###", 6 }, "A-Series (Kabini)" },
{ 15, 0, -1, 22, 0, -1, -1, -1, { "Sempron(tm)", 2 }, "Sempron (Kabini)" },
{ 15, 0, -1, 22, 0, 4, -1, -1, { "Athlon(tm) 5###", 4 }, "Athlon X4 (Kabini)" },
{ 15, 0, -1, 22, 0, 4, -1, -1, { "Athlon(tm) X4", 4 }, "Athlon X4 (Kabini)" },
{ 15, 0, -1, 22, 0, -1, -1, -1, { "E1-2###", 4 }, "E-Series (Kabini)", "TSMC N28" },
{ 15, 0, -1, 22, 0, -1, -1, -1, { "E2-3###", 4 }, "E-Series (Kabini)", "TSMC N28" },
{ 15, 0, -1, 22, 0, -1, -1, -1, { "A[46]-5###", 4 }, "A-Series (Kabini)", "TSMC N28" },
{ 15, 0, -1, 22, 0, -1, -1, -1, { "A4 PRO-3###", 6 }, "A-Series (Kabini)", "TSMC N28" },
{ 15, 0, -1, 22, 0, -1, -1, -1, { "Sempron(tm)", 2 }, "Sempron (Kabini)", "TSMC N28" },
{ 15, 0, -1, 22, 0, 4, -1, -1, { "Athlon(tm) 5###", 4 }, "Athlon X4 (Kabini)", "TSMC N28" },
{ 15, 0, -1, 22, 0, 4, -1, -1, { "Athlon(tm) X4", 4 }, "Athlon X4 (Kabini)", "TSMC N28" },
/* 2nd-gen, Puma core (2013): */
{ 15, 0, -1, 22, 48, 2, -1, -1, { "E1 Micro-62##T", 8 }, "E-Series (Mullins)" },
{ 15, 0, -1, 22, 48, 4, -1, -1, { "A4 Micro-64##T", 8 }, "A-Series (Mullins)" },
{ 15, 0, -1, 22, 48, 4, -1, -1, { "A10 Micro-67##T", 8 }, "A-Series (Mullins)" },
{ 15, 0, 1, 22, 48, -1, -1, -1, { "E[12]-6###", 4 }, "E-Series (Beema)" },
{ 15, 0, 1, 22, 48, -1, -1, -1, { "A[468]-6###", 4 }, "A-Series (Beema)" },
{ 15, 0, 1, 22, 48, -1, -1, -1, { "GX-###", 4 }, "G-Series (Steppe Eagle)" },
{ 15, 0, -1, 22, 48, 2, -1, -1, { "E1 Micro-62##T", 8 }, "E-Series (Mullins)", "GF 28SHP" },
{ 15, 0, -1, 22, 48, 4, -1, -1, { "A4 Micro-64##T", 8 }, "A-Series (Mullins)", "GF 28SHP" },
{ 15, 0, -1, 22, 48, 4, -1, -1, { "A10 Micro-67##T", 8 }, "A-Series (Mullins)", "GF 28SHP" },
{ 15, 0, 1, 22, 48, -1, -1, -1, { "E[12]-6###", 4 }, "E-Series (Beema)", "GF 28SHP" },
{ 15, 0, 1, 22, 48, -1, -1, -1, { "A[468]-6###", 4 }, "A-Series (Beema)", "GF 28SHP" },
{ 15, 0, 1, 22, 48, -1, -1, -1, { "GX-###", 4 }, "G-Series (Steppe Eagle)", "GF 28SHP" },
/* Family 17h */
/* Zen (2017) => https://en.wikichip.org/wiki/amd/microarchitectures/zen */
{ 15, -1, -1, 23, 1, -1, -1, -1, { "EPYC 7##1", 4 }, "EPYC (Naples)" },
{ 15, -1, -1, 23, 1, -1, -1, -1, { "Threadripper 1###", 4 }, "Threadripper (Whitehaven)" },
{ 15, -1, -1, 23, 1, -1, -1, -1, { "Ryzen 7 1###", 6 }, "Ryzen 7 (Summit Ridge)" },
{ 15, -1, -1, 23, 1, -1, -1, -1, { "Ryzen 5 1###", 6 }, "Ryzen 5 (Summit Ridge)" },
{ 15, -1, -1, 23, 1, -1, -1, -1, { "Ryzen 3 1###", 6 }, "Ryzen 3 (Summit Ridge)" },
{ 15, -1, -1, 23, 17, -1, -1, -1, { "Ryzen 7 2###", 6 }, "Ryzen 7 (Raven Ridge)" },
{ 15, -1, -1, 23, 17, -1, -1, -1, { "Ryzen 5 2###", 6 }, "Ryzen 5 (Raven Ridge)" },
{ 15, -1, -1, 23, 17, -1, -1, -1, { "Ryzen 3 2###", 6 }, "Ryzen 3 (Raven Ridge)" },
{ 15, -1, -1, 23, 17, -1, -1, -1, { "Athlon", 2 }, "Athlon (Raven Ridge)" },
{ 15, -1, -1, 23, 32, -1, -1, -1, { "Ryzen 3 3###", 6 }, "Ryzen 3 (Dali)" },
{ 15, -1, -1, 23, 32, -1, -1, -1, { "Athlon", 2 }, "Athlon (Dali)" },
{ 15, -1, 1, 23, 32, -1, -1, -1, { "", 0 }, "Dali" }, /* AMD 3020e */
{ 15, -1, -1, 23, 1, -1, -1, -1, { "EPYC 7##1", 4 }, "EPYC (Naples)", "GF 14LP" },
{ 15, -1, -1, 23, 1, -1, -1, -1, { "Threadripper 1###", 4 }, "Threadripper (Whitehaven)", "GF 14LP" },
{ 15, -1, -1, 23, 1, -1, -1, -1, { "Ryzen 7 1###", 6 }, "Ryzen 7 (Summit Ridge)", "GF 14LP" },
{ 15, -1, -1, 23, 1, -1, -1, -1, { "Ryzen 5 1###", 6 }, "Ryzen 5 (Summit Ridge)", "GF 14LP" },
{ 15, -1, -1, 23, 1, -1, -1, -1, { "Ryzen 3 1###", 6 }, "Ryzen 3 (Summit Ridge)", "GF 14LP" },
{ 15, -1, -1, 23, 17, -1, -1, -1, { "Ryzen 7 2###", 6 }, "Ryzen 7 (Raven Ridge)", "GF 14LP" },
{ 15, -1, -1, 23, 17, -1, -1, -1, { "Ryzen 5 2###", 6 }, "Ryzen 5 (Raven Ridge)", "GF 14LP" },
{ 15, -1, -1, 23, 17, -1, -1, -1, { "Ryzen 3 2###", 6 }, "Ryzen 3 (Raven Ridge)", "GF 14LP" },
{ 15, -1, -1, 23, 17, -1, -1, -1, { "Athlon", 2 }, "Athlon (Raven Ridge)", "GF 14LP" },
{ 15, -1, -1, 23, 32, -1, -1, -1, { "Ryzen 3 3###", 6 }, "Ryzen 3 (Dali)", "GF 14LP" },
{ 15, -1, -1, 23, 32, -1, -1, -1, { "Athlon", 2 }, "Athlon (Dali)", "GF 14LP" },
{ 15, -1, 1, 23, 32, -1, -1, -1, { "", 0 }, "Dali", "GF 14LP" }, /* AMD 3020e */
/* Zen+ (2018) => https://en.wikichip.org/wiki/amd/microarchitectures/zen%2B */
{ 15, -1, -1, 23, 8, -1, -1, -1, { "Threadripper 2###", 4 }, "Threadripper (Colfax)" },
{ 15, -1, -1, 23, 8, -1, -1, -1, { "Ryzen 7 2###", 6 }, "Ryzen 7 (Pinnacle Ridge)" },
{ 15, -1, -1, 23, 8, -1, -1, -1, { "Ryzen 5 2###", 6 }, "Ryzen 5 (Pinnacle Ridge)" },
{ 15, -1, -1, 23, 8, -1, -1, -1, { "Ryzen 3 2###", 6 }, "Ryzen 3 (Pinnacle Ridge)" },
{ 15, -1, -1, 23, 24, -1, -1, -1, { "Ryzen 7 3###", 6 }, "Ryzen 7 (Picasso)" },
{ 15, -1, -1, 23, 24, -1, -1, -1, { "Ryzen 5 3###", 6 }, "Ryzen 5 (Picasso)" },
{ 15, -1, -1, 23, 24, -1, -1, -1, { "Ryzen 3 3###", 6 }, "Ryzen 3 (Picasso)" },
{ 15, -1, -1, 23, 24, -1, -1, -1, { "Athlon", 2 }, "Athlon (Picasso)" },
{ 15, -1, -1, 23, 8, -1, -1, -1, { "Threadripper 2###", 4 }, "Threadripper (Colfax)", "GF 12LP" },
{ 15, -1, -1, 23, 8, -1, -1, -1, { "Ryzen 7 2###", 6 }, "Ryzen 7 (Pinnacle Ridge)", "GF 12LP" },
{ 15, -1, -1, 23, 8, -1, -1, -1, { "Ryzen 5 2###", 6 }, "Ryzen 5 (Pinnacle Ridge)", "GF 12LP" },
{ 15, -1, -1, 23, 8, -1, -1, -1, { "Ryzen 3 2###", 6 }, "Ryzen 3 (Pinnacle Ridge)", "GF 12LP" },
{ 15, -1, -1, 23, 24, -1, -1, -1, { "Ryzen 7 3###", 6 }, "Ryzen 7 (Picasso)", "GF 12LP" },
{ 15, -1, -1, 23, 24, -1, -1, -1, { "Ryzen 5 3###", 6 }, "Ryzen 5 (Picasso)", "GF 12LP" },
{ 15, -1, -1, 23, 24, -1, -1, -1, { "Ryzen 3 3###", 6 }, "Ryzen 3 (Picasso)", "GF 12LP" },
{ 15, -1, -1, 23, 24, -1, -1, -1, { "Athlon", 2 }, "Athlon (Picasso)", "GF 12LP" },
/* Zen 2 (2019) => https://en.wikichip.org/wiki/amd/microarchitectures/zen_2 */
{ 15, -1, -1, 23, 49, -1, -1, -1, { "EPYC 7##2", 4 }, "EPYC (Rome)" },
{ 15, -1, -1, 23, 49, -1, -1, -1, { "Threadripper 3###", 4 }, "Threadripper (Castle Peak)" },
{ 15, -1, -1, 23, 113, -1, -1, -1, { "Ryzen 9 3###", 6 }, "Ryzen 9 (Matisse)" },
{ 15, -1, -1, 23, 113, -1, -1, -1, { "Ryzen 7 3###", 6 }, "Ryzen 7 (Matisse)" },
{ 15, -1, -1, 23, 113, -1, -1, -1, { "Ryzen 5 3###", 6 }, "Ryzen 5 (Matisse)" },
{ 15, -1, -1, 23, 113, -1, -1, -1, { "Ryzen 3 3###", 6 }, "Ryzen 3 (Matisse)" },
{ 15, -1, -1, 23, 96, -1, -1, -1, { "Ryzen 9 4###", 6 }, "Ryzen 9 (Renoir)" },
{ 15, -1, -1, 23, 96, -1, -1, -1, { "Ryzen 7 4###", 6 }, "Ryzen 7 (Renoir)" },
{ 15, -1, -1, 23, 96, -1, -1, -1, { "Ryzen 5 4###", 6 }, "Ryzen 5 (Renoir)" },
{ 15, -1, -1, 23, 96, -1, -1, -1, { "Ryzen 3 4###", 6 }, "Ryzen 3 (Renoir)" },
{ 15, -1, -1, 23, 104, -1, -1, -1, { "Ryzen 7 5###", 6 }, "Ryzen 7 (Lucienne)" },
{ 15, -1, -1, 23, 104, -1, -1, -1, { "Ryzen 5 5###", 6 }, "Ryzen 5 (Lucienne)" },
{ 15, -1, -1, 23, 104, -1, -1, -1, { "Ryzen 3 5###", 6 }, "Ryzen 3 (Lucienne)" },
{ 15, -1, -1, 23, 71, -1, -1, -1, { "Desktop Kit", 4 }, "Desktop Kit (Zen 2)" }, /* 4700S Desktop Kit */
{ 15, -1, -1, 23, 132, -1, -1, -1, { "Desktop Kit", 4 }, "Desktop Kit (Zen 2)" }, /* 4800S Desktop Kit */
{ 15, -1, 2, 23, 144, -1, -1, -1, { "Custom APU", 4 }, "Van Gogh" }, /* Custom APU 0405 */
{ 15, -1, 0, 23, 145, -1, -1, -1, { "Custom APU", 4 }, "Van Gogh" }, /* Custom APU 0932 */
{ 15, -1, -1, 23, 160, -1, -1, -1, { "Ryzen 5 7###", 6 }, "Ryzen 5 (Mendocino)" },
{ 15, -1, -1, 23, 160, -1, -1, -1, { "Ryzen 3 7###", 6 }, "Ryzen 3 (Mendocino)" },
{ 15, -1, -1, 23, 160, -1, -1, -1, { "Athlon", 2 }, "Athlon (Mendocino)" },
{ 15, -1, -1, 23, 49, -1, -1, -1, { "EPYC 7##2", 4 }, "EPYC (Rome)", "TSMC N7FF" },
{ 15, -1, -1, 23, 49, -1, -1, -1, { "Threadripper 3###", 4 }, "Threadripper (Castle Peak)", "TSMC N7FF" },
{ 15, -1, -1, 23, 113, -1, -1, -1, { "Ryzen 9 3###", 6 }, "Ryzen 9 (Matisse)", "TSMC N7FF" },
{ 15, -1, -1, 23, 113, -1, -1, -1, { "Ryzen 7 3###", 6 }, "Ryzen 7 (Matisse)", "TSMC N7FF" },
{ 15, -1, -1, 23, 113, -1, -1, -1, { "Ryzen 5 3###", 6 }, "Ryzen 5 (Matisse)", "TSMC N7FF" },
{ 15, -1, -1, 23, 113, -1, -1, -1, { "Ryzen 3 3###", 6 }, "Ryzen 3 (Matisse)", "TSMC N7FF" },
{ 15, -1, -1, 23, 96, -1, -1, -1, { "Ryzen 9 4###", 6 }, "Ryzen 9 (Renoir)", "TSMC N7FF" },
{ 15, -1, -1, 23, 96, -1, -1, -1, { "Ryzen 7 4###", 6 }, "Ryzen 7 (Renoir)", "TSMC N7FF" },
{ 15, -1, -1, 23, 96, -1, -1, -1, { "Ryzen 5 4###", 6 }, "Ryzen 5 (Renoir)", "TSMC N7FF" },
{ 15, -1, -1, 23, 96, -1, -1, -1, { "Ryzen 3 4###", 6 }, "Ryzen 3 (Renoir)", "TSMC N7FF" },
{ 15, -1, -1, 23, 104, -1, -1, -1, { "Ryzen 7 5###", 6 }, "Ryzen 7 (Lucienne)", "TSMC N7FF" },
{ 15, -1, -1, 23, 104, -1, -1, -1, { "Ryzen 5 5###", 6 }, "Ryzen 5 (Lucienne)", "TSMC N7FF" },
{ 15, -1, -1, 23, 104, -1, -1, -1, { "Ryzen 3 5###", 6 }, "Ryzen 3 (Lucienne)", "TSMC N7FF" },
{ 15, -1, -1, 23, 71, -1, -1, -1, { "Desktop Kit", 4 }, "Desktop Kit (Zen 2)", "TSMC N7FF" }, /* 4700S Desktop Kit */
{ 15, -1, -1, 23, 132, -1, -1, -1, { "Desktop Kit", 4 }, "Desktop Kit (Zen 2)", "TSMC N7FF" }, /* 4800S Desktop Kit */
{ 15, -1, 2, 23, 144, -1, -1, -1, { "Custom APU", 4 }, "Van Gogh", "TSMC N7FF" }, /* Custom APU 0405 */
{ 15, -1, 0, 23, 145, -1, -1, -1, { "Custom APU", 4 }, "Van Gogh", "TSMC N7FF" }, /* Custom APU 0932 */
{ 15, -1, -1, 23, 160, -1, -1, -1, { "Ryzen 5 7###", 6 }, "Ryzen 5 (Mendocino)", "TSMC N6" },
{ 15, -1, -1, 23, 160, -1, -1, -1, { "Ryzen 3 7###", 6 }, "Ryzen 3 (Mendocino)", "TSMC N6" },
{ 15, -1, -1, 23, 160, -1, -1, -1, { "Athlon", 2 }, "Athlon (Mendocino)", "TSMC N6" },
/* Family 18h */
/* Zen Architecture for Hygon (2018) => https://en.wikichip.org/wiki/hygon/microarchitectures/dhyana */
{ 15, -1, -1, 24, 0, -1, -1, -1, { "C86", 2 }, "C86 (Dhyana)" },
{ 15, -1, -1, 24, 0, -1, -1, -1, { "C86", 2 }, "C86 (Dhyana)", UNKN_STR },
/* Family 19h */
/* Zen 3 (2020) => https://en.wikichip.org/wiki/amd/microarchitectures/zen_3 */
{ 15, -1, -1, 25, 1, -1, -1, -1, { "EPYC 7##3", 4 }, "EPYC (Milan)" },
{ 15, -1, -1, 25, 8, -1, -1, -1, { "Threadripper 5###", 4 }, "Threadripper (Chagall)" },
{ 15, -1, -1, 25, 33, -1, -1, -1, { "Ryzen 9 5###", 6 }, "Ryzen 9 (Vermeer)" },
{ 15, -1, -1, 25, 33, -1, -1, -1, { "Ryzen 7 5###", 6 }, "Ryzen 7 (Vermeer)" },
{ 15, -1, -1, 25, 33, -1, -1, -1, { "Ryzen 5 5###", 6 }, "Ryzen 5 (Vermeer)" },
{ 15, -1, -1, 25, 33, -1, -1, -1, { "Ryzen 3 5###", 6 }, "Ryzen 3 (Vermeer)" },
{ 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 9 5###", 6 }, "Ryzen 9 (Cezanne)" },
{ 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 7 5###", 6 }, "Ryzen 7 (Cezanne)" },
{ 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 5 5###", 6 }, "Ryzen 5 (Cezanne)" },
{ 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 3 5###", 6 }, "Ryzen 3 (Cezanne)" },
{ 15, -1, -1, 25, 1, -1, -1, -1, { "EPYC 7##3", 4 }, "EPYC (Milan)", "TSMC N7FF" },
{ 15, -1, -1, 25, 8, -1, -1, -1, { "Threadripper 5###", 4 }, "Threadripper (Chagall)", "TSMC N7FF" },
{ 15, -1, -1, 25, 33, -1, -1, -1, { "Ryzen 9 5###", 6 }, "Ryzen 9 (Vermeer)", "TSMC N7FF" },
{ 15, -1, -1, 25, 33, -1, -1, -1, { "Ryzen 7 5###", 6 }, "Ryzen 7 (Vermeer)", "TSMC N7FF" },
{ 15, -1, -1, 25, 33, -1, -1, -1, { "Ryzen 5 5###", 6 }, "Ryzen 5 (Vermeer)", "TSMC N7FF" },
{ 15, -1, -1, 25, 33, -1, -1, -1, { "Ryzen 3 5###", 6 }, "Ryzen 3 (Vermeer)", "TSMC N7FF" },
{ 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 9 5###", 6 }, "Ryzen 9 (Cezanne)", "TSMC N7FF" },
{ 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 7 5###", 6 }, "Ryzen 7 (Cezanne)", "TSMC N7FF" },
{ 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 5 5###", 6 }, "Ryzen 5 (Cezanne)", "TSMC N7FF" },
{ 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 3 5###", 6 }, "Ryzen 3 (Cezanne)", "TSMC N7FF" },
/* Zen 3+ (2022) */
{ 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 9 6###", 6 }, "Ryzen 9 (Rembrandt)" },
{ 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 7 6###", 6 }, "Ryzen 7 (Rembrandt)" },
{ 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 5 6###", 6 }, "Ryzen 5 (Rembrandt)" },
{ 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 3 6###", 6 }, "Ryzen 3 (Rembrandt)" },
{ 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 7 7###", 6 }, "Ryzen 7 (Rembrandt-R)" },
{ 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 5 7###", 6 }, "Ryzen 5 (Rembrandt-R)" },
{ 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 3 7###", 6 }, "Ryzen 3 (Rembrandt-R)" },
{ 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 9 6###", 6 }, "Ryzen 9 (Rembrandt)", "TSMC N6" },
{ 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 7 6###", 6 }, "Ryzen 7 (Rembrandt)", "TSMC N6" },
{ 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 5 6###", 6 }, "Ryzen 5 (Rembrandt)", "TSMC N6" },
{ 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 3 6###", 6 }, "Ryzen 3 (Rembrandt)", "TSMC N6" },
{ 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 7 7###", 6 }, "Ryzen 7 (Rembrandt-R)", "TSMC N6" },
{ 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 5 7###", 6 }, "Ryzen 5 (Rembrandt-R)", "TSMC N6" },
{ 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 3 7###", 6 }, "Ryzen 3 (Rembrandt-R)", "TSMC N6" },
/* Zen 4 (2022) => https://en.wikichip.org/wiki/amd/microarchitectures/zen_4 */
{ 15, -1, -1, 25, 17, -1, -1, -1, { "EPYC 9##4", 4 }, "EPYC (Genoa)" },
{ 15, -1, -1, 25, 24, -1, -1, -1, { "Threadripper 7###", 4 }, "Threadripper (Storm Peak)" },
{ 15, -1, -1, 25, 17, -1, -1, -1, { "EPYC 9##4", 4 }, "EPYC (Genoa)", "TSMC N5" },
{ 15, -1, -1, 25, 24, -1, -1, -1, { "Threadripper 7###", 4 }, "Threadripper (Storm Peak)", "TSMC N5" },
/* => Raphael (7000 series, Zen 4/RDNA2 based) */
{ 15, -1, 2, 25, 97, -1, -1, -1, { "Ryzen 9 7###", 6 }, "Ryzen 9 (Raphael)" },
{ 15, -1, 2, 25, 97, -1, -1, -1, { "Ryzen 7 7###", 6 }, "Ryzen 7 (Raphael)" },
{ 15, -1, 2, 25, 97, -1, -1, -1, { "Ryzen 5 7###", 6 }, "Ryzen 5 (Raphael)" },
{ 15, -1, 2, 25, 97, -1, -1, -1, { "Ryzen 3 7###", 6 }, "Ryzen 3 (Raphael)" },
{ 15, -1, 2, 25, 97, -1, -1, -1, { "Ryzen 9 7###", 6 }, "Ryzen 9 (Raphael)", "TSMC N5" },
{ 15, -1, 2, 25, 97, -1, -1, -1, { "Ryzen 7 7###", 6 }, "Ryzen 7 (Raphael)", "TSMC N5" },
{ 15, -1, 2, 25, 97, -1, -1, -1, { "Ryzen 5 7###", 6 }, "Ryzen 5 (Raphael)", "TSMC N5" },
{ 15, -1, 2, 25, 97, -1, -1, -1, { "Ryzen 3 7###", 6 }, "Ryzen 3 (Raphael)", "TSMC N5" },
/* => Dragon Range (7045 series, Zen 4/RDNA2 based) */
{ 15, -1, -1, 25, 97, -1, -1, -1, { "Ryzen 9 7###H", 8 }, "Ryzen 9 (Dragon Range)" },
{ 15, -1, -1, 25, 97, -1, -1, -1, { "Ryzen 7 7###H", 8 }, "Ryzen 7 (Dragon Range)" },
{ 15, -1, -1, 25, 97, -1, -1, -1, { "Ryzen 5 7###H", 8 }, "Ryzen 5 (Dragon Range)" },
{ 15, -1, -1, 25, 97, -1, -1, -1, { "Ryzen 9 7###H", 8 }, "Ryzen 9 (Dragon Range)", "TSMC N5" },
{ 15, -1, -1, 25, 97, -1, -1, -1, { "Ryzen 7 7###H", 8 }, "Ryzen 7 (Dragon Range)", "TSMC N5" },
{ 15, -1, -1, 25, 97, -1, -1, -1, { "Ryzen 5 7###H", 8 }, "Ryzen 5 (Dragon Range)", "TSMC N5" },
/* => Phoenix (7040 series, Zen 4/RDNA3/XDNA based) */
{ 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 9 7###H", 8 }, "Ryzen 9 (Phoenix)" },
{ 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 7 7###H", 8 }, "Ryzen 7 (Phoenix)" },
{ 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 7 7###U", 8 }, "Ryzen 7 (Phoenix)" },
{ 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 5 7###H", 8 }, "Ryzen 5 (Phoenix)" },
{ 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 5 7###U", 8 }, "Ryzen 5 (Phoenix)" },
{ 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 3 7###U", 8 }, "Ryzen 3 (Phoenix)" },
{ 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen Z1", 4 }, "Ryzen Z1 (Phoenix)" },
{ 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 9 7###H", 8 }, "Ryzen 9 (Phoenix)", "TSMC N4" },
{ 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 7 7###H", 8 }, "Ryzen 7 (Phoenix)", "TSMC N4" },
{ 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 7 7###U", 8 }, "Ryzen 7 (Phoenix)", "TSMC N4" },
{ 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 5 7###H", 8 }, "Ryzen 5 (Phoenix)", "TSMC N4" },
{ 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 5 7###U", 8 }, "Ryzen 5 (Phoenix)", "TSMC N4" },
{ 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 3 7###U", 8 }, "Ryzen 3 (Phoenix)", "TSMC N4" },
{ 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen Z1", 4 }, "Ryzen Z1 (Phoenix)", "TSMC N4" },
/* => Phoenix (8000 series, Zen 4 based) */
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 7 8###F", 8 }, "Ryzen 7 (Phoenix)" },
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 5 8###F", 8 }, "Ryzen 5 (Phoenix)" },
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 7 8###F", 8 }, "Ryzen 7 (Phoenix)", "TSMC N4" },
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 5 8###F", 8 }, "Ryzen 5 (Phoenix)", "TSMC N4" },
/* => Phoenix (8000 series with Radeon Graphics, Zen 4/RDNA3/XDNA based) */
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 9 8###G", 8 }, "Ryzen 9 (Phoenix)" },
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 7 8###G", 8 }, "Ryzen 7 (Phoenix)" },
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 5 8###G", 8 }, "Ryzen 5 (Phoenix)" },
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 3 8###G", 8 }, "Ryzen 3 (Phoenix)" },
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 9 8###G", 8 }, "Ryzen 9 (Phoenix)", "TSMC N4" },
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 7 8###G", 8 }, "Ryzen 7 (Phoenix)", "TSMC N4" },
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 5 8###G", 8 }, "Ryzen 5 (Phoenix)", "TSMC N4" },
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 3 8###G", 8 }, "Ryzen 3 (Phoenix)", "TSMC N4" },
/* => Hawk Point (8040 series, Zen 4/RDNA3/XDNA based) */
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 9 8###H", 8 }, "Ryzen 9 (Hawk Point)" },
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 7 8###H", 8 }, "Ryzen 7 (Hawk Point)" },
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 7 8###U", 8 }, "Ryzen 7 (Hawk Point)" },
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 5 8###H", 8 }, "Ryzen 5 (Hawk Point)" },
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 5 8###U", 8 }, "Ryzen 5 (Hawk Point)" },
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 3 8###U", 8 }, "Ryzen 3 (Hawk Point)" },
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 9 8###H", 8 }, "Ryzen 9 (Hawk Point)", "TSMC N4" },
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 7 8###H", 8 }, "Ryzen 7 (Hawk Point)", "TSMC N4" },
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 7 8###U", 8 }, "Ryzen 7 (Hawk Point)", "TSMC N4" },
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 5 8###H", 8 }, "Ryzen 5 (Hawk Point)", "TSMC N4" },
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 5 8###U", 8 }, "Ryzen 5 (Hawk Point)", "TSMC N4" },
{ 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 3 8###U", 8 }, "Ryzen 3 (Hawk Point)", "TSMC N4" },
/* Zen 5 (2024) => https://en.wikichip.org/wiki/amd/microarchitectures/zen_5 */
{ 15, -1, -1, 26, 2, -1, -1, -1, { "EPYC 9##5", 4 }, "EPYC (Turin)" },
{ 15, -1, -1, 26, 17, -1, -1, -1, { "EPYC 9##5", 4 }, "EPYC (Turin Dense)" },
{ 15, -1, -1, 26, 2, -1, -1, -1, { "EPYC 9##5", 4 }, "EPYC (Turin)", "TSMC N4X" },
{ 15, -1, -1, 26, 17, -1, -1, -1, { "EPYC 9##5", 4 }, "EPYC (Turin Dense)", "TSMC N3E" },
/* => Granite Ridge (9000 series, Zen 5 based) */
{ 15, -1, -1, 26, 68, -1, -1, -1, { "Ryzen 9 9###", 6 }, "Ryzen 9 (Granite Ridge)" },
{ 15, -1, -1, 26, 68, -1, -1, -1, { "Ryzen 7 9###", 6 }, "Ryzen 7 (Granite Ridge)" },
{ 15, -1, -1, 26, 68, -1, -1, -1, { "Ryzen 5 9###", 6 }, "Ryzen 5 (Granite Ridge)" },
{ 15, -1, -1, 26, 68, -1, -1, -1, { "Ryzen 3 9###", 6 }, "Ryzen 3 (Granite Ridge)" },
{ 15, -1, -1, 26, 68, -1, -1, -1, { "Ryzen 9 9###", 6 }, "Ryzen 9 (Granite Ridge)", "TSMC N4" },
{ 15, -1, -1, 26, 68, -1, -1, -1, { "Ryzen 7 9###", 6 }, "Ryzen 7 (Granite Ridge)", "TSMC N4" },
{ 15, -1, -1, 26, 68, -1, -1, -1, { "Ryzen 5 9###", 6 }, "Ryzen 5 (Granite Ridge)", "TSMC N4" },
{ 15, -1, -1, 26, 68, -1, -1, -1, { "Ryzen 3 9###", 6 }, "Ryzen 3 (Granite Ridge)", "TSMC N4" },
/* => Strix Point (Zen 5/RDNA3.5/XDNA2 based) */
{ 15, -1, -1, 26, 36, -1, -1, -1, { "Ryzen AI 9", 6 }, "Ryzen AI 9 (Strix Point)" },
{ 15, -1, -1, 26, 36, -1, -1, -1, { "Ryzen AI 7", 6 }, "Ryzen AI 7 (Strix Point)" },
// F M S EF EM #cores L2$ L3$ Pattern Name
{ 15, -1, -1, 26, 36, -1, -1, -1, { "Ryzen AI 9", 6 }, "Ryzen AI 9 (Strix Point)", "TSMC N4P" },
{ 15, -1, -1, 26, 36, -1, -1, -1, { "Ryzen AI 7", 6 }, "Ryzen AI 7 (Strix Point)", "TSMC N4P" },
// F M S EF EM #cores L2$ L3$ Pattern Codename Technology
};

431
libcpuid/recog_arm.c
View file

@ -60,6 +60,7 @@ struct arm_id_part {
const int id;
const char* name;
const char* codename;
const char* technology;
};
struct arm_hw_impl {
@ -72,268 +73,269 @@ struct arm_hw_impl {
/* Decoded PartNum for all implementers
ID taken from lscpu-arm: https://github.com/util-linux/util-linux/blob/master/sys-utils/lscpu-arm.c
*/
/* Codenames: https://en.wikichip.org/wiki/arm_holdings */
static const struct arm_id_part arm_part[] = {
{ 0x810, "ARM810", "" },
{ 0x920, "ARM920", "" },
{ 0x922, "ARM922", "" },
{ 0x926, "ARM926", "" },
{ 0x940, "ARM940", "" },
{ 0x946, "ARM946", "" },
{ 0x966, "ARM966", "" },
{ 0xa20, "ARM1020", "" },
{ 0xa22, "ARM1022", "" },
{ 0xa26, "ARM1026", "" },
{ 0xb02, "ARM11 MPCore", "" },
{ 0xb36, "ARM1136", "" },
{ 0xb56, "ARM1156", "" },
{ 0xb76, "ARM1176", "" },
{ 0xc05, "Cortex-A5", "Sparrow" },
{ 0xc07, "Cortex-A7", "Kingfisher" },
{ 0xc08, "Cortex-A8", "Tiger" },
{ 0xc09, "Cortex-A9", "Falcon" },
{ 0xc0d, "Cortex-A17", "Owl" }, /* Originally A12 */
{ 0xc0f, "Cortex-A15", "Eagle" },
{ 0xc0e, "Cortex-A17", "Owl" },
{ 0xc14, "Cortex-R4", "" },
{ 0xc15, "Cortex-R5", "" },
{ 0xc17, "Cortex-R7", "" },
{ 0xc18, "Cortex-R8", "" },
{ 0xc20, "Cortex-M0", "Swift" },
{ 0xc21, "Cortex-M1", "Proteus" },
{ 0xc23, "Cortex-M3", "Sandcat" },
{ 0xc24, "Cortex-M4", "Merlin" },
{ 0xc27, "Cortex-M7", "Pelican" },
{ 0xc60, "Cortex-M0+", "Flycatcher" },
{ 0xd01, "Cortex-A32", "Minerva" },
{ 0xd02, "Cortex-A34", "Metis" },
{ 0xd03, "Cortex-A53", "Apollo" },
{ 0xd04, "Cortex-A35", "Mercury" },
{ 0xd05, "Cortex-A55", "Ananke" },
{ 0xd06, "Cortex-A65", "Helios" },
{ 0xd07, "Cortex-A57", "Atlas" },
{ 0xd08, "Cortex-A72", "Maia" },
{ 0xd09, "Cortex-A73", "Artemis" },
{ 0xd0a, "Cortex-A75", "Prometheus" },
{ 0xd0b, "Cortex-A76", "Enyo" },
{ 0xd0c, "Neoverse-N1", "Ares" },
{ 0xd0d, "Cortex-A77", "Deimos" },
{ 0xd0e, "Cortex-A76AE", "Enyo-AE" },
{ 0xd13, "Cortex-R52", "" },
{ 0xd15, "Cortex-R82", "" },
{ 0xd16, "Cortex-R52+", "" },
{ 0xd20, "Cortex-M23", "Grebe" },
{ 0xd21, "Cortex-M33", "Teal" },
{ 0xd22, "Cortex-M55", "Yamin" },
{ 0xd23, "Cortex-M85", "" },
{ 0xd40, "Neoverse-V1", "Zeus" },
{ 0xd41, "Cortex-A78", "Hercules" },
{ 0xd42, "Cortex-A78AE", "Hercules-AE" },
{ 0xd43, "Cortex-A65AE", "Helios-AE" },
{ 0xd44, "Cortex-X1", "Hera" },
{ 0xd46, "Cortex-A510", "Klein" },
{ 0xd47, "Cortex-A710", "Matterhorn" },
{ 0xd48, "Cortex-X2", "Matterhorn ELP" },
{ 0xd49, "Neoverse-N2", "Perseus" },
{ 0xd4a, "Neoverse-E1", "Helios" },
{ 0xd4b, "Cortex-A78C", "Hercules-C" },
{ 0xd4c, "Cortex-X1C", "Hera-C" },
{ 0xd4d, "Cortex-A715", "Makalu" },
{ 0xd4e, "Cortex-X3", "Makalu ELP" },
{ 0xd4f, "Neoverse-V2", "Demeter" },
{ 0xd80, "Cortex-A520", "Hayes" },
{ 0xd81, "Cortex-A720", "Hunter" },
{ 0xd82, "Cortex-X4", "Hunter ELP" },
{ 0xd84, "Neoverse-V3", "Poseidon" },
{ 0xd8e, "Neoverse-N3", "Hermes" },
{ -1, "unknown", "" },
/* Part numbers: https://en.wikichip.org/wiki/arm_holdings/cortex#Part_numbers
Codenames: https://en.wikichip.org/wiki/arm_holdings */
static const struct arm_id_part arm_part[] = {
{ 0x810, "ARM810", "", UNKN_STR },
{ 0x920, "ARM920", "", UNKN_STR },
{ 0x922, "ARM922", "", UNKN_STR },
{ 0x926, "ARM926", "", UNKN_STR },
{ 0x940, "ARM940", "", UNKN_STR },
{ 0x946, "ARM946", "", UNKN_STR },
{ 0x966, "ARM966", "", UNKN_STR },
{ 0xa20, "ARM1020", "", UNKN_STR },
{ 0xa22, "ARM1022", "", UNKN_STR },
{ 0xa26, "ARM1026", "", UNKN_STR },
{ 0xb02, "ARM11 MPCore", "", UNKN_STR },
{ 0xb36, "ARM1136", "", UNKN_STR },
{ 0xb56, "ARM1156", "", UNKN_STR },
{ 0xb76, "ARM1176", "", UNKN_STR },
{ 0xc05, "Cortex-A5", "Sparrow", "40-28 nm" },
{ 0xc07, "Cortex-A7", "Kingfisher", "40-28 nm" },
{ 0xc08, "Cortex-A8", "Tiger", "65-45 nm" },
{ 0xc09, "Cortex-A9", "Falcon", "65-28 nm" },
{ 0xc0d, "Cortex-A17", "Owl", "28 nm" }, /* Originally A12 */
{ 0xc0f, "Cortex-A15", "Eagle", "32-20 nm" },
{ 0xc0e, "Cortex-A17", "Owl", "28 nm" },
{ 0xc14, "Cortex-R4", "", UNKN_STR },
{ 0xc15, "Cortex-R5", "", UNKN_STR },
{ 0xc17, "Cortex-R7", "", UNKN_STR },
{ 0xc18, "Cortex-R8", "", UNKN_STR },
{ 0xc20, "Cortex-M0", "Swift", UNKN_STR },
{ 0xc21, "Cortex-M1", "Proteus", UNKN_STR },
{ 0xc23, "Cortex-M3", "Sandcat", UNKN_STR },
{ 0xc24, "Cortex-M4", "Merlin", UNKN_STR },
{ 0xc27, "Cortex-M7", "Pelican", UNKN_STR },
{ 0xc60, "Cortex-M0+", "Flycatcher", UNKN_STR },
{ 0xd01, "Cortex-A32", "Minerva", "28 nm" },
{ 0xd02, "Cortex-A34", "Metis", UNKN_STR },
{ 0xd03, "Cortex-A53", "Apollo", "28-10 nm" },
{ 0xd04, "Cortex-A35", "Mercury", "28-10 nm" },
{ 0xd05, "Cortex-A55", "Ananke", "28-5 nm" },
{ 0xd06, "Cortex-A65", "Helios", UNKN_STR },
{ 0xd07, "Cortex-A57", "Atlas", "28-14 nm" },
{ 0xd08, "Cortex-A72", "Maia", "28-16 nm" },
{ 0xd09, "Cortex-A73", "Artemis", "28-10 nm" },
{ 0xd0a, "Cortex-A75", "Prometheus", "28-10 nm" },
{ 0xd0b, "Cortex-A76", "Enyo", "10-7 nm" },
{ 0xd0c, "Neoverse-N1", "Ares", "7 nm" },
{ 0xd0d, "Cortex-A77", "Deimos", "7 nm" },
{ 0xd0e, "Cortex-A76AE", "Enyo-AE", UNKN_STR },
{ 0xd13, "Cortex-R52", "", UNKN_STR },
{ 0xd15, "Cortex-R82", "", UNKN_STR },
{ 0xd16, "Cortex-R52+", "", UNKN_STR },
{ 0xd20, "Cortex-M23", "Grebe", UNKN_STR },
{ 0xd21, "Cortex-M33", "Teal", UNKN_STR },
{ 0xd22, "Cortex-M55", "Yamin", UNKN_STR },
{ 0xd23, "Cortex-M85", "", UNKN_STR },
{ 0xd40, "Neoverse-V1", "Zeus", "7 nm" },
{ 0xd41, "Cortex-A78", "Hercules", "5 nm" },
{ 0xd42, "Cortex-A78AE", "Hercules-AE", UNKN_STR },
{ 0xd43, "Cortex-A65AE", "Helios-AE", UNKN_STR },
{ 0xd44, "Cortex-X1", "Hera", "10-5 nm" },
{ 0xd46, "Cortex-A510", "Klein", "7-5 nm" },
{ 0xd47, "Cortex-A710", "Matterhorn", "7-5 nm" },
{ 0xd48, "Cortex-X2", "Matterhorn ELP", UNKN_STR },
{ 0xd49, "Neoverse-N2", "Perseus", "5 nm" },
{ 0xd4a, "Neoverse-E1", "Helios", UNKN_STR },
{ 0xd4b, "Cortex-A78C", "Hercules-C", "5 nm" },
{ 0xd4c, "Cortex-X1C", "Hera-C", UNKN_STR },
{ 0xd4d, "Cortex-A715", "Makalu", "7-5 nm" },
{ 0xd4e, "Cortex-X3", "Makalu ELP", UNKN_STR },
{ 0xd4f, "Neoverse-V2", "Demeter", UNKN_STR },
{ 0xd80, "Cortex-A520", "Hayes", "3 nm" },
{ 0xd81, "Cortex-A720", "Hunter", "3 nm" },
{ 0xd82, "Cortex-X4", "Hunter ELP", UNKN_STR },
{ 0xd84, "Neoverse-V3", "Poseidon", UNKN_STR },
{ 0xd8e, "Neoverse-N3", "Hermes", UNKN_STR },
{ -1, "unknown", "", UNKN_STR },
};
static const struct arm_id_part brcm_part[] = {
{ 0x0f, "Brahma-B15", "" },
{ 0x100, "Brahma-B53", "" },
{ 0x516, "ThunderX2", "" },
{ -1, "unknown", "" },
{ 0x0f, "Brahma-B15", "", UNKN_STR },
{ 0x100, "Brahma-B53", "", UNKN_STR },
{ 0x516, "ThunderX2", "", UNKN_STR },
{ -1, "unknown", "", UNKN_STR },
};
static const struct arm_id_part dec_part[] = {
{ 0xa10, "SA110", "" },
{ 0xa11, "SA1100", "" },
{ -1, "unknown", "" },
{ 0xa10, "SA110", "", UNKN_STR },
{ 0xa11, "SA1100", "", UNKN_STR },
{ -1, "unknown", "", UNKN_STR },
};
static const struct arm_id_part cavium_part[] = {
{ 0x0a0, "ThunderX", "" },
{ 0x0a1, "ThunderX-88XX", "" },
{ 0x0a2, "ThunderX-81XX", "" },
{ 0x0a3, "ThunderX-83XX", "" },
{ 0x0af, "ThunderX2-99xx", "" },
{ 0x0b0, "OcteonTX2", "" },
{ 0x0b1, "OcteonTX2-98XX", "" },
{ 0x0b2, "OcteonTX2-96XX", "" },
{ 0x0b3, "OcteonTX2-95XX", "" },
{ 0x0b4, "OcteonTX2-95XXN", "" },
{ 0x0b5, "OcteonTX2-95XXMM", "" },
{ 0x0b6, "OcteonTX2-95XXO", "" },
{ 0x0b8, "ThunderX3-T110", "" },
{ -1, "unknown", "" },
{ 0x0a0, "ThunderX", "", UNKN_STR },
{ 0x0a1, "ThunderX-88XX", "", UNKN_STR },
{ 0x0a2, "ThunderX-81XX", "", UNKN_STR },
{ 0x0a3, "ThunderX-83XX", "", UNKN_STR },
{ 0x0af, "ThunderX2-99xx", "", UNKN_STR },
{ 0x0b0, "OcteonTX2", "", UNKN_STR },
{ 0x0b1, "OcteonTX2-98XX", "", UNKN_STR },
{ 0x0b2, "OcteonTX2-96XX", "", UNKN_STR },
{ 0x0b3, "OcteonTX2-95XX", "", UNKN_STR },
{ 0x0b4, "OcteonTX2-95XXN", "", UNKN_STR },
{ 0x0b5, "OcteonTX2-95XXMM", "", UNKN_STR },
{ 0x0b6, "OcteonTX2-95XXO", "", UNKN_STR },
{ 0x0b8, "ThunderX3-T110", "", UNKN_STR },
{ -1, "unknown", "", UNKN_STR },
};
static const struct arm_id_part apm_part[] = {
{ 0x000, "X-Gene", "" },
{ -1, "unknown", "" },
{ 0x000, "X-Gene", "", UNKN_STR },
{ -1, "unknown", "", UNKN_STR },
};
static const struct arm_id_part qcom_part[] = {
{ 0x001, "Oryon", "" },
{ 0x00f, "Scorpion", "" },
{ 0x02d, "Scorpion", "" },
{ 0x04d, "Krait", "" },
{ 0x06f, "Krait", "" },
{ 0x201, "Kryo", "" },
{ 0x205, "Kryo", "" },
{ 0x211, "Kryo", "" },
{ 0x800, "Falkor-V1/Kryo", "" },
{ 0x801, "Kryo-V2", "" },
{ 0x802, "Kryo-3XX-Gold", "" },
{ 0x803, "Kryo-3XX-Silver", "" },
{ 0x804, "Kryo-4XX-Gold", "" },
{ 0x805, "Kryo-4XX-Silver", "" },
{ 0xc00, "Falkor", "" },
{ 0xc01, "Saphira", "" },
{ -1, "unknown", "" },
{ 0x001, "Oryon", "", UNKN_STR },
{ 0x00f, "Scorpion", "", "65-45 nm" },
{ 0x02d, "Scorpion", "", "65-45 nm" },
{ 0x04d, "Krait", "", "28 nm" },
{ 0x06f, "Krait", "", "28 nm" },
{ 0x201, "Kryo", "", "14 nm" },
{ 0x205, "Kryo", "", "14 nm" },
{ 0x211, "Kryo", "", "14 nm" },
{ 0x800, "Falkor-V1/Kryo", "", UNKN_STR },
{ 0x801, "Kryo-V2", "", "14-6 nm" },
{ 0x802, "Kryo-3XX-Gold", "", "10 nm" },
{ 0x803, "Kryo-3XX-Silver", "", "10 nm" },
{ 0x804, "Kryo-4XX-Gold", "", "11-7 nm" },
{ 0x805, "Kryo-4XX-Silver", "", "8-7 nm" },
{ 0xc00, "Falkor", "", "10 nm" },
{ 0xc01, "Saphira", "", "8-7 nm" },
{ -1, "unknown", "", UNKN_STR },
};
static const struct arm_id_part samsung_part[] = {
{ 0x001, "Exynos M1", "" },
{ 0x002, "Exynos M3", "" },
{ 0x003, "Exynos M4", "" },
{ 0x004, "Exynos M5", "" },
{ -1, "unknown", "" },
{ 0x001, "Exynos M1", "", "14 nm" },
{ 0x002, "Exynos M3", "", "10 nm" },
{ 0x003, "Exynos M4", "", "8 nm" },
{ 0x004, "Exynos M5", "", "7 nm" },
{ -1, "unknown", "", UNKN_STR },
};
static const struct arm_id_part nvidia_part[] = {
{ 0x000, "Denver", "" },
{ 0x003, "Denver 2", "" },
{ 0x004, "Carmel", "" },
{ -1, "unknown", "" },
{ 0x000, "Denver", "", "28 nm" },
{ 0x003, "Denver 2", "", "16 nm" },
{ 0x004, "Carmel", "", "12 nm" },
{ -1, "unknown", "", UNKN_STR },
};
static const struct arm_id_part marvell_part[] = {
{ 0x131, "Feroceon-88FR131", "" },
{ 0x581, "PJ4/PJ4b", "" },
{ 0x584, "PJ4B-MP", "" },
{ -1, "unknown", "" },
{ 0x131, "Feroceon-88FR131", "", UNKN_STR },
{ 0x581, "PJ4/PJ4b", "", UNKN_STR },
{ 0x584, "PJ4B-MP", "", UNKN_STR },
{ -1, "unknown", "", UNKN_STR },
};
static const struct arm_id_part apple_part[] = {
{ 0x000, "A6", "Swift" },
{ 0x001, "A7", "Cyclone" },
{ 0x002, "A8", "Typhoon" },
{ 0x003, "A8X", "Typhoon" },
{ 0x004, "A9", "Twister" },
{ 0x005, "A9X", "Twister" },
{ 0x006, "A10 Fusion", "Zephyr" },
{ 0x007, "A10 Fusion", "Hurricane" },
{ 0x008, "A11 Bionic", "Monsoon" },
{ 0x009, "A11 Bionic", "Mistral" },
{ 0x00b, "A12", "Vortex" },
{ 0x00c, "A12", "Tempest" },
{ 0x00f, "M9", "Tempest" },
{ 0x010, "A12X Bionic", "Vortex" },
{ 0x011, "A12X Bionic", "Tempest" },
{ 0x012, "A13 Bionic", "Lightning" },
{ 0x013, "A13 Bionic", "Thunder" },
{ 0x020, "A14", "Icestorm" },
{ 0x021, "A14", "Firestorm" },
{ 0x022, "M1", "Icestorm" },
{ 0x023, "M1", "Firestorm" },
{ 0x024, "M1 Pro", "Icestorm" },
{ 0x025, "M1 Pro", "Firestorm" },
{ 0x026, "M10", "Thunder" },
{ 0x028, "M1 Max", "Icestorm" },
{ 0x029, "M1 Max", "Firestorm" },
{ 0x030, "A15", "Blizzard" },
{ 0x031, "A15", "Avalanche" },
{ 0x032, "M2", "Blizzard" },
{ 0x033, "M2", "Avalanche" },
{ 0x034, "M2 Pro", "Blizzard" },
{ 0x035, "M2 Pro", "Avalanche" },
{ 0x036, "A16", "Sawtooth" },
{ 0x037, "A16", "Everest" },
{ 0x038, "M2 Max", "Blizzard" },
{ 0x039, "M2 Max", "Avalanche" },
{ -1, "unknown", "" },
{ 0x000, "A6", "Swift", "32 nm" },
{ 0x001, "A7", "Cyclone", "28 nm" },
{ 0x002, "A8", "Typhoon", "20 nm" },
{ 0x003, "A8X", "Typhoon", "20 nm" },
{ 0x004, "A9", "Twister", "16 nm" },
{ 0x005, "A9X", "Twister", "16 nm" },
{ 0x006, "A10 Fusion", "Zephyr", "16 nm" },
{ 0x007, "A10 Fusion", "Hurricane", "16 nm" },
{ 0x008, "A11 Bionic", "Monsoon", "10 nm" },
{ 0x009, "A11 Bionic", "Mistral", "10 nm" },
{ 0x00b, "A12", "Vortex", "TSMC N7" },
{ 0x00c, "A12", "Tempest", "TSMC N7" },
{ 0x00f, "M9", "Tempest", "TSMC N7" },
{ 0x010, "A12X Bionic", "Vortex", "TSMC N7" },
{ 0x011, "A12X Bionic", "Tempest", "TSMC N7" },
{ 0x012, "A13 Bionic", "Lightning", "TSMC N7P" },
{ 0x013, "A13 Bionic", "Thunder", "TSMC N7P" },
{ 0x020, "A14", "Icestorm", "TSMC N5" },
{ 0x021, "A14", "Firestorm", "TSMC N5" },
{ 0x022, "M1", "Icestorm", "TSMC N5" },
{ 0x023, "M1", "Firestorm", "TSMC N5" },
{ 0x024, "M1 Pro", "Icestorm", "TSMC N5" },
{ 0x025, "M1 Pro", "Firestorm", "TSMC N5" },
{ 0x026, "M10", "Thunder", "TSMC N7P" },
{ 0x028, "M1 Max", "Icestorm", "TSMC N5" },
{ 0x029, "M1 Max", "Firestorm", "TSMC N5" },
{ 0x030, "A15", "Blizzard", "TSMC N5P" },
{ 0x031, "A15", "Avalanche", "TSMC N5P" },
{ 0x032, "M2", "Blizzard", "TSMC N5P" },
{ 0x033, "M2", "Avalanche", "TSMC N5P" },
{ 0x034, "M2 Pro", "Blizzard", "TSMC N5P" },
{ 0x035, "M2 Pro", "Avalanche", "TSMC N5P" },
{ 0x036, "A16", "Sawtooth", "TSMC N4P" },
{ 0x037, "A16", "Everest", "TSMC N4P" },
{ 0x038, "M2 Max", "Blizzard", "TSMC N5P" },
{ 0x039, "M2 Max", "Avalanche", "TSMC N5P" },
{ -1, "unknown", "", UNKN_STR },
};
static const struct arm_id_part faraday_part[] = {
{ 0x526, "FA526", "" },
{ 0x626, "FA626", "" },
{ -1, "unknown", "" },
{ 0x526, "FA526", "", UNKN_STR },
{ 0x626, "FA626", "", UNKN_STR },
{ -1, "unknown", "", UNKN_STR },
};
static const struct arm_id_part intel_part[] = {
{ 0x200, "i80200", "" },
{ 0x210, "PXA250A", "" },
{ 0x212, "PXA210A", "" },
{ 0x242, "i80321-400", "" },
{ 0x243, "i80321-600", "" },
{ 0x290, "PXA250B/PXA26x", "" },
{ 0x292, "PXA210B", "" },
{ 0x2c2, "i80321-400-B0", "" },
{ 0x2c3, "i80321-600-B0", "" },
{ 0x2d0, "PXA250C/PXA255/PXA26x", "" },
{ 0x2d2, "PXA210C", "" },
{ 0x411, "PXA27x", "" },
{ 0x41c, "IPX425-533", "" },
{ 0x41d, "IPX425-400", "" },
{ 0x41f, "IPX425-266", "" },
{ 0x682, "PXA32x", "" },
{ 0x683, "PXA930/PXA935", "" },
{ 0x688, "PXA30x", "" },
{ 0x689, "PXA31x", "" },
{ 0xb11, "SA1110", "" },
{ 0xc12, "IPX1200", "" },
{ -1, "unknown", "" },
{ 0x200, "i80200", "", UNKN_STR },
{ 0x210, "PXA250A", "", UNKN_STR },
{ 0x212, "PXA210A", "", UNKN_STR },
{ 0x242, "i80321-400", "", UNKN_STR },
{ 0x243, "i80321-600", "", UNKN_STR },
{ 0x290, "PXA250B/PXA26x", "", UNKN_STR },
{ 0x292, "PXA210B", "", UNKN_STR },
{ 0x2c2, "i80321-400-B0", "", UNKN_STR },
{ 0x2c3, "i80321-600-B0", "", UNKN_STR },
{ 0x2d0, "PXA250C/PXA255/PXA26x", "", UNKN_STR },
{ 0x2d2, "PXA210C", "", UNKN_STR },
{ 0x411, "PXA27x", "", UNKN_STR },
{ 0x41c, "IPX425-533", "", UNKN_STR },
{ 0x41d, "IPX425-400", "", UNKN_STR },
{ 0x41f, "IPX425-266", "", UNKN_STR },
{ 0x682, "PXA32x", "", UNKN_STR },
{ 0x683, "PXA930/PXA935", "", UNKN_STR },
{ 0x688, "PXA30x", "", UNKN_STR },
{ 0x689, "PXA31x", "", UNKN_STR },
{ 0xb11, "SA1110", "", UNKN_STR },
{ 0xc12, "IPX1200", "", UNKN_STR },
{ -1, "unknown", "", UNKN_STR },
};
static const struct arm_id_part fujitsu_part[] = {
{ 0x001, "A64FX", "" },
{ -1, "unknown", "" },
{ 0x001, "A64FX", "", "7 nm" },
{ -1, "unknown", "", UNKN_STR },
};
static const struct arm_id_part hisi_part[] = {
{ 0xd01, "TaiShan-v110", "" }, /* used in Kunpeng-920 SoC */
{ 0xd02, "TaiShan-v120", "" }, /* used in Kirin 990A and 9000S SoCs */
{ 0xd40, "Cortex-A76", "" }, /* HiSilicon uses this ID though advertises A76 */
{ 0xd41, "Cortex-A77", "" }, /* HiSilicon uses this ID though advertises A77 */
{ -1, "unknown", "" },
{ 0xd01, "TaiShan-v110", "", UNKN_STR }, /* used in Kunpeng-920 SoC */
{ 0xd02, "TaiShan-v120", "", UNKN_STR }, /* used in Kirin 990A and 9000S SoCs */
{ 0xd40, "Cortex-A76", "", UNKN_STR }, /* HiSilicon uses this ID though advertises A76 */
{ 0xd41, "Cortex-A77", "", UNKN_STR }, /* HiSilicon uses this ID though advertises A77 */
{ -1, "unknown", "", UNKN_STR },
};
static const struct arm_id_part ampere_part[] = {
{ 0xac3, "Ampere-1", "" },
{ 0xac4, "Ampere-1a", "" },
{ -1, "unknown", "" },
{ 0xac3, "Ampere-1", "", UNKN_STR },
{ 0xac4, "Ampere-1a", "", UNKN_STR },
{ -1, "unknown", "", UNKN_STR },
};
static const struct arm_id_part ft_part[] = {
{ 0x303, "FTC310", "" },
{ 0x660, "FTC660", "" },
{ 0x661, "FTC661", "" },
{ 0x662, "FTC662", "" },
{ 0x663, "FTC663", "" },
{ 0x664, "FTC664", "" },
{ 0x862, "FTC862", "" },
{ -1, "unknown", "" },
{ 0x303, "FTC310", "", UNKN_STR },
{ 0x660, "FTC660", "", UNKN_STR },
{ 0x661, "FTC661", "", UNKN_STR },
{ 0x662, "FTC662", "", UNKN_STR },
{ 0x663, "FTC663", "", UNKN_STR },
{ 0x664, "FTC664", "", UNKN_STR },
{ 0x862, "FTC862", "", UNKN_STR },
{ -1, "unknown", "", UNKN_STR },
};
static const struct arm_id_part ms_part[] = {
{ 0xd49, "Azure-Cobalt-100", "" },
{ -1, "unknown", "" },
{ 0xd49, "Azure-Cobalt-100", "", UNKN_STR },
{ -1, "unknown", "", UNKN_STR },
};
static const struct arm_id_part unknown_part[] = {
{ -1, "unknown", "" },
{ -1, "unknown", "", UNKN_STR },
};
/* Implementers list */
@ -2545,9 +2547,10 @@ int cpuid_identify_arm(struct cpu_raw_data_t* raw, struct cpu_id_t* data)
const struct arm_hw_impl* hw_impl = get_cpu_implementer_from_code(data->arm.implementer);
const struct arm_id_part* id_part = get_cpu_implementer_parts(hw_impl, data->arm.part_num);
data->vendor = hw_impl->vendor;
snprintf(data->vendor_str, VENDOR_STR_MAX, "%s", hw_impl->name);
snprintf(data->brand_str, BRAND_STR_MAX, "%s", id_part->name);
snprintf(data->cpu_codename, CODENAME_STR_MAX,"%s", id_part->codename);
strncpy(data->vendor_str, hw_impl->name, VENDOR_STR_MAX);
strncpy(data->brand_str, id_part->name, BRAND_STR_MAX);
strncpy(data->cpu_codename, id_part->codename, CODENAME_STR_MAX);
strncpy(data->technology_node, id_part->technology, TECHNOLOGY_STR_MAX);
use_cpuid_scheme = (decode_arm_architecture_version_by_midr(raw, data) == false);
load_arm_features(raw, data, &ext_status);
if (use_cpuid_scheme)

62
libcpuid/recog_centaur.c
View file

@ -34,55 +34,55 @@
const struct match_entry_t cpudb_centaur[] = {
// F M S EF EM #cores L2$ L3$ Pattern Name
{ -1, -1, -1, -1, -1, -1, -1, -1, { "", 0 }, "Unknown Centaur CPU" },
// F M S EF EM #cores L2$ L3$ Pattern Name
// F M S EF EM #cores L2$ L3$ Pattern Codename Technology
{ -1, -1, -1, -1, -1, -1, -1, -1, { "", 0 }, "Unknown Centaur CPU", "" },
// F M S EF EM #cores L2$ L3$ Pattern Codename Technology
/* VIA */
// F M S EF EM #cores L2$ L3$ Pattern Name
{ 6, -1, -1, -1, -1, -1, -1, -1, { "VIA", 2 }, "Unknown VIA CPU" },
// F M S EF EM #cores L2$ L3$ Pattern Codename Technology
{ 6, -1, -1, -1, -1, -1, -1, -1, { "VIA", 2 }, "Unknown VIA CPU", "" },
/* Samuel (2000, 180 nm) */
{ 6, 6, -1, -1, -1, -1, -1, -1, { "VIA Samuel", 4 }, "VIA Cyrix III (Samuel)" },
{ 6, 6, -1, -1, -1, -1, -1, -1, { "VIA Samuel", 4 }, "VIA Cyrix III (Samuel)", "180 nm" },
/* Samuel 2 (2001, 150 nm) */
{ 6, 7, -1, -1, -1, -1, -1, -1, { "VIA Samuel 2", 6 }, "VIA C3 (Samuel 2)" },
{ 6, 7, -1, -1, -1, -1, -1, -1, { "VIA Samuel 2", 6 }, "VIA C3 (Samuel 2)", "150 nm" },
/* Ezra (2001, 130 nm) */
{ 6, 7, -1, -1, -1, -1, -1, -1, { "VIA Ezra", 4 }, "VIA C3 (Ezra)" },
{ 6, 8, -1, -1, -1, -1, -1, -1, { "VIA C3 Ezra", 6 }, "VIA C3 (Ezra-T)" },
{ 6, 7, -1, -1, -1, -1, -1, -1, { "VIA Ezra", 4 }, "VIA C3 (Ezra)", "130 nm" },
{ 6, 8, -1, -1, -1, -1, -1, -1, { "VIA C3 Ezra", 6 }, "VIA C3 (Ezra-T)", "130 nm" },
/* Nehemiah (2003, 130 nm) */
{ 6, 9, -1, -1, -1, -1, -1, -1, { "VIA Nehemiah", 4 }, "VIA C3 (Nehemiah)" },
{ 6, 9, -1, -1, -1, -1, -1, -1, { "VIA Nehemiah", 4 }, "VIA C3 (Nehemiah)", "130 nm" },
/* Esther (2005, 90 nm) */
{ 6, 10, -1, -1, -1, -1, -1, -1, { "VIA Esther", 4 }, "VIA C7 (Esther)" },
{ 6, 13, -1, -1, -1, -1, -1, -1, { "VIA C7-M", 4 }, "VIA C7-M (Esther)" },
{ 6, 10, -1, -1, -1, -1, -1, -1, { "VIA Esther", 4 }, "VIA C7 (Esther)", "90 nm" },
{ 6, 13, -1, -1, -1, -1, -1, -1, { "VIA C7-M", 4 }, "VIA C7-M (Esther)", "90 nm" },
/* Isaiah (2008, 65 nm) */
{ 6, 15, -1, -1, -1, -1, -1, -1, { "VIA Nano", 4 }, "VIA Nano (Isaiah)" },
{ 6, 15, -1, -1, -1, 1, -1, -1, { "VIA Nano", 4 }, "VIA Nano (Isaiah)" },
{ 6, 15, -1, -1, -1, 2, -1, -1, { "VIA Nano", 4 }, "VIA Nano X2 (Isaiah)" },
{ 6, 15, -1, -1, -1, -1, -1, -1, { "VIA QuadCore", 4 }, "VIA Nano X4 (Isaiah)" },
{ 6, 15, -1, -1, -1, 4, -1, -1, { "VIA Eden X4", 6 }, "VIA Eden X4 (Isaiah)" },
// F M S EF EM #cores L2$ L3$ Pattern Name
{ 6, 15, -1, -1, -1, -1, -1, -1, { "VIA Nano", 4 }, "VIA Nano (Isaiah)", "65 nm" },
{ 6, 15, -1, -1, -1, 1, -1, -1, { "VIA Nano", 4 }, "VIA Nano (Isaiah)", "65 nm" },
{ 6, 15, -1, -1, -1, 2, -1, -1, { "VIA Nano", 4 }, "VIA Nano X2 (Isaiah)", "65 nm" },
{ 6, 15, -1, -1, -1, -1, -1, -1, { "VIA QuadCore", 4 }, "VIA Nano X4 (Isaiah)", "65 nm" },
{ 6, 15, -1, -1, -1, 4, -1, -1, { "VIA Eden X4", 6 }, "VIA Eden X4 (Isaiah)", "65 nm" },
// F M S EF EM #cores L2$ L3$ Pattern Codename Technology
/* Zhaoxin */
// F M S EF EM #cores L2$ L3$ Pattern Name
{ 7, -1, -1, -1, -1, -1, -1, -1, {"ZHAOXIN", 2 }, "Unknown Zhaoxin CPU" },
// F M S EF EM #cores L2$ L3$ Pattern Codename Technology
{ 7, -1, -1, -1, -1, -1, -1, -1, {"ZHAOXIN", 2 }, "Unknown Zhaoxin CPU" "" },
/* Zhangjiang (2015, 28 nm) */
{ 7, -1, -1, -1, 15, -1, -1, -1, { "ZHAOXIN KaisHeng KH-C", 8 }, "Zhaoxin KaisHeng (ZhangJiang)" }, // C+ (4000)
{ 7, -1, -1, -1, 15, -1, -1, -1, { "ZHAOXIN KaiXian ZX-C", 8 }, "Zhaoxin KaiXian (ZhangJiang)" }, // C/C+ (4000)
{ 7, -1, -1, -1, 15, -1, -1, -1, { "ZHAOXIN KaisHeng KH-C", 8 }, "Zhaoxin KaisHeng (ZhangJiang)", "28 nm" }, // C+ (4000)
{ 7, -1, -1, -1, 15, -1, -1, -1, { "ZHAOXIN KaiXian ZX-C", 8 }, "Zhaoxin KaiXian (ZhangJiang)", "28 nm" }, // C/C+ (4000)
/* WuDaoKou (2017, 28 nm) */
{ 7, -1, -1, -1, 27, -1, -1, -1, { "ZHAOXIN KaisHeng KH-20###", 8 }, "Zhaoxin KaisHeng (WuDaoKou)" }, // KH (20000)
{ 7, -1, -1, -1, 27, -1, -1, -1, { "ZHAOXIN KaiXian KX-5###", 8 }, "Zhaoxin KaiXian (WuDaoKou)" }, // KX (5000)
{ 7, -1, -1, -1, 27, -1, -1, -1, { "ZHAOXIN KaiXian KX-U5###", 8 }, "Zhaoxin KaiXian (WuDaoKou)" }, // KX (U5000)
{ 7, -1, -1, -1, 27, -1, -1, -1, { "ZHAOXIN KaisHeng KH-20###", 8 }, "Zhaoxin KaisHeng (WuDaoKou)", "28 nm" }, // KH (20000)
{ 7, -1, -1, -1, 27, -1, -1, -1, { "ZHAOXIN KaiXian KX-5###", 8 }, "Zhaoxin KaiXian (WuDaoKou)", "28 nm" }, // KX (5000)
{ 7, -1, -1, -1, 27, -1, -1, -1, { "ZHAOXIN KaiXian KX-U5###", 8 }, "Zhaoxin KaiXian (WuDaoKou)", "28 nm" }, // KX (U5000)
/* LuJiaZui (2019, 16 nm) */
{ 7, -1, -1, -1, 59, -1, -1, -1, { "ZHAOXIN KaisHeng KH-30###", 8 }, "Zhaoxin KaisHeng (LuJiaZui)" }, // KH (30000)
{ 7, -1, -1, -1, 59, -1, -1, -1, { "ZHAOXIN KaiXian KX-6###", 8 }, "Zhaoxin KaiXian (LuJiaZui)" }, // KX (6000)
{ 7, -1, -1, -1, 59, -1, -1, -1, { "ZHAOXIN KaiXian KX-U6###", 8 }, "Zhaoxin KaiXian (LuJiaZui)" }, // KX (U6000)
{ 7, -1, -1, -1, 59, -1, -1, -1, { "ZHAOXIN KaisHeng KH-30###", 8 }, "Zhaoxin KaisHeng (LuJiaZui)", "16 nm" }, // KH (30000)
{ 7, -1, -1, -1, 59, -1, -1, -1, { "ZHAOXIN KaiXian KX-6###", 8 }, "Zhaoxin KaiXian (LuJiaZui)", "16 nm" }, // KX (6000)
{ 7, -1, -1, -1, 59, -1, -1, -1, { "ZHAOXIN KaiXian KX-U6###", 8 }, "Zhaoxin KaiXian (LuJiaZui)", "16 nm" }, // KX (U6000)
/* Yongfeng (2022, 16 nm) */
{ 7, -1, -1, -1, 91, -1, -1, -1, { "ZHAOXIN KaisHeng KH-40###", 8 }, "Zhaoxin KaisHeng (Yongfeng)" }, // KH (40000)
{ 7, -1, -1, -1, 91, -1, -1, -1, { "ZHAOXIN KaiXian KX-7###", 8 }, "Zhaoxin KaiXian (Yongfeng)" }, // KX (7000)
// F M S EF EM #cores L2$ L3$ Pattern Name
{ 7, -1, -1, -1, 91, -1, -1, -1, { "ZHAOXIN KaisHeng KH-40###", 8 }, "Zhaoxin KaisHeng (Yongfeng)", "16 nm" }, // KH (40000)
{ 7, -1, -1, -1, 91, -1, -1, -1, { "ZHAOXIN KaiXian KX-7###", 8 }, "Zhaoxin KaiXian (Yongfeng)", "16 nm" }, // KX (7000)
// F M S EF EM #cores L2$ L3$ Pattern Codename Technology
};
int cpuid_identify_centaur(struct cpu_raw_data_t* raw, struct cpu_id_t* data, struct internal_id_info_t* internal)

885
libcpuid/recog_intel.c
View file

@ -32,499 +32,498 @@
const struct match_entry_t cpudb_intel[] = {
// F M S EF EM #cores L2$ L3$ Pattern Name
{ -1, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown Intel CPU" },
// F M S EF EM #cores L2$ L3$ Pattern Codename Technology
{ -1, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown Intel CPU", UNKN_STR },
/* i486 */
{ 4, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown i486" },
{ 4, 0, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX-25/33" },
{ 4, 1, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX-50" },
{ 4, 2, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 SX" },
{ 4, 3, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX2" },
{ 4, 4, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 SL" },
{ 4, 5, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 SX2" },
{ 4, 7, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX2 WriteBack" },
{ 4, 8, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX4" },
{ 4, 9, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX4 WriteBack" },
{ 4, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown i486", UNKN_STR },
{ 4, 0, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX-25/33", UNKN_STR },
{ 4, 1, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX-50", UNKN_STR },
{ 4, 2, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 SX", UNKN_STR },
{ 4, 3, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX2", UNKN_STR },
{ 4, 4, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 SL", UNKN_STR },
{ 4, 5, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 SX2", UNKN_STR },
{ 4, 7, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX2 WriteBack", UNKN_STR },
{ 4, 8, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX4", UNKN_STR },
{ 4, 9, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX4 WriteBack", UNKN_STR },
/* P6 CPUs */
{ 5, 0, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium A-Step" },
{ 5, 1, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 1 (0.8u)" },
{ 5, 2, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 1 (0.35u)" },
{ 5, 3, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium OverDrive" },
{ 5, 4, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 1 (0.35u)" },
{ 5, 7, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 1 (0.35u)" },
{ 5, 8, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium MMX (0.25u)" },
{ 5, 0, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium A-Step", UNKN_STR },
{ 5, 1, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 1", "0.8 µm" },
{ 5, 2, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 1", "0.35 µm" },
{ 5, 3, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium OverDrive", UNKN_STR },
{ 5, 4, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 1", "0.35 µm" },
{ 5, 7, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 1", "0.35 µm" },
{ 5, 8, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium MMX", "0.25 µm" },
/* P6 CPUs */
{ 6, 0, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium Pro" },
{ 6, 1, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium Pro" },
{ 6, 3, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium II (Klamath)" },
{ 6, 5, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium II (Deschutes)" },
{ 6, 5, -1, -1, -1, 1, -1, -1, { "Pentium(R) M", 4 }, "Mobile Pentium II (Tonga)" },
{ 6, 6, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium II (Dixon)" },
{ 6, 3, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-II Xeon (Klamath)" },
{ 6, 5, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-II Xeon (Drake)" },
{ 6, 6, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-II Xeon (Dixon)" },
{ 6, 5, -1, -1, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-II Celeron (Covington)" },
{ 6, 6, -1, -1, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-II Celeron (Mendocino)" },
{ 6, 7, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium III (Katmai)" },
{ 6, 8, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium III (Coppermine)" },
{ 6, 10, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium III (Coppermine)" },
{ 6, 11, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium III (Tualatin)" },
{ 6, 11, -1, -1, -1, 1, 512, -1, { "Pentium(R)", 2 }, "Pentium III (Tualatin)" },
{ 6, 7, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-III Xeon (Tanner)" },
{ 6, 8, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-III Xeon (Cascades)" },
{ 6, 10, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-III Xeon (Cascades)" },
{ 6, 11, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-III Xeon (Tualatin)" },
{ 6, 7, -1, -1, -1, 1, 128, -1, { "Celeron(R)", 2 }, "P-III Celeron (Katmai)" },
{ 6, 8, -1, -1, -1, 1, 128, -1, { "Celeron(R)", 2 }, "P-III Celeron (Coppermine)" },
{ 6, 10, -1, -1, -1, 1, 128, -1, { "Celeron(R)", 2 }, "P-III Celeron (Coppermine)" },
{ 6, 11, -1, -1, -1, 1, 256, -1, { "Celeron(R)", 2 }, "P-III Celeron (Tualatin)" },
{ 6, 0, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium Pro", UNKN_STR },
{ 6, 1, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium Pro", UNKN_STR },
{ 6, 3, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium II (Klamath)", "0.18 µm" },
{ 6, 5, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium II (Deschutes)", "0.18 µm" },
{ 6, 5, -1, -1, -1, 1, -1, -1, { "Pentium(R) M", 4 }, "Mobile Pentium II (Tonga)", "0.18 µm" },
{ 6, 6, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium II (Dixon)", "0.25 µm" },
{ 6, 3, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-II Xeon (Klamath)", "0.35 µm" },
{ 6, 5, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-II Xeon (Drake)", "0.25 µm" },
{ 6, 6, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-II Xeon (Dixon)", "0.25 µm" },
{ 6, 5, -1, -1, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-II Celeron (Covington)", "0.25 µm" },
{ 6, 6, -1, -1, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-II Celeron (Mendocino)", "0.25 µm" },
{ 6, 7, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium III (Katmai)", "0.25 µm" },
{ 6, 8, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium III (Coppermine)", "0.18 µm" },
{ 6, 10, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium III (Coppermine)", "0.18 µm" },
{ 6, 11, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium III (Tualatin)", "0.13 µm" },
{ 6, 11, -1, -1, -1, 1, 512, -1, { "Pentium(R)", 2 }, "Pentium III (Tualatin)", "0.13 µm" },
{ 6, 7, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-III Xeon (Tanner)", "0.25 µm" },
{ 6, 8, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-III Xeon (Cascades)", "0.18 µm" },
{ 6, 10, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-III Xeon (Cascades)", "0.18 µm" },
{ 6, 11, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-III Xeon (Tualatin)", "0.13 µm" },
{ 6, 7, -1, -1, -1, 1, 128, -1, { "Celeron(R)", 2 }, "P-III Celeron (Katmai)", "0.25 µm" },
{ 6, 8, -1, -1, -1, 1, 128, -1, { "Celeron(R)", 2 }, "P-III Celeron (Coppermine)", "0.18 µm" },
{ 6, 10, -1, -1, -1, 1, 128, -1, { "Celeron(R)", 2 }, "P-III Celeron (Coppermine)", "0.18 µm" },
{ 6, 11, -1, -1, -1, 1, 256, -1, { "Celeron(R)", 2 }, "P-III Celeron (Tualatin)", "0.13 µm" },
/* NetBurst CPUs */
/* Willamette (180nm): */
{ 15, 0, -1, 15, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 4 (Willamette)" },
{ 15, 1, -1, 15, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 4 (Willamette)" },
{ 15, 0, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Mobile P-4 (Willamette)" },
{ 15, 1, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Mobile P-4 (Willamette)" },
{ 15, 1, -1, 15, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-4 Celeron (Willamette)" },
{ 15, 0, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Foster)" },
{ 15, 1, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Foster)" },
/* Northwood / Mobile Pentium 4 / Banias (130nm): */
{ 15, 2, -1, 15, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 4 (Northwood)" },
{ 15, 2, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Mobile P-4 (Northwood)" },
{ 15, 2, -1, 15, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-4 Celeron (Northwood)" },
{ 6, 9, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium M (Banias)" },
{ 6, 9, -1, -1, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Pentium M (Banias)" },
{ 6, 9, -1, -1, -1, 1, -1, -1, { "Celeron(R)", 2 }, "Celeron M (Banias)" },
{ 6, 9, -1, -1, -1, 1, -1, -1, { "Celeron(R) M", 4 }, "Celeron M (Banias)" },
{ 15, 2, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Prestonia)" },
{ 15, 2, -1, 15, -1, 1, -1, -1, { "Xeon(TM) MP", 4 }, "Xeon (Gallatin)" },
/* Prescott / Dothan (90nm): */
{ 15, 3, -1, 15, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 4 (Prescott)" },
{ 15, 4, -1, 15, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 4 (Prescott)" },
{ 15, 3, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Mobile P-4 (Prescott)" },
{ 15, 4, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Mobile P-4 (Prescott)" },
{ 15, 3, -1, 15, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-4 Celeron D (Prescott)" },
{ 15, 4, -1, 15, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-4 Celeron D (Prescott)" },
{ 15, 4, -1, 15, -1, 1, -1, -1, { "Pentium(R) D", 4 }, "Pentium D (SmithField)" },
{ 6, 13, -1, -1, -1, 1, -1, -1, { "Pentium(R) M", 4 }, "Pentium M (Dothan)" },
{ 6, 13, -1, -1, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Pentium M (Dothan)" },
{ 6, 13, -1, -1, -1, 1, -1, -1, { "Celeron(R)", 2 }, "Celeron M (Dothan)" },
{ 6, 13, -1, -1, -1, 1, -1, -1, { "Celeron(R) M", 4 }, "Celeron M (Dothan)" },
{ 15, 3, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Nocona)" },
{ 15, 4, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Nocona)" },
{ 15, 4, 3, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Irwindale)" },
{ 15, 4, 10, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Irwindale)" },
{ 15, 4, 1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Cranford)" },
{ 15, 4, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Potomac)" },
/* Cedar Mill / Yonah / Presler (65nm): */
{ 15, 6, -1, 15, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 4 (Cedar Mill)" },
{ 15, 6, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Mobile P-4 (Cedar Mill)" },
{ 15, 6, -1, 15, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-4 Celeron D (Cedar Mill)" },
{ 6, 14, -1, -1, -1, 1, -1, -1, { "Core(TM) [UT]1###", 6 }, "Core Solo (Yonah)" },
{ 6, 14, -1, -1, -1, 2, -1, -1, { "Core(TM) Duo [UTL]2###", 6 }, "Core Duo (Yonah)" },
{ 15, 6, -1, 15, -1, 1, -1, -1, { "Pentium(R) D", 4 }, "Pentium D (Presler)" },
{ 15, 6, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Dempsey)" },
/* Willamette (180 nm): */
{ 15, 0, -1, 15, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 4 (Willamette)", "0.18 µm" },
{ 15, 1, -1, 15, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 4 (Willamette)", "0.18 µm" },
{ 15, 0, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Mobile P-4 (Willamette)", "0.18 µm" },
{ 15, 1, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Mobile P-4 (Willamette)", "0.18 µm" },
{ 15, 1, -1, 15, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-4 Celeron (Willamette)", "0.18 µm" },
{ 15, 0, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Foster)", "0.18 µm" },
{ 15, 1, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Foster)", "0.18 µm" },
/* Northwood / Mobile Pentium 4 / Banias (130 nm): */
{ 15, 2, -1, 15, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 4 (Northwood)", "0.13 µm" },
{ 15, 2, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Mobile P-4 (Northwood)", "0.13 µm" },
{ 15, 2, -1, 15, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-4 Celeron (Northwood)", "0.13 µm" },
{ 6, 9, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium M (Banias)", "0.13 µm" },
{ 6, 9, -1, -1, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Pentium M (Banias)", "0.13 µm" },
{ 6, 9, -1, -1, -1, 1, -1, -1, { "Celeron(R)", 2 }, "Celeron M (Banias)", "0.13 µm" },
{ 6, 9, -1, -1, -1, 1, -1, -1, { "Celeron(R) M", 4 }, "Celeron M (Banias)", "0.13 µm" },
{ 15, 2, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Prestonia)", "0.13 µm" },
{ 15, 2, -1, 15, -1, 1, -1, -1, { "Xeon(TM) MP", 4 }, "Xeon (Gallatin)", "0.13 µm" },
/* Prescott / Dothan (90 nm): */
{ 15, 3, -1, 15, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 4 (Prescott)", "90 nm" },
{ 15, 4, -1, 15, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 4 (Prescott)", "90 nm" },
{ 15, 3, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Mobile P-4 (Prescott)", "90 nm" },
{ 15, 4, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Mobile P-4 (Prescott)", "90 nm" },
{ 15, 3, -1, 15, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-4 Celeron D (Prescott)", "90 nm" },
{ 15, 4, -1, 15, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-4 Celeron D (Prescott)", "90 nm" },
{ 15, 4, -1, 15, -1, 1, -1, -1, { "Pentium(R) D", 4 }, "Pentium D (SmithField)", "90 nm" },
{ 6, 13, -1, -1, -1, 1, -1, -1, { "Pentium(R) M", 4 }, "Pentium M (Dothan)", "90 nm" },
{ 6, 13, -1, -1, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Pentium M (Dothan)", "90 nm" },
{ 6, 13, -1, -1, -1, 1, -1, -1, { "Celeron(R)", 2 }, "Celeron M (Dothan)", "90 nm" },
{ 6, 13, -1, -1, -1, 1, -1, -1, { "Celeron(R) M", 4 }, "Celeron M (Dothan)", "90 nm" },
{ 15, 3, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Nocona)", "90 nm" },
{ 15, 4, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Nocona)", "90 nm" },
{ 15, 4, 3, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Irwindale)", "90 nm" },
{ 15, 4, 10, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Irwindale)", "90 nm" },
{ 15, 4, 1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Cranford)", "90 nm" },
{ 15, 4, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Potomac)", "90 nm" },
/* Cedar Mill / Yonah / Presler (65 nm): */
{ 15, 6, -1, 15, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 4 (Cedar Mill)", "65 nm" },
{ 15, 6, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 4 }, "Mobile P-4 (Cedar Mill)", "65 nm" },
{ 15, 6, -1, 15, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-4 Celeron D (Cedar Mill)", "65 nm" },
{ 6, 14, -1, -1, -1, 1, -1, -1, { "Core(TM) [UT]1###", 6 }, "Core Solo (Yonah)", "65 nm" },
{ 6, 14, -1, -1, -1, 2, -1, -1, { "Core(TM) Duo [UTL]2###", 6 }, "Core Duo (Yonah)", "65 nm" },
{ 15, 6, -1, 15, -1, 1, -1, -1, { "Pentium(R) D", 4 }, "Pentium D (Presler)", "65 nm" },
{ 15, 6, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Dempsey)", "65 nm" },
/* Bonnell CPUs (first generation cores, 45nm): */
{ 6, 12, -1, -1, -1, -1, -1, -1, { "Atom(TM) Z5##", 6 }, "Atom (Silverthorne)" },
{ 6, 12, -1, -1, -1, -1, -1, -1, { "Atom(TM) N2##", 6 }, "Atom (Diamondville)" },
{ 6, 12, -1, -1, -1, -1, -1, -1, { "Atom(TM) [23]##", 6 }, "Atom (Diamondville)" },
/* Bonnell CPUs (second generation cores, 45nm): */
{ 6, 12, -1, -1, -1, -1, -1, -1, { "Atom(TM) [ND][45]##", 6 }, "Atom (Pineview)" },
{ 6, 12, -1, -1, -1, -1, -1, -1, { "Atom(TM) Z6##", 6 }, "Atom (Lincroft)" },
/* Bonnell CPUs (third generation cores, 32nm): */
{ 6, 12, -1, -1, -1, -1, -1, -1, { "Atom(TM) [ND]2###", 6 }, "Atom (Cedarview)" },
{ 6, 6, -1, -1, -1, -1, -1, -1, { "Atom(TM) [ND]2###", 6 }, "Atom (Cedarview)" },
/* Bonnell CPUs (first generation cores, 45 nm): */
{ 6, 12, -1, -1, -1, -1, -1, -1, { "Atom(TM) Z5##", 6 }, "Atom (Silverthorne)", "45 nm" },
{ 6, 12, -1, -1, -1, -1, -1, -1, { "Atom(TM) N2##", 6 }, "Atom (Diamondville)", "45 nm" },
{ 6, 12, -1, -1, -1, -1, -1, -1, { "Atom(TM) [23]##", 6 }, "Atom (Diamondville)", "45 nm" },
/* Bonnell CPUs (second generation cores, 45 nm): */
{ 6, 12, -1, -1, -1, -1, -1, -1, { "Atom(TM) [ND][45]##", 6 }, "Atom (Pineview)", "45 nm" },
{ 6, 12, -1, -1, -1, -1, -1, -1, { "Atom(TM) Z6##", 6 }, "Atom (Lincroft)", "45 nm" },
/* Bonnell CPUs (third generation cores, 32 nm): */
{ 6, 12, -1, -1, -1, -1, -1, -1, { "Atom(TM) [ND]2###", 6 }, "Atom (Cedarview)", "32 nm" },
{ 6, 6, -1, -1, -1, -1, -1, -1, { "Atom(TM) [ND]2###", 6 }, "Atom (Cedarview)", "32 nm" },
/* Conroe CPUs (65nm): https://en.wikipedia.org/wiki/Conroe_(microprocessor) */
{ 6, 15, -1, -1, -1, 2, 2048, -1, { "Core(TM)2 Duo E6###", 8 }, "Core 2 Duo (Conroe-2M)" },
{ 6, 15, -1, -1, -1, 2, 4096, -1, { "Core(TM)2 Duo E6###", 8 }, "Core 2 Duo (Conroe)" },
{ 6, 15, -1, -1, -1, 2, 4096, -1, { "Core(TM)2 6###", 4 }, "Core 2 Duo (Conroe)" },
{ 6, 15, -1, -1, -1, 4, 4096, -1, { "Core(TM)2 Quad Q6###", 8 }, "Core 2 Quad (Kentsfield)" },
{ 6, 15, -1, -1, -1, 2, 2048, -1, { "Core(TM)2 Duo E4###", 8 }, "Core 2 Duo (Allendale)" },
{ 6, 15, -1, -1, 15, 2, 2048, -1, { "Core(TM)2 U7###", 6 }, "Core 2 Duo (Merom-2M)" },
{ 6, 15, -1, -1, 15, 2, 2048, -1, { "Core(TM)2 T[57]###", 6 }, "Core 2 Duo (Merom-2M)" },
{ 6, 15, -1, -1, 15, 2, 4096, -1, { "Core(TM)2 T7###", 6 }, "Core 2 Duo (Merom)" },
{ 6, 15, -1, -1, 15, 2, 4096, -1, { "Core(TM)2 S[LP]7###", 6 }, "Core 2 Duo (Merom)" },
{ 6, 15, -1, -1, 15, 2, 4096, -1, { "Core(TM)2 L7###", 6 }, "Core 2 Duo (Merom)" },
{ 6, 15, -1, -1, 15, 2, -1, -1, { "Pentium(R) Dual E2###", 8 }, "Pentium Dual-Core (Allendale)" },
{ 6, 15, -1, -1, 15, 2, -1, -1, { "Celeron(R) E1###", 6 }, "Celeron (Allendale)" },
{ 6, 6, -1, -1, 22, 1, -1, -1, { "Celeron(R) [24]##", 4 }, "Celeron (Conroe-L)" },
/* Conroe CPUs (65 nm): https://en.wikipedia.org/wiki/Conroe_(microprocessor) */
{ 6, 15, -1, -1, -1, 2, 2048, -1, { "Core(TM)2 Duo E6###", 8 }, "Core 2 Duo (Conroe-2M)", "65 nm" },
{ 6, 15, -1, -1, -1, 2, 4096, -1, { "Core(TM)2 Duo E6###", 8 }, "Core 2 Duo (Conroe)", "65 nm" },
{ 6, 15, -1, -1, -1, 2, 4096, -1, { "Core(TM)2 6###", 4 }, "Core 2 Duo (Conroe)", "65 nm" },
{ 6, 15, -1, -1, -1, 4, 4096, -1, { "Core(TM)2 Quad Q6###", 8 }, "Core 2 Quad (Kentsfield)", "65 nm" },
{ 6, 15, -1, -1, -1, 2, 2048, -1, { "Core(TM)2 Duo E4###", 8 }, "Core 2 Duo (Allendale)", "65 nm" },
{ 6, 15, -1, -1, 15, 2, 2048, -1, { "Core(TM)2 U7###", 6 }, "Core 2 Duo (Merom-2M)", "65 nm" },
{ 6, 15, -1, -1, 15, 2, 2048, -1, { "Core(TM)2 T[57]###", 6 }, "Core 2 Duo (Merom-2M)", "65 nm" },
{ 6, 15, -1, -1, 15, 2, 4096, -1, { "Core(TM)2 T7###", 6 }, "Core 2 Duo (Merom)", "65 nm" },
{ 6, 15, -1, -1, 15, 2, 4096, -1, { "Core(TM)2 S[LP]7###", 6 }, "Core 2 Duo (Merom)", "65 nm" },
{ 6, 15, -1, -1, 15, 2, 4096, -1, { "Core(TM)2 L7###", 6 }, "Core 2 Duo (Merom)", "65 nm" },
{ 6, 15, -1, -1, 15, 2, -1, -1, { "Pentium(R) Dual E2###", 8 }, "Pentium Dual-Core (Allendale)", "65 nm" },
{ 6, 15, -1, -1, 15, 2, -1, -1, { "Celeron(R) E1###", 6 }, "Celeron (Allendale)", "65 nm" },
{ 6, 6, -1, -1, 22, 1, -1, -1, { "Celeron(R) [24]##", 4 }, "Celeron (Conroe-L)", "65 nm" },
/* Penryn CPUs (45nm): https://en.wikipedia.org/wiki/Penryn_(microarchitecture)#CPU_List */
{ 6, 7, -1, -1, 23, 2, 1024, -1, { "Celeron(R) E3###", 6 }, "Celeron (Wolfdale-3M)" },
{ 6, 7, -1, -1, 23, 2, 1024, -1, { "Pentium(R) E2###", 6 }, "Celeron (Wolfdale-3M)" },
{ 6, 7, -1, -1, 23, 2, 2048, -1, { "Pentium(R) E[56]###", 6 }, "Pentium (Wolfdale-3M)" },
{ 6, 7, -1, -1, 23, 2, 3072, -1, { "Core(TM)2 Duo E7###", 8 }, "Core 2 Duo (Wolfdale-3M)" },
{ 6, 7, -1, -1, 23, 2, 6144, -1, { "Core(TM)2 Duo E8###", 8 }, "Core 2 Duo (Wolfdale)" },
{ 6, 7, -1, -1, 23, 2, 1024, -1, { "Pentium(R) Dual-Core T4###", 8 }, "Pentium Dual-Core (Penryn-L)" },
{ 6, 7, -1, -1, 23, 1, 1024, -1, { "Celeron(R) [79]##", 4 }, "Celeron (Penryn-L)" },
{ 6, 7, -1, -1, 23, 2, 3072, -1, { "Core(TM)2 Duo SU[78]###", 8 }, "Core 2 Duo (Penryn-3M)" },
{ 6, 7, -1, -1, 23, 2, 3072, -1, { "Core(TM)2 Duo P[78]###", 8 }, "Core 2 Duo (Penryn-3M)" },
{ 6, 7, -1, -1, 23, 2, 2048, -1, { "Core(TM)2 Duo T6###", 8 }, "Core 2 Duo (Penryn-3M)" },
{ 6, 7, -1, -1, 23, 2, 3072, -1, { "Core(TM)2 Duo T8###", 8 }, "Core 2 Duo (Penryn-3M)" },
{ 6, 7, -1, -1, 23, 2, 6144, -1, { "Core(TM)2 Duo S[LP]9###", 8 }, "Core 2 Duo (Penryn)" },
{ 6, 7, -1, -1, 23, 2, 6144, -1, { "Core(TM)2 Duo [PT]9###", 8 }, "Core 2 Duo (Penryn)" },
{ 6, 7, -1, -1, 23, 2, 6144, -1, { "Core(TM)2 Duo E8###", 8 }, "Core 2 Duo (Penryn)" },
{ 6, 7, -1, -1, 23, 4, 2048, -1, { "Core(TM)2 Quad Q8###", 8 }, "Core 2 Quad (Yorkfield-6M)" }, // 2×2 MB L2$
{ 6, 7, -1, -1, 23, 4, 3072, -1, { "Core(TM)2 Quad Q9#0#", 8 }, "Core 2 Quad (Yorkfield-6M)" }, // 2×3 MB L2$
{ 6, 7, -1, -1, 23, 4, 6144, -1, { "Core(TM)2 Quad Q9#5#", 8 }, "Core 2 Quad (Yorkfield)" }, // 2×6 MB L2$
/* Penryn CPUs (45 nm): https://en.wikipedia.org/wiki/Penryn_(microarchitecture)#CPU_List */
{ 6, 7, -1, -1, 23, 2, 1024, -1, { "Celeron(R) E3###", 6 }, "Celeron (Wolfdale-3M)", "45 nm" },
{ 6, 7, -1, -1, 23, 2, 1024, -1, { "Pentium(R) E2###", 6 }, "Celeron (Wolfdale-3M)", "45 nm" },
{ 6, 7, -1, -1, 23, 2, 2048, -1, { "Pentium(R) E[56]###", 6 }, "Pentium (Wolfdale-3M)", "45 nm" },
{ 6, 7, -1, -1, 23, 2, 3072, -1, { "Core(TM)2 Duo E7###", 8 }, "Core 2 Duo (Wolfdale-3M)", "45 nm" },
{ 6, 7, -1, -1, 23, 2, 6144, -1, { "Core(TM)2 Duo E8###", 8 }, "Core 2 Duo (Wolfdale)", "45 nm" },
{ 6, 7, -1, -1, 23, 2, 1024, -1, { "Pentium(R) Dual-Core T4###", 8 }, "Pentium Dual-Core (Penryn-L)", "45 nm" },
{ 6, 7, -1, -1, 23, 1, 1024, -1, { "Celeron(R) [79]##", 4 }, "Celeron (Penryn-L)", "45 nm" },
{ 6, 7, -1, -1, 23, 2, 3072, -1, { "Core(TM)2 Duo SU[78]###", 8 }, "Core 2 Duo (Penryn-3M)", "45 nm" },
{ 6, 7, -1, -1, 23, 2, 3072, -1, { "Core(TM)2 Duo P[78]###", 8 }, "Core 2 Duo (Penryn-3M)", "45 nm" },
{ 6, 7, -1, -1, 23, 2, 2048, -1, { "Core(TM)2 Duo T6###", 8 }, "Core 2 Duo (Penryn-3M)", "45 nm" },
{ 6, 7, -1, -1, 23, 2, 3072, -1, { "Core(TM)2 Duo T8###", 8 }, "Core 2 Duo (Penryn-3M)", "45 nm" },
{ 6, 7, -1, -1, 23, 2, 6144, -1, { "Core(TM)2 Duo S[LP]9###", 8 }, "Core 2 Duo (Penryn)", "45 nm" },
{ 6, 7, -1, -1, 23, 2, 6144, -1, { "Core(TM)2 Duo [PT]9###", 8 }, "Core 2 Duo (Penryn)", "45 nm" },
{ 6, 7, -1, -1, 23, 2, 6144, -1, { "Core(TM)2 Duo E8###", 8 }, "Core 2 Duo (Penryn)", "45 nm" },
{ 6, 7, -1, -1, 23, 4, 2048, -1, { "Core(TM)2 Quad Q8###", 8 }, "Core 2 Quad (Yorkfield-6M)", "45 nm" }, /* 2×2 MB L2$ */
{ 6, 7, -1, -1, 23, 4, 3072, -1, { "Core(TM)2 Quad Q9#0#", 8 }, "Core 2 Quad (Yorkfield-6M)", "45 nm" }, /* 2×3 MB L2$ */
{ 6, 7, -1, -1, 23, 4, 6144, -1, { "Core(TM)2 Quad Q9#5#", 8 }, "Core 2 Quad (Yorkfield)", "45 nm" }, /* 2×6 MB L2$ */
/* Core microarchitecture-based Xeons: */
{ 6, 14, -1, -1, 14, 1, -1, -1, { "Xeon(R) 51##", 4 }, "Xeon LV (Woodcrest)" },
{ 6, 15, -1, -1, 15, 2, -1, -1, { "Xeon(R) 51##", 4 }, "Xeon (Woodcrest)" },
{ 6, 15, -1, -1, 15, 2, -1, -1, { "Xeon(R) 30##", 4 }, "Xeon (Conroe)" },
{ 6, 15, -1, -1, 15, 4, -1, -1, { "Xeon(R) X32##", 6 }, "Xeon (Kentsfield)" },
{ 6, 15, -1, -1, 15, 4, -1, -1, { "Xeon(R) [EXL]53##", 6 }, "Xeon (Clovertown)" },
{ 6, 7, -1, -1, 23, 2, -1, -1, { "Xeon(R) [EL]31##", 6 }, "Xeon (Wolfdale)" },
{ 6, 7, -1, -1, 23, 2, -1, -1, { "Xeon(R) [EXL]52##", 6 }, "Xeon (Wolfdale DP)" },
{ 6, 7, -1, -1, 23, 4, -1, -1, { "Xeon(R) [EXL]54##", 6 }, "Xeon (Harpertown)" },
{ 6, 7, -1, -1, 23, 4, -1, -1, { "Xeon(R) [XL]33##", 6 }, "Xeon (Yorkfield)" },
{ 6, 14, -1, -1, 14, 1, -1, -1, { "Xeon(R) 51##", 4 }, "Xeon LV (Woodcrest)", "65 nm" },
{ 6, 15, -1, -1, 15, 2, -1, -1, { "Xeon(R) 51##", 4 }, "Xeon (Woodcrest)", "65 nm" },
{ 6, 15, -1, -1, 15, 2, -1, -1, { "Xeon(R) 30##", 4 }, "Xeon (Conroe)", "65 nm" },
{ 6, 15, -1, -1, 15, 4, -1, -1, { "Xeon(R) X32##", 6 }, "Xeon (Kentsfield)", "65 nm" },
{ 6, 15, -1, -1, 15, 4, -1, -1, { "Xeon(R) [EXL]53##", 6 }, "Xeon (Clovertown)", "65 nm" },
{ 6, 7, -1, -1, 23, 2, -1, -1, { "Xeon(R) [EL]31##", 6 }, "Xeon (Wolfdale)", "45 nm" },
{ 6, 7, -1, -1, 23, 2, -1, -1, { "Xeon(R) [EXL]52##", 6 }, "Xeon (Wolfdale DP)", "45 nm" },
{ 6, 7, -1, -1, 23, 4, -1, -1, { "Xeon(R) [EXL]54##", 6 }, "Xeon (Harpertown)", "45 nm" },
{ 6, 7, -1, -1, 23, 4, -1, -1, { "Xeon(R) [XL]33##", 6 }, "Xeon (Yorkfield)" , "45 nm" },
/* Nehalem CPUs (45nm): */
{ 6, 10, -1, -1, 26, -1, -1, -1, { "Xeon(R) [WELX]5###", 6 }, "Xeon (Gainestown)" },
{ 6, 10, -1, -1, 26, -1, -1, -1, { "Xeon(R) [WELX]3###", 6 }, "Xeon (Bloomfield)" },
{ 6, 10, -1, -1, 26, -1, -1, -1, { "Core(TM) i7 9#5", 8 }, "Core i7 Extreme (Bloomfield)" },
{ 6, 10, -1, -1, 26, -1, -1, -1, { "Core(TM) i7 9#0", 8 }, "Core i7 (Bloomfield)" },
{ 6, 10, -1, -1, 30, -1, -1, -1, { "Core(TM) i7 8##", 8 }, "Core i7 (Lynnfield)" },
{ 6, 5, -1, -1, 30, -1, -1, -1, { "Core(TM) i5 7##", 8 }, "Core i5 (Lynnfield)" },
/* Nehalem CPUs (45 nm): */
{ 6, 10, -1, -1, 26, -1, -1, -1, { "Xeon(R) [WELX]5###", 6 }, "Xeon (Gainestown)", "45 nm" },
{ 6, 10, -1, -1, 26, -1, -1, -1, { "Xeon(R) [WELX]3###", 6 }, "Xeon (Bloomfield)", "45 nm" },
{ 6, 10, -1, -1, 26, -1, -1, -1, { "Core(TM) i7 9#5", 8 }, "Core i7 Extreme (Bloomfield)", "45 nm" },
{ 6, 10, -1, -1, 26, -1, -1, -1, { "Core(TM) i7 9#0", 8 }, "Core i7 (Bloomfield)", "45 nm" },
{ 6, 10, -1, -1, 30, -1, -1, -1, { "Core(TM) i7 8##", 8 }, "Core i7 (Lynnfield)", "45 nm" },
{ 6, 5, -1, -1, 30, -1, -1, -1, { "Core(TM) i5 7##", 8 }, "Core i5 (Lynnfield)", "45 nm" },
/* Westmere CPUs (32nm): */
{ 6, 12, -1, -1, 44, -1, -1, -1, { "Xeon(R) [XEL]5###", 6 }, "Xeon (Westmere-EP)" },
{ 6, 12, -1, -1, 44, -1, -1, -1, { "Xeon(R) W3###", 6 }, "Xeon (Gulftown)" },
{ 6, 12, -1, -1, 44, -1, -1, -1, { "Core(TM) i7 X 9##", 10 }, "Core i7 Extreme (Gulftown)" },
{ 6, 12, -1, -1, 44, -1, -1, -1, { "Core(TM) i7 9##", 8 }, "Core i7 (Gulftown)" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Xeon(R) L3###", 6 }, "Xeon (Clarkdale)" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Core(TM) i5-6##", 8 }, "Core i5 (Clarkdale)" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Core(TM) i3-5##", 8 }, "Core i3 (Clarkdale)" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Pentium(R) G6###", 6 }, "Pentium (Clarkdale)" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Celeron(R) G1###", 6 }, "Celeron (Clarkdale)" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Core(TM) i7 M 6##", 8 }, "Core i7 (Arrandale)" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Core(TM) i5 M [45]##", 8 }, "Core i5 (Arrandale)" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Core(TM) i3 M 3##", 8 }, "Core i3 (Arrandale)" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Pentium(R) P6###", 6 }, "Pentium (Arrandale)" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Pentium(R) 5U###", 6 }, "Pentium (Arrandale)" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Celeron(R) P4###", 6 }, "Celeron (Arrandale)" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Celeron(R) U3###", 6 }, "Celeron (Arrandale)" },
/* Westmere CPUs (32 nm): */
{ 6, 12, -1, -1, 44, -1, -1, -1, { "Xeon(R) [XEL]5###", 6 }, "Xeon (Westmere-EP)", "32 nm" },
{ 6, 12, -1, -1, 44, -1, -1, -1, { "Xeon(R) W3###", 6 }, "Xeon (Gulftown)", "32 nm" },
{ 6, 12, -1, -1, 44, -1, -1, -1, { "Core(TM) i7 X 9##", 10 }, "Core i7 Extreme (Gulftown)", "32 nm" },
{ 6, 12, -1, -1, 44, -1, -1, -1, { "Core(TM) i7 9##", 8 }, "Core i7 (Gulftown)", "32 nm" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Xeon(R) L3###", 6 }, "Xeon (Clarkdale)", "32 nm" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Core(TM) i5-6##", 8 }, "Core i5 (Clarkdale)", "32 nm" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Core(TM) i3-5##", 8 }, "Core i3 (Clarkdale)", "32 nm" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Pentium(R) G6###", 6 }, "Pentium (Clarkdale)", "32 nm" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Celeron(R) G1###", 6 }, "Celeron (Clarkdale)", "32 nm" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Core(TM) i7 M 6##", 8 }, "Core i7 (Arrandale)", "32 nm" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Core(TM) i5 M [45]##", 8 }, "Core i5 (Arrandale)", "32 nm" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Core(TM) i3 M 3##", 8 }, "Core i3 (Arrandale)", "32 nm" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Pentium(R) P6###", 6 }, "Pentium (Arrandale)", "32 nm" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Pentium(R) 5U###", 6 }, "Pentium (Arrandale)", "32 nm" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Celeron(R) P4###", 6 }, "Celeron (Arrandale)", "32 nm" },
{ 6, 5, -1, -1, 37, -1, -1, -1, { "Celeron(R) U3###", 6 }, "Celeron (Arrandale)", "32 nm" },
/* Sandy Bridge CPUs (2nd gen, 32nm): */
{ 6, 10, -1, -1, 42, -1, -1, -1, { "Xeon(R) E5####", 6 }, "Xeon E5 (Sandy Bridge)" },
{ 6, 10, -1, -1, 42, -1, -1, -1, { "Xeon(R) E3####", 6 }, "Xeon E3 (Sandy Bridge)" },
{ 6, 10, -1, -1, 42, -1, -1, -1, { "Core(TM) i7-2###", 8 }, "Core i7 (Sandy Bridge)" },
{ 6, 10, -1, -1, 42, -1, -1, -1, { "Core(TM) i5-2###", 8 }, "Core i5 (Sandy Bridge)" },
{ 6, 10, -1, -1, 42, -1, -1, -1, { "Core(TM) i3-2###", 8 }, "Core i3 (Sandy Bridge)" },
{ 6, 10, -1, -1, 42, -1, -1, -1, { "Pentium(R) G[68]##", 6 }, "Pentium (Sandy Bridge)" },
{ 6, 10, -1, -1, 42, -1, -1, -1, { "Celeron(R) G[45]##", 6 }, "Celeron (Sandy Bridge)" },
{ 6, 13, -1, -1, 45, -1, -1, -1, { "Core(TM) i7-3###[KX]",10 }, "Core i7 Extreme (Sandy Bridge-E)" },
{ 6, 13, -1, -1, 45, -1, -1, -1, { "Xeon(R) E5-####", 4 }, "Xeon E5 (Sandy Bridge-E)" },
{ 6, 13, -1, -1, 45, -1, -1, -1, { "Xeon(R) E3-####", 4 }, "Xeon E3 (Sandy Bridge-E)" },
/* Sandy Bridge CPUs (2nd gen, 32 nm): */
{ 6, 10, -1, -1, 42, -1, -1, -1, { "Xeon(R) E5####", 6 }, "Xeon E5 (Sandy Bridge)", "32 nm" },
{ 6, 10, -1, -1, 42, -1, -1, -1, { "Xeon(R) E3####", 6 }, "Xeon E3 (Sandy Bridge)", "32 nm" },
{ 6, 10, -1, -1, 42, -1, -1, -1, { "Core(TM) i7-2###", 8 }, "Core i7 (Sandy Bridge)", "32 nm" },
{ 6, 10, -1, -1, 42, -1, -1, -1, { "Core(TM) i5-2###", 8 }, "Core i5 (Sandy Bridge)", "32 nm" },
{ 6, 10, -1, -1, 42, -1, -1, -1, { "Core(TM) i3-2###", 8 }, "Core i3 (Sandy Bridge)", "32 nm" },
{ 6, 10, -1, -1, 42, -1, -1, -1, { "Pentium(R) G[68]##", 6 }, "Pentium (Sandy Bridge)", "32 nm" },
{ 6, 10, -1, -1, 42, -1, -1, -1, { "Celeron(R) G[45]##", 6 }, "Celeron (Sandy Bridge)", "32 nm" },
{ 6, 13, -1, -1, 45, -1, -1, -1, { "Core(TM) i7-3###[KX]", 10 }, "Core i7 Extreme (Sandy Bridge-E)", "32 nm" },
{ 6, 13, -1, -1, 45, -1, -1, -1, { "Xeon(R) E5-####", 4 }, "Xeon E5 (Sandy Bridge-E)", "32 nm" },
{ 6, 13, -1, -1, 45, -1, -1, -1, { "Xeon(R) E3-####", 4 }, "Xeon E3 (Sandy Bridge-E)", "32 nm" },
/* Ivy Bridge CPUs (3rd gen, 22nm): */
{ 6, 10, -1, -1, 58, -1, -1, -1, { "Xeon(R) E7-#### v2", 6 }, "Xeon E7 (Ivy Bridge)" },
{ 6, 10, -1, -1, 58, -1, -1, -1, { "Xeon(R) E5-#### v2", 6 }, "Xeon E5 (Ivy Bridge)" },
{ 6, 10, -1, -1, 58, -1, -1, -1, { "Xeon(R) E3-#### v2", 6 }, "Xeon E3 (Ivy Bridge)" },
{ 6, 10, -1, -1, 58, -1, -1, -1, { "Core(TM) i7-3###", 8 }, "Core i7 (Ivy Bridge)" },
{ 6, 10, -1, -1, 58, -1, -1, -1, { "Core(TM) i5-3###", 8 }, "Core i5 (Ivy Bridge)" },
{ 6, 10, -1, -1, 58, -1, -1, -1, { "Core(TM) i3-3###", 8 }, "Core i3 (Ivy Bridge)" },
{ 6, 10, -1, -1, 58, -1, -1, -1, { "Pentium(R) G2###", 6 }, "Pentium (Ivy Bridge)" },
{ 6, 10, -1, -1, 58, -1, -1, -1, { "Celeron(R) G1###", 6 }, "Celeron (Ivy Bridge)" },
{ 6, 14, -1, -1, 62, -1, -1, -1, { "Xeon(R) E7-#### v2", 6 }, "Xeon E7 (Ivy Bridge-E)" },
{ 6, 14, -1, -1, 62, -1, -1, -1, { "Xeon(R) E5-#### v2", 6 }, "Xeon E5 (Ivy Bridge-E)" },
{ 6, 14, -1, -1, 62, -1, -1, -1, { "Xeon(R) E3-#### v2", 6 }, "Xeon E3 (Ivy Bridge-E)" },
{ 6, 14, -1, -1, 62, -1, -1, -1, { "Core(TM) i7-4###X", 10 }, "Core i7 Extreme (Ivy Bridge-E)" },
{ 6, 14, -1, -1, 62, -1, -1, -1, { "Core(TM) i7-4###K", 8 }, "Core i7 (Ivy Bridge-E)" },
/* Ivy Bridge CPUs (3rd gen, 22 nm): */
{ 6, 10, -1, -1, 58, -1, -1, -1, { "Xeon(R) E7-#### v2", 6 }, "Xeon E7 (Ivy Bridge)", "22 nm" },
{ 6, 10, -1, -1, 58, -1, -1, -1, { "Xeon(R) E5-#### v2", 6 }, "Xeon E5 (Ivy Bridge)", "22 nm" },
{ 6, 10, -1, -1, 58, -1, -1, -1, { "Xeon(R) E3-#### v2", 6 }, "Xeon E3 (Ivy Bridge)", "22 nm" },
{ 6, 10, -1, -1, 58, -1, -1, -1, { "Core(TM) i7-3###", 8 }, "Core i7 (Ivy Bridge)", "22 nm" },
{ 6, 10, -1, -1, 58, -1, -1, -1, { "Core(TM) i5-3###", 8 }, "Core i5 (Ivy Bridge)", "22 nm" },
{ 6, 10, -1, -1, 58, -1, -1, -1, { "Core(TM) i3-3###", 8 }, "Core i3 (Ivy Bridge)", "22 nm" },
{ 6, 10, -1, -1, 58, -1, -1, -1, { "Pentium(R) G2###", 6 }, "Pentium (Ivy Bridge)", "22 nm" },
{ 6, 10, -1, -1, 58, -1, -1, -1, { "Celeron(R) G1###", 6 }, "Celeron (Ivy Bridge)", "22 nm" },
{ 6, 14, -1, -1, 62, -1, -1, -1, { "Xeon(R) E7-#### v2", 6 }, "Xeon E7 (Ivy Bridge-E)", "22 nm" },
{ 6, 14, -1, -1, 62, -1, -1, -1, { "Xeon(R) E5-#### v2", 6 }, "Xeon E5 (Ivy Bridge-E)", "22 nm" },
{ 6, 14, -1, -1, 62, -1, -1, -1, { "Xeon(R) E3-#### v2", 6 }, "Xeon E3 (Ivy Bridge-E)", "22 nm" },
{ 6, 14, -1, -1, 62, -1, -1, -1, { "Core(TM) i7-4###X", 10 }, "Core i7 Extreme (Ivy Bridge-E)", "22 nm" },
{ 6, 14, -1, -1, 62, -1, -1, -1, { "Core(TM) i7-4###K", 8 }, "Core i7 (Ivy Bridge-E)", "22 nm" },
/* Haswell CPUs (4th gen, 22nm): */
{ 6, 12, -1, -1, 60, -1, -1, -1, { "Xeon(R) E7-#### v3", 6 }, "Xeon E7 (Haswell)" },
{ 6, 12, -1, -1, 60, -1, -1, -1, { "Xeon(R) E5-#### v3", 6 }, "Xeon E5 (Haswell)" },
{ 6, 12, -1, -1, 60, -1, -1, -1, { "Xeon(R) E3-#### v3", 6 }, "Xeon E3 (Haswell)" },
{ 6, 12, -1, -1, 60, -1, -1, -1, { "Core(TM) i7-4###", 8 }, "Core i7 (Haswell)" },
{ 6, 12, -1, -1, 60, -1, -1, -1, { "Core(TM) i5-4###", 8 }, "Core i5 (Haswell)" },
{ 6, 12, -1, -1, 60, -1, -1, -1, { "Core(TM) i3-4###", 8 }, "Core i3 (Haswell)" },
{ 6, 12, -1, -1, 60, -1, -1, -1, { "Pentium(R) G3###", 6 }, "Pentium (Haswell)" },
{ 6, 12, -1, -1, 60, -1, -1, -1, { "Celeron(R) G1###", 6 }, "Celeron (Haswell)" },
{ 6, 15, -1, -1, 63, -1, -1, -1, { "Core(TM) i7-5###[KX]", 8 }, "Core i7 Extreme (Haswell)" },
{ 6, 5, -1, -1, 69, -1, -1, -1, { "Core(TM) i7-4###", 8 }, "Core i7 (Haswell)" },
{ 6, 5, -1, -1, 69, -1, -1, -1, { "Core(TM) i5-4###", 8 }, "Core i5 (Haswell)" },
{ 6, 5, -1, -1, 69, -1, -1, -1, { "Core(TM) i3-4###", 8 }, "Core i3 (Haswell)" },
{ 6, 6, -1, -1, 70, -1, -1, -1, { "Core(TM) i7-4###R", 10 }, "Core i7 (Haswell)" }, // GT3e
{ 6, 6, -1, -1, 70, -1, -1, -1, { "Core(TM) i7-4###R", 10 }, "Core i5 (Haswell)" }, // GT3e
/* Haswell CPUs (4th gen, 22 nm): */
{ 6, 12, -1, -1, 60, -1, -1, -1, { "Xeon(R) E7-#### v3", 6 }, "Xeon E7 (Haswell)", "22 nm" },
{ 6, 12, -1, -1, 60, -1, -1, -1, { "Xeon(R) E5-#### v3", 6 }, "Xeon E5 (Haswell)", "22 nm" },
{ 6, 12, -1, -1, 60, -1, -1, -1, { "Xeon(R) E3-#### v3", 6 }, "Xeon E3 (Haswell)", "22 nm" },
{ 6, 12, -1, -1, 60, -1, -1, -1, { "Core(TM) i7-4###", 8 }, "Core i7 (Haswell)", "22 nm" },
{ 6, 12, -1, -1, 60, -1, -1, -1, { "Core(TM) i5-4###", 8 }, "Core i5 (Haswell)", "22 nm" },
{ 6, 12, -1, -1, 60, -1, -1, -1, { "Core(TM) i3-4###", 8 }, "Core i3 (Haswell)", "22 nm" },
{ 6, 12, -1, -1, 60, -1, -1, -1, { "Pentium(R) G3###", 6 }, "Pentium (Haswell)", "22 nm" },
{ 6, 12, -1, -1, 60, -1, -1, -1, { "Celeron(R) G1###", 6 }, "Celeron (Haswell)", "22 nm" },
{ 6, 15, -1, -1, 63, -1, -1, -1, { "Core(TM) i7-5###[KX]", 8 }, "Core i7 Extreme (Haswell)", "22 nm" },
{ 6, 5, -1, -1, 69, -1, -1, -1, { "Core(TM) i7-4###", 8 }, "Core i7 (Haswell)", "22 nm" },
{ 6, 5, -1, -1, 69, -1, -1, -1, { "Core(TM) i5-4###", 8 }, "Core i5 (Haswell)", "22 nm" },
{ 6, 5, -1, -1, 69, -1, -1, -1, { "Core(TM) i3-4###", 8 }, "Core i3 (Haswell)", "22 nm" },
{ 6, 6, -1, -1, 70, -1, -1, -1, { "Core(TM) i7-4###R", 10 }, "Core i7 (Haswell)", "22 nm" }, /* GT3e */
{ 6, 6, -1, -1, 70, -1, -1, -1, { "Core(TM) i7-4###R", 10 }, "Core i5 (Haswell)", "22 nm" }, /* GT3e */
/* Silvermont CPUs (2013, 22nm, low-power) */
{ 6, 7, -1, -1, 55, -1, -1, -1, { "Pentium(R) J2###", 6 }, "Pentium (Bay Trail-D)" },
{ 6, 7, -1, -1, 55, -1, -1, -1, { "Celeron(R) J1###", 6 }, "Celeron (Bay Trail-D)" },
{ 6, 7, -1, -1, 55, -1, -1, -1, { "Pentium(R) N3###", 6 }, "Pentium (Bay Trail-M)" },
{ 6, 7, -1, -1, 55, -1, -1, -1, { "Celeron(R) N2###", 6 }, "Celeron (Bay Trail-M)" },
{ 6, 7, -1, -1, 55, -1, -1, -1, { "Atom(TM) Z3###", 6 }, "Atom (Bay Trail-T)" },
{ 6, 7, -1, -1, 55, -1, -1, -1, { "Atom(TM) E3###", 6 }, "Atom (Bay Trail-I)" },
/* Silvermont CPUs (2013, 22 nm, low-power) */
{ 6, 7, -1, -1, 55, -1, -1, -1, { "Pentium(R) J2###", 6 }, "Pentium (Bay Trail-D)", "22 nm" },
{ 6, 7, -1, -1, 55, -1, -1, -1, { "Celeron(R) J1###", 6 }, "Celeron (Bay Trail-D)", "22 nm" },
{ 6, 7, -1, -1, 55, -1, -1, -1, { "Pentium(R) N3###", 6 }, "Pentium (Bay Trail-M)", "22 nm" },
{ 6, 7, -1, -1, 55, -1, -1, -1, { "Celeron(R) N2###", 6 }, "Celeron (Bay Trail-M)", "22 nm" },
{ 6, 7, -1, -1, 55, -1, -1, -1, { "Atom(TM) Z3###", 6 }, "Atom (Bay Trail-T)" , "22 nm" },
{ 6, 7, -1, -1, 55, -1, -1, -1, { "Atom(TM) E3###", 6 }, "Atom (Bay Trail-I)" , "22 nm" },
/* Broadwell CPUs (5th gen, 14nm): */
{ 6, 7, -1, -1, 71, 4, -1, -1, { "Core(TM) i7-5###C", 10 }, "Core i7 (Broadwell)" },
{ 6, 7, -1, -1, 71, 4, -1, -1, { "Core(TM) i5-5###C", 10 }, "Core i5 (Broadwell)" },
{ 6, 13, -1, -1, 61, 4, -1, -1, { "Core(TM) i7-5###HQ", 12 }, "Core i7 (Broadwell-U)" },
{ 6, 13, -1, -1, 61, 2, -1, -1, { "Core(TM) i7-5###U", 10 }, "Core i7 (Broadwell-U)" },
{ 6, 13, -1, -1, 61, 2, -1, -1, { "Core(TM) i5-5###[HU]", 10 }, "Core i5 (Broadwell-U)" },
{ 6, 13, -1, -1, 61, 2, -1, -1, { "Core(TM) i3-5###U", 10 }, "Core i3 (Broadwell-U)" },
{ 6, 13, -1, -1, 61, 2, -1, -1, { "Core(TM) M-5Y##", 8 }, "Core M (Broadwell-U)" },
{ 6, 13, -1, -1, 61, 2, -1, -1, { "Pentium(R) 3###U", 6 }, "Pentium (Broadwell-U)" },
{ 6, 13, -1, -1, 61, 2, -1, -1, { "Celeron(R) 3###U", 6 }, "Celeron (Broadwell-U)" },
{ 6, 15, -1, -1, 79, 4, -1, -1, { "Core(TM) i7-6###[KX]", 10 }, "Core i7 (Broadwell-E)" },
/* Broadwell CPUs (5th gen, 14 nm): */
{ 6, 7, -1, -1, 71, 4, -1, -1, { "Core(TM) i7-5###C", 10 }, "Core i7 (Broadwell)", "14 nm" },
{ 6, 7, -1, -1, 71, 4, -1, -1, { "Core(TM) i5-5###C", 10 }, "Core i5 (Broadwell)", "14 nm" },
{ 6, 13, -1, -1, 61, 4, -1, -1, { "Core(TM) i7-5###HQ", 12 }, "Core i7 (Broadwell-U)", "14 nm" },
{ 6, 13, -1, -1, 61, 2, -1, -1, { "Core(TM) i7-5###U", 10 }, "Core i7 (Broadwell-U)", "14 nm" },
{ 6, 13, -1, -1, 61, 2, -1, -1, { "Core(TM) i5-5###[HU]", 10 }, "Core i5 (Broadwell-U)", "14 nm" },
{ 6, 13, -1, -1, 61, 2, -1, -1, { "Core(TM) i3-5###U", 10 }, "Core i3 (Broadwell-U)", "14 nm" },
{ 6, 13, -1, -1, 61, 2, -1, -1, { "Core(TM) M-5Y##", 8 }, "Core M (Broadwell-U)", "14 nm" },
{ 6, 13, -1, -1, 61, 2, -1, -1, { "Pentium(R) 3###U", 6 }, "Pentium (Broadwell-U)", "14 nm" },
{ 6, 13, -1, -1, 61, 2, -1, -1, { "Celeron(R) 3###U", 6 }, "Celeron (Broadwell-U)", "14 nm" },
{ 6, 15, -1, -1, 79, 4, -1, -1, { "Core(TM) i7-6###[KX]", 10 }, "Core i7 (Broadwell-E)", "14 nm" },
/* Skylake (client) CPUs (2015, 6th Core i gen, 14nm) => https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client) */
{ 6, 14, -1, -1, 94, 4, -1, -1, { "Core(TM) i7-6###", 8 }, "Core i7 (Skylake)" },
{ 6, 14, -1, -1, 94, 4, -1, -1, { "Core(TM) i5-6###", 8 }, "Core i5 (Skylake)" },
{ 6, 14, -1, -1, 94, 2, -1, -1, { "Core(TM) i3-6###", 8 }, "Core i3 (Skylake)" },
{ 6, 14, -1, -1, 94, 2, -1, -1, { "Pentium(R) G4###", 4 }, "Pentium (Skylake)" },
{ 6, 14, -1, -1, 94, 2, -1, -1, { "Celeron(R) G3###", 4 }, "Celeron (Skylake)" },
{ 6, 14, -1, -1, 78, 2, -1, -1, { "Core(TM) m7-6Y##", 8 }, "Core m7 (Skylake)" },
{ 6, 14, -1, -1, 78, 2, -1, -1, { "Core(TM) m5-6Y##", 8 }, "Core m5 (Skylake)" },
{ 6, 14, -1, -1, 78, 2, -1, -1, { "Core(TM) m3-6Y##", 8 }, "Core m3 (Skylake)" },
{ 6, 14, -1, -1, 78, 2, -1, -1, { "Pentium(R) 4###[UY]", 4 }, "Pentium (Skylake)" },
{ 6, 14, -1, -1, 78, 2, -1, -1, { "Celeron(R) 3###U", 4 }, "Celeron (Skylake)" },
{ 6, 14, -1, -1, 78, 2, -1, -1, { "Celeron(R) G3###E", 6 }, "Celeron (Skylake)" },
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Core(TM) i9-7###X", 10 }, "Core i9 (Skylake-X)" }, /* 10 to 18 cores */
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Core(TM) i7-7###X", 10 }, "Core i7 (Skylake-X)" }, /* 6 to 8 cores */
{ 6, 14, -1, -1, 94, -1, -1, -1, { "Xeon(R) W-#1##X", 8 }, "Xeon (Skylake-X)" },
/* Skylake (server) CPUs (2017, 1st Xeon Scalable gen, 14nm) => https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(server) */
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) W-#1##", 6 }, "Xeon W (Skylake-W)" },
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) D-#1##", 6 }, "Xeon D (Skylake-DE)" },
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Platinum #1##", 6 }, "Xeon Platinum (Skylake-SP)" },
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Gold #1##", 6 }, "Xeon Gold (Skylake-SP)" },
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Silver #1##", 6 }, "Xeon Silver (Skylake-SP)" },
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Bronze #1##", 6 }, "Xeon Bronze (Skylake-SP)" },
/* Skylake (client) CPUs (2015, 6th Core i gen, 14 nm) => https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client) */
{ 6, 14, -1, -1, 94, 4, -1, -1, { "Core(TM) i7-6###", 8 }, "Core i7 (Skylake)", "14 nm" },
{ 6, 14, -1, -1, 94, 4, -1, -1, { "Core(TM) i5-6###", 8 }, "Core i5 (Skylake)", "14 nm" },
{ 6, 14, -1, -1, 94, 2, -1, -1, { "Core(TM) i3-6###", 8 }, "Core i3 (Skylake)", "14 nm" },
{ 6, 14, -1, -1, 94, 2, -1, -1, { "Pentium(R) G4###", 4 }, "Pentium (Skylake)", "14 nm" },
{ 6, 14, -1, -1, 94, 2, -1, -1, { "Celeron(R) G3###", 4 }, "Celeron (Skylake)", "14 nm" },
{ 6, 14, -1, -1, 78, 2, -1, -1, { "Core(TM) m7-6Y##", 8 }, "Core m7 (Skylake)", "14 nm" },
{ 6, 14, -1, -1, 78, 2, -1, -1, { "Core(TM) m5-6Y##", 8 }, "Core m5 (Skylake)", "14 nm" },
{ 6, 14, -1, -1, 78, 2, -1, -1, { "Core(TM) m3-6Y##", 8 }, "Core m3 (Skylake)", "14 nm" },
{ 6, 14, -1, -1, 78, 2, -1, -1, { "Pentium(R) 4###[UY]", 4 }, "Pentium (Skylake)", "14 nm" },
{ 6, 14, -1, -1, 78, 2, -1, -1, { "Celeron(R) 3###U", 4 }, "Celeron (Skylake)", "14 nm" },
{ 6, 14, -1, -1, 78, 2, -1, -1, { "Celeron(R) G3###E", 6 }, "Celeron (Skylake)", "14 nm" },
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Core(TM) i9-7###X", 10 }, "Core i9 (Skylake-X)", "14 nm" }, /* 10 to 18 cores */
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Core(TM) i7-7###X", 10 }, "Core i7 (Skylake-X)", "14 nm" }, /* 6 to 8 cores */
{ 6, 14, -1, -1, 94, -1, -1, -1, { "Xeon(R) W-#1##X", 8 }, "Xeon (Skylake-X)", "14 nm" },
/* Skylake (server) CPUs (2017, 1st Xeon Scalable gen, 14 nm) => https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(server) */
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) W-#1##", 6 }, "Xeon W (Skylake-W)", "14 nm" },
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) D-#1##", 6 }, "Xeon D (Skylake-DE)", "14 nm" },
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Platinum #1##", 6 }, "Xeon Platinum (Skylake-SP)", "14 nm" },
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Gold #1##", 6 }, "Xeon Gold (Skylake-SP)", "14 nm" },
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Silver #1##", 6 }, "Xeon Silver (Skylake-SP)", "14 nm" },
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Bronze #1##", 6 }, "Xeon Bronze (Skylake-SP)", "14 nm" },
/* Kaby Lake CPUs (7th gen, 14nm): */
{ 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i7-7###", 8 }, "Core i7 (Kaby Lake)" },
{ 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i5-7###", 8 }, "Core i5 (Kaby Lake)" },
{ 6, 14, -1, -1, 158, 2, -1, -1, { "Core(TM) i3-7###", 8 }, "Core i3 (Kaby Lake)" },
{ 6, 14, -1, -1, 158, 2, -1, -1, { "Pentium(R) G4###", 4 }, "Pentium (Kaby Lake)" },
{ 6, 14, -1, -1, 158, 2, -1, -1, { "Celeron(R) G3###", 4 }, "Celeron (Kaby Lake)" },
{ 6, 14, 9, -1, 142, 2, -1, -1, { "Core(TM) i7-7.##", 8 }, "Core i7 (Kaby Lake-U)" },
{ 6, 14, 9, -1, 142, 2, -1, -1, { "Core(TM) i5-7.##", 8 }, "Core i5 (Kaby Lake-U)" },
{ 6, 14, 9, -1, 142, 2, -1, -1, { "Core(TM) i3-7.##", 8 }, "Core i3 (Kaby Lake-U)" },
{ 6, 14, 9, -1, 142, 2, -1, -1, { "Core(TM) m3-7.##", 8 }, "Core m3 (Kaby Lake-U)" },
{ 6, 14, 9, -1, 142, 2, -1, -1, { "Pentium(R) Gold 4###[UY]", 8 }, "Pentium Gold (Kaby Lake-U)" },
{ 6, 14, 9, -1, 142, 2, -1, -1, { "Celeron(R) 3###[UY]", 6 }, "Celeron (Kaby Lake-U)" },
{ 6, 14, 9, -1, 158, 4, -1, -1, { "Core(TM) i7-8###G", 10 }, "Core i7 (Kaby Lake-G)" },
{ 6, 14, 9, -1, 158, 4, -1, -1, { "Core(TM) i5-8###G", 10 }, "Core i5 (Kaby Lake-G)" },
{ 6, 14, 10, -1, 142, 4, -1, -1, { "Core(TM) i7-8###U", 10 }, "Core i7 (Kaby Lake-R)" }, /* i7-8550U + i7-8650U */
{ 6, 14, 10, -1, 142, 4, -1, -1, { "Core(TM) i5-8###U", 10 }, "Core i5 (Kaby Lake-R)" }, /* i5-8250U + i5-8350U */
{ 6, 14, 10, -1, 142, 2, -1, -1, { "Pentium(R) Gold 4###U", 8 }, "Pentium Gold (Kaby Lake-U)" },
{ 6, 14, 10, -1, 142, 2, -1, -1, { "Celeron(R) 3###U", 6 }, "Celeron (Kaby Lake-U)" },
/* Kaby Lake CPUs (7th gen, 14+ nm): */
{ 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i7-7###", 8 }, "Core i7 (Kaby Lake)", "14+ nm" },
{ 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i5-7###", 8 }, "Core i5 (Kaby Lake)", "14+ nm" },
{ 6, 14, -1, -1, 158, 2, -1, -1, { "Core(TM) i3-7###", 8 }, "Core i3 (Kaby Lake)", "14+ nm" },
{ 6, 14, -1, -1, 158, 2, -1, -1, { "Pentium(R) G4###", 4 }, "Pentium (Kaby Lake)", "14+ nm" },
{ 6, 14, -1, -1, 158, 2, -1, -1, { "Celeron(R) G3###", 4 }, "Celeron (Kaby Lake)", "14+ nm" },
{ 6, 14, 9, -1, 142, 2, -1, -1, { "Core(TM) i7-7.##", 8 }, "Core i7 (Kaby Lake-U)", "14+ nm" },
{ 6, 14, 9, -1, 142, 2, -1, -1, { "Core(TM) i5-7.##", 8 }, "Core i5 (Kaby Lake-U)", "14+ nm" },
{ 6, 14, 9, -1, 142, 2, -1, -1, { "Core(TM) i3-7.##", 8 }, "Core i3 (Kaby Lake-U)", "14+ nm" },
{ 6, 14, 9, -1, 142, 2, -1, -1, { "Core(TM) m3-7.##", 8 }, "Core m3 (Kaby Lake-U)", "14+ nm" },
{ 6, 14, 9, -1, 142, 2, -1, -1, { "Pentium(R) Gold 4###[UY]", 8 }, "Pentium Gold (Kaby Lake-U)", "14+ nm" },
{ 6, 14, 9, -1, 142, 2, -1, -1, { "Celeron(R) 3###[UY]", 6 }, "Celeron (Kaby Lake-U)", "14+ nm" },
{ 6, 14, 9, -1, 158, 4, -1, -1, { "Core(TM) i7-8###G", 10 }, "Core i7 (Kaby Lake-G)", "14+ nm" },
{ 6, 14, 9, -1, 158, 4, -1, -1, { "Core(TM) i5-8###G", 10 }, "Core i5 (Kaby Lake-G)", "14+ nm" },
{ 6, 14, 10, -1, 142, 4, -1, -1, { "Core(TM) i7-8###U", 10 }, "Core i7 (Kaby Lake-R)", "14+ nm" }, /* i7-8550U + i7-8650U */
{ 6, 14, 10, -1, 142, 4, -1, -1, { "Core(TM) i5-8###U", 10 }, "Core i5 (Kaby Lake-R)", "14+ nm" }, /* i5-8250U + i5-8350U */
{ 6, 14, 10, -1, 142, 2, -1, -1, { "Pentium(R) Gold 4###U", 8 }, "Pentium Gold (Kaby Lake-U)", "14+ nm" },
{ 6, 14, 10, -1, 142, 2, -1, -1, { "Celeron(R) 3###U", 6 }, "Celeron (Kaby Lake-U)", "14+ nm" },
/* Coffee Lake CPUs (8th gen, 14nm): */
{ 6, 14, -1, -1, 158, 6, -1, -1, { "Core(TM) i7-8###", 8 }, "Core i7 (Coffee Lake-S)" },
{ 6, 14, -1, -1, 158, 6, -1, -1, { "Core(TM) i5-8###", 8 }, "Core i5 (Coffee Lake-S)" },
{ 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i3-8###", 8 }, "Core i3 (Coffee Lake-S)" },
{ 6, 14, -1, -1, 158, 2, -1, -1, { "Pentium(R) Gold G5###", 6 }, "Pentium Gold (Coffee Lake-S)" },
{ 6, 14, -1, -1, 158, 2, -1, -1, { "Celeron(R) G4###", 4 }, "Celeron (Coffee Lake-S)" },
{ 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i9-8###[HB]", 10 }, "Core i9 (Coffee Lake-H)" },
{ 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i7-8###[HB]", 10 }, "Core i7 (Coffee Lake-H)" },
{ 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i5-8###[HB]", 10 }, "Core i5 (Coffee Lake-H)" },
{ 6, 14, -1, -1, 142, 2, -1, -1, { "Core(TM) i3-8###[HB]", 10 }, "Core i3 (Coffee Lake-H)" },
{ 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i7-8###U", 10 }, "Core i7 (Coffee Lake-U)" },
{ 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i5-8###U", 10 }, "Core i5 (Coffee Lake-U)" },
{ 6, 14, -1, -1, 142, 2, -1, -1, { "Core(TM) i3-8###U", 10 }, "Core i3 (Coffee Lake-U)" },
{ 6, 6, -1, -1, 102, 2, -1, -1, { "Core(TM) i3-8###U", 10 }, "Core i3 (Cannon Lake-U)" }, /* Core i3 8121U */
{ 6, 6, -1, -1, 102, 2, -1, -1, { "Core(TM) m3-8###Y", 10 }, "Core m3 (Cannon Lake-Y)" }, /* Core m3 8114Y */
{ 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i7-8###U", 12 }, "Core i7 (Whiskey Lake-U)" },
{ 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i5-8###U", 12 }, "Core i5 (Whiskey Lake-U)" },
{ 6, 14, -1, -1, 142, 2, -1, -1, { "Core(TM) i3-8###U", 12 }, "Core i3 (Whiskey Lake-U)" },
{ 6, 14, -1, -1, 142, 2, -1, -1, { "Pentium(R) Gold 5###U", 8 }, "Pentium Gold (Whiskey Lake-U)" },
{ 6, 14, -1, -1, 142, 2, -1, -1, { "Celeron(R) 4###U", 6 }, "Celeron (Whiskey Lake-U)" },
/* Coffee Lake CPUs (8th gen, 14++ nm): */
{ 6, 14, -1, -1, 158, 6, -1, -1, { "Core(TM) i7-8###", 8 }, "Core i7 (Coffee Lake-S)", "14++ nm" },
{ 6, 14, -1, -1, 158, 6, -1, -1, { "Core(TM) i5-8###", 8 }, "Core i5 (Coffee Lake-S)", "14++ nm" },
{ 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i3-8###", 8 }, "Core i3 (Coffee Lake-S)", "14++ nm" },
{ 6, 14, -1, -1, 158, 2, -1, -1, { "Pentium(R) Gold G5###", 6 }, "Pentium Gold (Coffee Lake-S)", "14++ nm" },
{ 6, 14, -1, -1, 158, 2, -1, -1, { "Celeron(R) G4###", 4 }, "Celeron (Coffee Lake-S)", "14++ nm" },
{ 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i9-8###[HB]", 10 }, "Core i9 (Coffee Lake-H)", "14++ nm" },
{ 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i7-8###[HB]", 10 }, "Core i7 (Coffee Lake-H)", "14++ nm" },
{ 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i5-8###[HB]", 10 }, "Core i5 (Coffee Lake-H)", "14++ nm" },
{ 6, 14, -1, -1, 142, 2, -1, -1, { "Core(TM) i3-8###[HB]", 10 }, "Core i3 (Coffee Lake-H)", "14++ nm" },
{ 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i7-8###U", 10 }, "Core i7 (Coffee Lake-U)", "14++ nm" },
{ 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i5-8###U", 10 }, "Core i5 (Coffee Lake-U)", "14++ nm" },
{ 6, 14, -1, -1, 142, 2, -1, -1, { "Core(TM) i3-8###U", 10 }, "Core i3 (Coffee Lake-U)", "14++ nm" },
{ 6, 6, -1, -1, 102, 2, -1, -1, { "Core(TM) i3-8###U", 10 }, "Core i3 (Cannon Lake-U)", "14++ nm" }, /* Core i3 8121U */
{ 6, 6, -1, -1, 102, 2, -1, -1, { "Core(TM) m3-8###Y", 10 }, "Core m3 (Cannon Lake-Y)", "14++ nm" }, /* Core m3 8114Y */
{ 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i7-8###U", 12 }, "Core i7 (Whiskey Lake-U)", "14++ nm" },
{ 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i5-8###U", 12 }, "Core i5 (Whiskey Lake-U)", "14++ nm" },
{ 6, 14, -1, -1, 142, 2, -1, -1, { "Core(TM) i3-8###U", 12 }, "Core i3 (Whiskey Lake-U)", "14++ nm" },
{ 6, 14, -1, -1, 142, 2, -1, -1, { "Pentium(R) Gold 5###U", 8 }, "Pentium Gold (Whiskey Lake-U)", "14++ nm" },
{ 6, 14, -1, -1, 142, 2, -1, -1, { "Celeron(R) 4###U", 6 }, "Celeron (Whiskey Lake-U)", "14++ nm" },
/* Coffee Lake Refresh CPUs (9th gen, 14nm): */
{ 6, 14, -1, -1, 158, 8, -1, -1, { "Core(TM) i9-9###", 8 }, "Core i9 (Coffee Lake-S)" },
{ 6, 14, -1, -1, 158, 8, -1, -1, { "Core(TM) i7-9###", 8 }, "Core i7 (Coffee Lake-S)" },
{ 6, 14, -1, -1, 158, 6, -1, -1, { "Core(TM) i5-9###", 8 }, "Core i5 (Coffee Lake-S)" },
{ 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i3-9###", 8 }, "Core i3 (Coffee Lake-S)" },
{ 6, 14, -1, -1, 158, 2, -1, -1, { "Pentium(R) Gold G5###", 6 }, "Pentium Gold (Coffee Lake-S)" },
{ 6, 14, -1, -1, 158, 2, -1, -1, { "Celeron(R) G4###", 4 }, "Celeron (Coffee Lake-S)" },
/* Coffee Lake Refresh CPUs (9th gen, 14++ nm): */
{ 6, 14, -1, -1, 158, 8, -1, -1, { "Core(TM) i9-9###", 8 }, "Core i9 (Coffee Lake-S)", "14++ nm" },
{ 6, 14, -1, -1, 158, 8, -1, -1, { "Core(TM) i7-9###", 8 }, "Core i7 (Coffee Lake-S)", "14++ nm" },
{ 6, 14, -1, -1, 158, 6, -1, -1, { "Core(TM) i5-9###", 8 }, "Core i5 (Coffee Lake-S)", "14++ nm" },
{ 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i3-9###", 8 }, "Core i3 (Coffee Lake-S)", "14++ nm" },
{ 6, 14, -1, -1, 158, 2, -1, -1, { "Pentium(R) Gold G5###", 6 }, "Pentium Gold (Coffee Lake-S)", "14++ nm" },
{ 6, 14, -1, -1, 158, 2, -1, -1, { "Celeron(R) G4###", 4 }, "Celeron (Coffee Lake-S)", "14++ nm" },
/* Cascade Lake CPUs (2019, 2nd Xeon Scalable gen, 14nm) => https://en.wikichip.org/wiki/intel/microarchitectures/cascade_lake */
{ 6, 5, 7, -1, 85, -1, -1, -1, { "Core(TM) i9-10###X", 10 }, "Core i9 (Cascade Lake-X)" },
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) W-#[23]##", 6 }, "Xeon W (Cascade Lake-W)" },
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Platinum #2##", 6 }, "Xeon Platinum (Cascade Lake-SP)" },
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Gold #2##", 6 }, "Xeon Gold (Cascade Lake-SP)" },
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Silver #2##", 6 }, "Xeon Silver (Cascade Lake-SP)" },
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Bronze #2##", 6 }, "Xeon Bronze (Cascade Lake-SP)" },
/* Cascade Lake CPUs (2019, 2nd Xeon Scalable gen, 14++ nm) => https://en.wikichip.org/wiki/intel/microarchitectures/cascade_lake */
{ 6, 5, 7, -1, 85, -1, -1, -1, { "Core(TM) i9-10###X", 10 }, "Core i9 (Cascade Lake-X)", "14++ nm" },
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) W-#[23]##", 6 }, "Xeon W (Cascade Lake-W)", "14++ nm" },
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Platinum #2##", 6 }, "Xeon Platinum (Cascade Lake-SP)", "14++ nm" },
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Gold #2##", 6 }, "Xeon Gold (Cascade Lake-SP)", "14++ nm" },
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Silver #2##", 6 }, "Xeon Silver (Cascade Lake-SP)", "14++ nm" },
{ 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Bronze #2##", 6 }, "Xeon Bronze (Cascade Lake-SP)", "14++ nm" },
/* Comet Lake CPUs (10th gen, 14nm): */
{ 6, 5, -1, -1, 165, 10, -1, -1, { "Core(TM) i9-10###", 8 }, "Core i9 (Comet Lake-S)" },
{ 6, 5, -1, -1, 165, 8, -1, -1, { "Core(TM) i7-10###", 8 }, "Core i7 (Comet Lake-S)" },
{ 6, 5, -1, -1, 165, 6, -1, -1, { "Core(TM) i5-10###", 8 }, "Core i5 (Comet Lake-S)" },
{ 6, 5, -1, -1, 165, 4, -1, -1, { "Core(TM) i3-10###", 8 }, "Core i3 (Comet Lake-S)" },
{ 6, 5, -1, -1, 165, 2, -1, -1, { "Pentium(R) Gold G6###", 6 }, "Pentium Gold (Comet Lake-S)" },
{ 6, 5, -1, -1, 165, 2, -1, -1, { "Celeron(R) G5###", 4 }, "Celeron (Comet Lake-S)" },
{ 6, 14, 12, -1, 142, 6, -1, -1, { "Core(TM) i7-10###U", 10 }, "Core i7 (Comet Lake-U)" },
{ 6, 14, 12, -1, 142, 4, -1, -1, { "Core(TM) i7-10###U", 10 }, "Core i7 (Comet Lake-U)" },
{ 6, 14, 12, -1, 142, 4, -1, -1, { "Core(TM) i5-10###U", 10 }, "Core i5 (Comet Lake-U)" },
{ 6, 14, 12, -1, 142, 2, -1, -1, { "Pentium(R) Gold 6###U", 6 }, "Pentium Gold (Comet Lake-U)" },
{ 6, 14, 12, -1, 142, 2, -1, -1, { "Celeron(R) 5###U", 4 }, "Celeron (Comet Lake-U)" },
/* Comet Lake CPUs (10th gen, 14++ nm): */
{ 6, 5, -1, -1, 165, 10, -1, -1, { "Core(TM) i9-10###", 8 }, "Core i9 (Comet Lake-S)", "14++ nm" },
{ 6, 5, -1, -1, 165, 8, -1, -1, { "Core(TM) i7-10###", 8 }, "Core i7 (Comet Lake-S)", "14++ nm" },
{ 6, 5, -1, -1, 165, 6, -1, -1, { "Core(TM) i5-10###", 8 }, "Core i5 (Comet Lake-S)", "14++ nm" },
{ 6, 5, -1, -1, 165, 4, -1, -1, { "Core(TM) i3-10###", 8 }, "Core i3 (Comet Lake-S)", "14++ nm" },
{ 6, 5, -1, -1, 165, 2, -1, -1, { "Pentium(R) Gold G6###", 6 }, "Pentium Gold (Comet Lake-S)", "14++ nm" },
{ 6, 5, -1, -1, 165, 2, -1, -1, { "Celeron(R) G5###", 4 }, "Celeron (Comet Lake-S)", "14++ nm" },
{ 6, 14, 12, -1, 142, 6, -1, -1, { "Core(TM) i7-10###U", 10 }, "Core i7 (Comet Lake-U)", "14++ nm" },
{ 6, 14, 12, -1, 142, 4, -1, -1, { "Core(TM) i7-10###U", 10 }, "Core i7 (Comet Lake-U)", "14++ nm" },
{ 6, 14, 12, -1, 142, 4, -1, -1, { "Core(TM) i5-10###U", 10 }, "Core i5 (Comet Lake-U)", "14++ nm" },
{ 6, 14, 12, -1, 142, 2, -1, -1, { "Pentium(R) Gold 6###U", 6 }, "Pentium Gold (Comet Lake-U)", "14++ nm" },
{ 6, 14, 12, -1, 142, 2, -1, -1, { "Celeron(R) 5###U", 4 }, "Celeron (Comet Lake-U)", "14++ nm" },
/* Ice Lake (client) CPUs (2019, 10th Core i gen, 10nm) => https://en.wikichip.org/wiki/intel/microarchitectures/ice_lake_(client) */
{ 6, 14, -1, -1, 126, 4, -1, -1, { "Core(TM) i7-10##", 8 }, "Core i7 (Ice Lake)" },
{ 6, 14, -1, -1, 126, 4, -1, -1, { "Core(TM) i5-10##", 8 }, "Core i5 (Ice Lake)" },
{ 6, 14, -1, -1, 126, 2, -1, -1, { "Core(TM) i3-10##", 8 }, "Core i3 (Ice Lake)" },
{ 6, 14, -1, -1, 126, 2, -1, -1, { "Pentium(R) 68##", 4 }, "Pentium (Ice Lake)" },
/* Ice Lake (server) CPUs (2021, 3rd Xeon Scalable gen, 10nm) => https://en.wikichip.org/wiki/intel/microarchitectures/ice_lake_(server) */
{ 6, 12, -1, -1, 108, 4, -1, -1, { "Xeon(R) D-[12]7##", 6 }, "Xeon D (Ice Lake-D)" },
{ 6, 10, -1, -1, 106, -1, -1, -1, { "Xeon(R) W-#3##", 6 }, "Xeon W (Ice Lake-W)" },
{ 6, 10, -1, -1, 106, -1, -1, -1, { "Xeon(R) Platinum #3##", 6 }, "Xeon Platinum (Ice Lake-SP)" },
{ 6, 10, -1, -1, 106, -1, -1, -1, { "Xeon(R) Gold #3##", 6 }, "Xeon Gold (Ice Lake-SP)" },
{ 6, 10, -1, -1, 106, -1, -1, -1, { "Xeon(R) Silver #3##", 6 }, "Xeon Silver (Ice Lake-SP)" },
{ 6, 10, -1, -1, 106, -1, -1, -1, { "Xeon(R) Bronze #3##", 6 }, "Xeon Bronze (Ice Lake-SP)" },
/* Ice Lake (client) CPUs (2019, 10th Core i gen, 10 nm) => https://en.wikichip.org/wiki/intel/microarchitectures/ice_lake_(client) */
{ 6, 14, -1, -1, 126, 4, -1, -1, { "Core(TM) i7-10##", 8 }, "Core i7 (Ice Lake)", "10 nm" },
{ 6, 14, -1, -1, 126, 4, -1, -1, { "Core(TM) i5-10##", 8 }, "Core i5 (Ice Lake)", "10 nm" },
{ 6, 14, -1, -1, 126, 2, -1, -1, { "Core(TM) i3-10##", 8 }, "Core i3 (Ice Lake)", "10 nm" },
{ 6, 14, -1, -1, 126, 2, -1, -1, { "Pentium(R) 68##", 4 }, "Pentium (Ice Lake)", "10 nm" },
/* Ice Lake (server) CPUs (2021, 3rd Xeon Scalable gen, 10 nm) => https://en.wikichip.org/wiki/intel/microarchitectures/ice_lake_(server) */
{ 6, 12, -1, -1, 108, 4, -1, -1, { "Xeon(R) D-[12]7##", 6 }, "Xeon D (Ice Lake-D)", "10 nm" },
{ 6, 10, -1, -1, 106, -1, -1, -1, { "Xeon(R) W-#3##", 6 }, "Xeon W (Ice Lake-W)", "10 nm" },
{ 6, 10, -1, -1, 106, -1, -1, -1, { "Xeon(R) Platinum #3##", 6 }, "Xeon Platinum (Ice Lake-SP)", "10 nm" },
{ 6, 10, -1, -1, 106, -1, -1, -1, { "Xeon(R) Gold #3##", 6 }, "Xeon Gold (Ice Lake-SP)", "10 nm" },
{ 6, 10, -1, -1, 106, -1, -1, -1, { "Xeon(R) Silver #3##", 6 }, "Xeon Silver (Ice Lake-SP)", "10 nm" },
{ 6, 10, -1, -1, 106, -1, -1, -1, { "Xeon(R) Bronze #3##", 6 }, "Xeon Bronze (Ice Lake-SP)", "10 nm" },
/* Rocket Lake CPUs (11th gen, 14nm): */
{ 6, 7, -1, -1, 167, -1, -1, -1, { "Core(TM) i9-11###", 8 }, "Core i9 (Rocket Lake-S)" },
{ 6, 7, -1, -1, 167, -1, -1, -1, { "Core(TM) i7-11###", 8 }, "Core i7 (Rocket Lake-S)" },
{ 6, 7, -1, -1, 167, -1, -1, -1, { "Core(TM) i5-11###", 8 }, "Core i5 (Rocket Lake-S)" },
{ 6, 7, -1, -1, 167, -1, -1, -1, { "Xeon(R) E-23##", 6 }, "Xeon E (Rocket Lake)" },
/* Rocket Lake CPUs (11th gen, 14++ nm): */
{ 6, 7, -1, -1, 167, -1, -1, -1, { "Core(TM) i9-11###", 8 }, "Core i9 (Rocket Lake-S)", "14++ nm" },
{ 6, 7, -1, -1, 167, -1, -1, -1, { "Core(TM) i7-11###", 8 }, "Core i7 (Rocket Lake-S)", "14++ nm" },
{ 6, 7, -1, -1, 167, -1, -1, -1, { "Core(TM) i5-11###", 8 }, "Core i5 (Rocket Lake-S)", "14++ nm" },
{ 6, 7, -1, -1, 167, -1, -1, -1, { "Xeon(R) E-23##", 6 }, "Xeon E (Rocket Lake)" , "14++ nm" },
/* Goldmont Plus CPUs (2017, 14nm, low-power) */
{ 6, 10, -1, -1, 122, -1, -1, -1, { "Pentium(R) Silver [JN]5###", 8 }, "Pentium (Gemini Lake)" },
{ 6, 10, -1, -1, 122, -1, -1, -1, { "Celeron(R) [JN]4###", 6 }, "Celeron (Gemini Lake)" },
{ 6, 12, -1, -1, 92, -1, -1, -1, { "Atom(TM)", 2 }, "Atom (Apollo Lake)" },
/* Goldmont Plus CPUs (2017, 14 nm, low-power) */
{ 6, 10, -1, -1, 122, -1, -1, -1, { "Pentium(R) Silver [JN]5###", 8 }, "Pentium (Gemini Lake)", "14 nm" },
{ 6, 10, -1, -1, 122, -1, -1, -1, { "Celeron(R) [JN]4###", 6 }, "Celeron (Gemini Lake)", "14 nm" },
{ 6, 12, -1, -1, 92, -1, -1, -1, { "Atom(TM)", 2 }, "Atom (Apollo Lake)" , "14 nm" },
/* Tremont CPUs (2020, 10nm, low-power) */
{ 6, 6, -1, -1, 150, -1, -1, -1, { "Pentium(R) [JN]6###", 6 }, "Pentium (Elkhart Lake)" },
{ 6, 6, -1, -1, 150, -1, -1, -1, { "Celeron(R) [JN]6###", 6 }, "Celeron (Elkhart Lake)" },
{ 6, 6, -1, -1, 150, -1, -1, -1, { "Atom(TM) x6###", 6 }, "Atom (Elkhart Lake)" },
{ 6, 10, -1, -1, 138, -1, -1, -1, { "Core(TM) i5-L##G7", 12 }, "Core i5 (Lakefield)" },
{ 6, 10, -1, -1, 138, -1, -1, -1, { "Core(TM) i3-L##G4", 12 }, "Core i3 (Lakefield)" },
{ 6, 12, -1, -1, 156, -1, -1, -1, { "Pentium(R) Silver N6###", 8 }, "Pentium Silver (Jasper Lake)" },
{ 6, 12, -1, -1, 156, -1, -1, -1, { "Celeron(R) N[45]###", 6 }, "Celeron (Jasper Lake)" },
/* Tremont CPUs (2020, Intel 10 nm, low-power) */
{ 6, 6, -1, -1, 150, -1, -1, -1, { "Pentium(R) [JN]6###", 6 }, "Pentium (Elkhart Lake)", "10 nm" },
{ 6, 6, -1, -1, 150, -1, -1, -1, { "Celeron(R) [JN]6###", 6 }, "Celeron (Elkhart Lake)", "10 nm" },
{ 6, 6, -1, -1, 150, -1, -1, -1, { "Atom(TM) x6###", 6 }, "Atom (Elkhart Lake)", "10 nm" },
{ 6, 10, -1, -1, 138, -1, -1, -1, { "Core(TM) i5-L##G7", 12 }, "Core i5 (Lakefield)", "10 nm" },
{ 6, 10, -1, -1, 138, -1, -1, -1, { "Core(TM) i3-L##G4", 12 }, "Core i3 (Lakefield)", "10 nm" },
{ 6, 12, -1, -1, 156, -1, -1, -1, { "Pentium(R) Silver N6###", 8 }, "Pentium Silver (Jasper Lake)", "10 nm" },
{ 6, 12, -1, -1, 156, -1, -1, -1, { "Celeron(R) N[45]###", 6 }, "Celeron (Jasper Lake)", "10 nm" },
/* Tiger Lake CPUs (2020, 11th gen, 10nm, mobile processors): */
{ 6, 12, -1, -1, 140, -1, -1, -1, { "Core(TM) i7-11##G7", 12 }, "Core i7 (Tiger Lake-UP3)" },
{ 6, 12, -1, -1, 140, -1, -1, -1, { "Core(TM) i5-11##G7", 12 }, "Core i5 (Tiger Lake-UP3)" },
{ 6, 12, -1, -1, 140, -1, -1, -1, { "Core(TM) i3-11##G7", 12 }, "Core i3 (Tiger Lake-UP3)" },
{ 6, 12, -1, -1, 140, 2, -1, -1, { "Pentium(R) Gold 7###", 6 }, "Pentium Gold (Tiger Lake-UP3)" },
{ 6, 12, -1, -1, 140, 2, -1, -1, { "Celeron(R) 6###", 4 }, "Celeron (Tiger Lake-UP3)" },
/* Tiger Lake CPUs (2020, 11th gen, Intel 10 nm SuperFin, mobile processors): */
{ 6, 12, -1, -1, 140, -1, -1, -1, { "Core(TM) i7-11##G7", 12 }, "Core i7 (Tiger Lake-UP3)", "10SF" },
{ 6, 12, -1, -1, 140, -1, -1, -1, { "Core(TM) i5-11##G7", 12 }, "Core i5 (Tiger Lake-UP3)", "10SF" },
{ 6, 12, -1, -1, 140, -1, -1, -1, { "Core(TM) i3-11##G7", 12 }, "Core i3 (Tiger Lake-UP3)", "10SF" },
{ 6, 12, -1, -1, 140, 2, -1, -1, { "Pentium(R) Gold 7###", 6 }, "Pentium Gold (Tiger Lake-UP3)", "10SF" },
{ 6, 12, -1, -1, 140, 2, -1, -1, { "Celeron(R) 6###", 4 }, "Celeron (Tiger Lake-UP3)", "10SF" },
/* Alder Lake CPUs (2021, 12th gen, 10nm) => https://en.wikichip.org/wiki/intel/microarchitectures/alder_lake */
{ 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i9-12###", 8 }, "Core i9 (Alder Lake-S)" },
{ 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i7-12###", 8 }, "Core i7 (Alder Lake-S)" },
{ 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i5-12###", 8 }, "Core i5 (Alder Lake-S)" },
{ 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i3-12###", 8 }, "Core i3 (Alder Lake-S)" },
{ 6, 7, -1, -1, 151, -1, -1, -1, { "Pentium(R) Gold G7###", 8 }, "Pentium Gold (Alder Lake-S)" },
{ 6, 7, -1, -1, 151, -1, -1, -1, { "Celeron(R) G6###", 6 }, "Celeron (Alder Lake-S)" },
{ 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i9-12###HX", 12 }, "Core i9 (Alder Lake-HX)" },
{ 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i7-12###HX", 12 }, "Core i7 (Alder Lake-HX)" },
{ 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i5-12###HX", 12 }, "Core i5 (Alder Lake-HX)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i7-12##P", 10 }, "Core i7 (Alder Lake-P)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i5-12##P", 10 }, "Core i5 (Alder Lake-P)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i3-12##P", 10 }, "Core i3 (Alder Lake-P)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i7-12##U", 10 }, "Core i7 (Alder Lake-U)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i5-12##U", 10 }, "Core i5 (Alder Lake-U)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i3-12##U", 10 }, "Core i3 (Alder Lake-U)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Pentium(R) Gold 8###", 6 }, "Pentium Gold (Alder Lake-U)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Celeron(R) 7###", 4 }, "Celeron (Alder Lake-U)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i9-12###H", 10 }, "Core i9 (Alder Lake-H)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i7-12###H", 10 }, "Core i7 (Alder Lake-H)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i5-12###H", 10 }, "Core i5 (Alder Lake-H)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i7-12##UL", 12 }, "Core i7 (Alder Lake-PS)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i5-12##UL", 12 }, "Core i5 (Alder Lake-PS)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i3-12##UL", 12 }, "Core i3 (Alder Lake-PS)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Celeron(R) 7###L", 6 }, "Celeron (Alder Lake-PS)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i7-12###HL", 12 }, "Core i7 (Alder Lake-PS)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i5-12###HL", 12 }, "Core i5 (Alder Lake-PS)" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i3-12###HL", 12 }, "Core i3 (Alder Lake-PS)" },
{ 6, 14, -1, -1, 190, -1, -1, -1, { "Core(TM) i3-N3##", 10 }, "Core i3 (Alder Lake-N)" }, /* Core i3 N300 + Core i3 N305 */
{ 6, 14, -1, -1, 190, 4, -1, -1, { "Processor N##", 4 }, "Intel Processor (Alder Lake-N)" },
{ 6, 14, -1, -1, 190, 2, -1, -1, { "Processor N##", 4 }, "Intel Processor (Alder Lake-N)" }, /* Intel Processor N50 */
{ 6, 14, -1, -1, 190, -1, -1, -1, { "Atom(TM) x7###E", 8 }, "Atom (Alder Lake-N)" },
/* Alder Lake CPUs (2021, 12th gen, Intel 7) => https://en.wikichip.org/wiki/intel/microarchitectures/alder_lake */
{ 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i9-12###", 8 }, "Core i9 (Alder Lake-S)", "Intel 7" },
{ 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i7-12###", 8 }, "Core i7 (Alder Lake-S)", "Intel 7" },
{ 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i5-12###", 8 }, "Core i5 (Alder Lake-S)", "Intel 7" },
{ 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i3-12###", 8 }, "Core i3 (Alder Lake-S)", "Intel 7" },
{ 6, 7, -1, -1, 151, -1, -1, -1, { "Pentium(R) Gold G7###", 8 }, "Pentium Gold (Alder Lake-S)" , "Intel 7" },
{ 6, 7, -1, -1, 151, -1, -1, -1, { "Celeron(R) G6###", 6 }, "Celeron (Alder Lake-S)", "Intel 7" },
{ 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i9-12###HX", 12 }, "Core i9 (Alder Lake-HX)", "Intel 7" },
{ 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i7-12###HX", 12 }, "Core i7 (Alder Lake-HX)", "Intel 7" },
{ 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i5-12###HX", 12 }, "Core i5 (Alder Lake-HX)", "Intel 7" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i7-12##P", 10 }, "Core i7 (Alder Lake-P)", "Intel 7" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i5-12##P", 10 }, "Core i5 (Alder Lake-P)", "Intel 7" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i3-12##P", 10 }, "Core i3 (Alder Lake-P)", "Intel 7" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i7-12##U", 10 }, "Core i7 (Alder Lake-U)", "Intel 7" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i5-12##U", 10 }, "Core i5 (Alder Lake-U)", "Intel 7" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i3-12##U", 10 }, "Core i3 (Alder Lake-U)", "Intel 7" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Pentium(R) Gold 8###", 6 }, "Pentium Gold (Alder Lake-U)", "Intel 7" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Celeron(R) 7###", 4 }, "Celeron (Alder Lake-U)", "Intel 7" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i9-12###H", 10 }, "Core i9 (Alder Lake-H)", "Intel 7" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i7-12###H", 10 }, "Core i7 (Alder Lake-H)", "Intel 7" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i5-12###H", 10 }, "Core i5 (Alder Lake-H)", "Intel 7" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i7-12##UL", 12 }, "Core i7 (Alder Lake-PS)", "Intel 7" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i5-12##UL", 12 }, "Core i5 (Alder Lake-PS)", "Intel 7" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i3-12##UL", 12 }, "Core i3 (Alder Lake-PS)", "Intel 7" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Celeron(R) 7###L", 6 }, "Celeron (Alder Lake-PS)", "Intel 7" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i7-12###HL", 12 }, "Core i7 (Alder Lake-PS)", "Intel 7" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i5-12###HL", 12 }, "Core i5 (Alder Lake-PS)", "Intel 7" },
{ 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i3-12###HL", 12 }, "Core i3 (Alder Lake-PS)", "Intel 7" },
{ 6, 14, -1, -1, 190, -1, -1, -1, { "Core(TM) i3-N3##", 10 }, "Core i3 (Alder Lake-N)", "Intel 7" }, /* Core i3 N300 + Core i3 N305 */
{ 6, 14, -1, -1, 190, 4, -1, -1, { "Processor N##", 4 }, "Intel Processor (Alder Lake-N)", "Intel 7" },
{ 6, 14, -1, -1, 190, 2, -1, -1, { "Processor N##", 4 }, "Intel Processor (Alder Lake-N)", "Intel 7" }, /* Intel Processor N50 */
{ 6, 14, -1, -1, 190, -1, -1, -1, { "Atom(TM) x7###E", 8 }, "Atom (Alder Lake-N)", "Intel 7" },
/* Twin Lake CPUs (2025, Intel 7) => https://en.wikichip.org/wiki/intel/microarchitectures/twin_lake */
{ 6, 14, -1, -1, 190, 8, -1, -1, { "Core(TM) 3 N#5#", 8 }, "Core 3 (Twin Lake-N)" }, /* Core 3 N350 + Core 3 N355 */
{ 6, 14, -1, -1, 190, 4, -1, -1, { "Processor N#5#", 6 }, "Intel Processor (Twin Lake-N)" }, /* Intel Processor N150 + Intel Processor N150 */
{ 6, 14, -1, -1, 190, 8, -1, -1, { "Core(TM) 3 N#5#", 8 }, "Core 3 (Twin Lake-N)", "Intel 7" }, /* Core 3 N350 + Core 3 N355 */
{ 6, 14, -1, -1, 190, 4, -1, -1, { "Processor N#5#", 6 }, "Intel Processor (Twin Lake-N)", "Intel 7" }, /* Intel Processor N150 + Intel Processor N150 */
/* Raptor Lake CPUs (2022, 13th Core i gen, Intel 7) => https://en.wikichip.org/wiki/intel/microarchitectures/raptor_lake */
{ 6, 15, -1, -1, 191, -1, -1, -1, { "Core(TM) i5-13###", 8 }, "Core i5 (Raptor Lake-S)" }, // "Golden Cove" cores
{ 6, 15, -1, -1, 191, -1, -1, -1, { "Core(TM) i3-13###", 8 }, "Core i3 (Raptor Lake-S)" }, // "Golden Cove" cores
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i9-13###", 8 }, "Core i9 (Raptor Lake-S)" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i7-13###", 8 }, "Core i7 (Raptor Lake-S)" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i5-13###", 8 }, "Core i5 (Raptor Lake-S)" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i3-13###", 8 }, "Core i3 (Raptor Lake-S)" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i9-13###HX", 12 }, "Core i9 (Raptor Lake-HX)" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i7-13###HX", 12 }, "Core i7 (Raptor Lake-HX)" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i5-13###HX", 12 }, "Core i5 (Raptor Lake-HX)" },
{ 6, 10, 2, -1, 186, -1, -1, -1, { "Core(TM) i7-13###P", 10 }, "Core i7 (Raptor Lake-P)" },
{ 6, 10, 2, -1, 186, -1, -1, -1, { "Core(TM) i5-13###P", 10 }, "Core i5 (Raptor Lake-P)" },
{ 6, 10, 3, -1, 186, -1, -1, -1, { "Core(TM) i7-13###U", 10 }, "Core i7 (Raptor Lake-U)" },
{ 6, 10, 3, -1, 186, -1, -1, -1, { "Core(TM) i5-13###U", 10 }, "Core i5 (Raptor Lake-U)" },
{ 6, 10, 3, -1, 186, -1, -1, -1, { "Core(TM) i3-13###U", 10 }, "Core i3 (Raptor Lake-U)" },
{ 6, 10, 3, -1, 186, -1, -1, -1, { "Processor U300", 6 }, "Intel Processor (Raptor Lake-U)" }, /* Intel Processor U300 */
{ 6, 10, -1, -1, 186, -1, -1, -1, { "Core(TM) i9-13###H", 10 }, "Core i9 (Raptor Lake-H)" },
{ 6, 10, -1, -1, 186, -1, -1, -1, { "Core(TM) i7-13###H", 10 }, "Core i7 (Raptor Lake-H)" },
{ 6, 10, -1, -1, 186, -1, -1, -1, { "Core(TM) i5-13###H", 10 }, "Core i5 (Raptor Lake-H)" },
{ 6, 15, -1, -1, 191, -1, -1, -1, { "Core(TM) i5-13###", 8 }, "Core i5 (Raptor Lake-S)", "Intel 7" }, /* "Golden Cove" cores */
{ 6, 15, -1, -1, 191, -1, -1, -1, { "Core(TM) i3-13###", 8 }, "Core i3 (Raptor Lake-S)", "Intel 7" }, /* "Golden Cove" cores */
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i9-13###", 8 }, "Core i9 (Raptor Lake-S)", "Intel 7" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i7-13###", 8 }, "Core i7 (Raptor Lake-S)", "Intel 7" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i5-13###", 8 }, "Core i5 (Raptor Lake-S)", "Intel 7" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i3-13###", 8 }, "Core i3 (Raptor Lake-S)", "Intel 7" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i9-13###HX", 12 }, "Core i9 (Raptor Lake-HX)", "Intel 7" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i7-13###HX", 12 }, "Core i7 (Raptor Lake-HX)", "Intel 7" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i5-13###HX", 12 }, "Core i5 (Raptor Lake-HX)", "Intel 7" },
{ 6, 10, 2, -1, 186, -1, -1, -1, { "Core(TM) i7-13###P", 10 }, "Core i7 (Raptor Lake-P)", "Intel 7" },
{ 6, 10, 2, -1, 186, -1, -1, -1, { "Core(TM) i5-13###P", 10 }, "Core i5 (Raptor Lake-P)", "Intel 7" },
{ 6, 10, 3, -1, 186, -1, -1, -1, { "Core(TM) i7-13###U", 10 }, "Core i7 (Raptor Lake-U)", "Intel 7" },
{ 6, 10, 3, -1, 186, -1, -1, -1, { "Core(TM) i5-13###U", 10 }, "Core i5 (Raptor Lake-U)", "Intel 7" },
{ 6, 10, 3, -1, 186, -1, -1, -1, { "Core(TM) i3-13###U", 10 }, "Core i3 (Raptor Lake-U)", "Intel 7" },
{ 6, 10, 3, -1, 186, -1, -1, -1, { "Processor U300", 6 }, "Intel Processor (Raptor Lake-U)", "Intel 7" }, /* Intel Processor U300 */
{ 6, 10, -1, -1, 186, -1, -1, -1, { "Core(TM) i9-13###H", 10 }, "Core i9 (Raptor Lake-H)", "Intel 7" },
{ 6, 10, -1, -1, 186, -1, -1, -1, { "Core(TM) i7-13###H", 10 }, "Core i7 (Raptor Lake-H)", "Intel 7" },
{ 6, 10, -1, -1, 186, -1, -1, -1, { "Core(TM) i5-13###H", 10 }, "Core i5 (Raptor Lake-H)", "Intel 7" },
/* Raptor Lake Refresh CPUs (2023, 14th Core i gen, Intel 7) => https://en.wikipedia.org/wiki/Raptor_Lake#List_of_14th_generation_Raptor_Lake_processors */
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i9-14###", 8 }, "Core i9 (Raptor Lake-S)" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i7-14###", 8 }, "Core i7 (Raptor Lake-S)" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i5-14###", 8 }, "Core i5 (Raptor Lake-S)" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i3-14###", 8 }, "Core i3 (Raptor Lake-S)" },
{ 6, 7, -1, -1, 183, 2, -1, -1, { "Processor 300", 4 }, "Intel Processor (Raptor Lake-S)"}, /* Intel Processor 300 + Intel Processor 300T */
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i9-14###HX", 12 }, "Core i9 (Raptor Lake-HX)" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i7-14###HX", 12 }, "Core i7 (Raptor Lake-HX)" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i5-14###HX", 12 }, "Core i5 (Raptor Lake-HX)" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Xeon(R) E-24##", 6 }, "Xeon E (Raptor Lake)" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 7 1##U", 8 }, "Core 7 (Raptor Lake-U)" }, /* Core 7 150U */
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 5 1##U", 8 }, "Core 5 (Raptor Lake-U)" }, /* Core 5 120U */
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 3 1##U", 8 }, "Core 3 (Raptor Lake-U)" }, /* Core 3 100U */
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i9-14###", 8 }, "Core i9 (Raptor Lake-S)" , "Intel 7" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i7-14###", 8 }, "Core i7 (Raptor Lake-S)" , "Intel 7" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i5-14###", 8 }, "Core i5 (Raptor Lake-S)" , "Intel 7" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i3-14###", 8 }, "Core i3 (Raptor Lake-S)" , "Intel 7" },
{ 6, 7, -1, -1, 183, 2, -1, -1, { "Processor 300", 4 }, "Intel Processor (Raptor Lake-S)", "Intel 7" }, /* Intel Processor 300 + Intel Processor 300T */
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i9-14###HX", 12 }, "Core i9 (Raptor Lake-HX)", "Intel 7" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i7-14###HX", 12 }, "Core i7 (Raptor Lake-HX)", "Intel 7" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i5-14###HX", 12 }, "Core i5 (Raptor Lake-HX)", "Intel 7" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Xeon(R) E-24##", 6 }, "Xeon E (Raptor Lake)", "Intel 7" },
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 7 1##U", 8 }, "Core 7 (Raptor Lake-U)", "Intel 7" }, /* Core 7 150U */
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 5 1##U", 8 }, "Core 5 (Raptor Lake-U)", "Intel 7" }, /* Core 5 120U */
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 3 1##U", 8 }, "Core 3 (Raptor Lake-U)", "Intel 7" }, /* Core 3 100U */
/* Raptor Lake Re-refresh CPUs (2025, Core Series 2 processors Intel 7) => https://en.wikipedia.org/wiki/Raptor_Lake#List_of_Core_Series_2_processors */
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 7 2##U", 8 }, "Core 7 (Raptor Lake-U)" }, /* Core 7 250U */
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 5 2##U", 8 }, "Core 5 (Raptor Lake-U)" }, /* Core 5 220U */
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 9 2##H", 8 }, "Core 9 (Raptor Lake-H)" }, /* Core 9 270H */
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 7 2##H", 8 }, "Core 7 (Raptor Lake-H)" }, /* Core 7 240H + Core 7 250H */
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 5 2##H", 8 }, "Core 5 (Raptor Lake-H)" }, /* Core 5 210H + Core 5 220H */
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 7 2##U", 8 }, "Core 7 (Raptor Lake-U)", "Intel 7" }, /* Core 7 250U */
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 5 2##U", 8 }, "Core 5 (Raptor Lake-U)", "Intel 7" }, /* Core 5 220U */
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 9 2##H", 8 }, "Core 9 (Raptor Lake-H)", "Intel 7" }, /* Core 9 270H */
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 7 2##H", 8 }, "Core 7 (Raptor Lake-H)", "Intel 7" }, /* Core 7 240H + Core 7 250H */
{ 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 5 2##H", 8 }, "Core 5 (Raptor Lake-H)", "Intel 7" }, /* Core 5 210H + Core 5 220H */
/* Sapphire Rapids CPUs (2023, 4th Xeon Scalable gen, Intel 7) => https://en.wikichip.org/wiki/intel/microarchitectures/sapphire_rapids */
{ 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) w9-#4##", 6 }, "Xeon w9 (Sapphire Rapids-WS)" },
{ 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) w7-#4##", 6 }, "Xeon w7 (Sapphire Rapids-WS)" },
{ 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) w5-#4##", 6 }, "Xeon w5 (Sapphire Rapids-WS)" },
{ 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) w3-#4##", 6 }, "Xeon w3 (Sapphire Rapids-WS)" },
{ 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) Max #4##", 6 }, "Xeon Max (Sapphire Rapids-HBM)" },
{ 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) Platinum #4##", 6 }, "Xeon Platinum (Sapphire Rapids-SP)" },
{ 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) Gold #4##", 6 }, "Xeon Gold (Sapphire Rapids-SP)" },
{ 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) Silver #4##", 6 }, "Xeon Silver (Sapphire Rapids-SP)" },
{ 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) Bronze #4##", 6 }, "Xeon Bronze (Sapphire Rapids-SP)" },
{ 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) w9-#4##", 6 }, "Xeon w9 (Sapphire Rapids-WS)", "Intel 7" },
{ 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) w7-#4##", 6 }, "Xeon w7 (Sapphire Rapids-WS)", "Intel 7" },
{ 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) w5-#4##", 6 }, "Xeon w5 (Sapphire Rapids-WS)", "Intel 7" },
{ 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) w3-#4##", 6 }, "Xeon w3 (Sapphire Rapids-WS)", "Intel 7" },
{ 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) Max #4##", 6 }, "Xeon Max (Sapphire Rapids-HBM)", "Intel 7" },
{ 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) Platinum #4##", 6 }, "Xeon Platinum (Sapphire Rapids-SP)", "Intel 7" },
{ 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) Gold #4##", 6 }, "Xeon Gold (Sapphire Rapids-SP)", "Intel 7" },
{ 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) Silver #4##", 6 }, "Xeon Silver (Sapphire Rapids-SP)" , "Intel 7" },
{ 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) Bronze #4##", 6 }, "Xeon Bronze (Sapphire Rapids-SP)" , "Intel 7" },
/* Emerald Rapids CPUs (2023, 5th Xeon Scalable gen, Intel 7) => https://en.wikichip.org/wiki/intel/microarchitectures/emerald_rapids */
{ 6, 15, -1, -1, 207, -1, -1, -1, { "Xeon(R) Platinum #5##", 6 }, "Xeon Platinum (Emerald Rapids-SP)" }, // Xeon Platinum (8500)
{ 6, 15, -1, -1, 207, -1, -1, -1, { "Xeon(R) Gold #5##", 6 }, "Xeon Gold (Emerald Rapids-SP)" }, // Xeon Gold (5500 and 6500)
{ 6, 15, -1, -1, 207, -1, -1, -1, { "Xeon(R) Silver #5##", 6 }, "Xeon Silver (Emerald Rapids-SP)" }, // Xeon Silver (4500)
{ 6, 15, -1, -1, 207, -1, -1, -1, { "Xeon(R) Bronze #5##", 6 }, "Xeon Bronze (Emerald Rapids-SP)" }, // Xeon Bronze (3500)
{ 6, 15, -1, -1, 207, -1, -1, -1, { "Xeon(R) Platinum #5##", 6 }, "Xeon Platinum (Emerald Rapids-SP)" , "Intel 7" }, /* Xeon Platinum (8500) */
{ 6, 15, -1, -1, 207, -1, -1, -1, { "Xeon(R) Gold #5##", 6 }, "Xeon Gold (Emerald Rapids-SP)", "Intel 7" }, /* Xeon Gold (5500 and 6500) */
{ 6, 15, -1, -1, 207, -1, -1, -1, { "Xeon(R) Silver #5##", 6 }, "Xeon Silver (Emerald Rapids-SP)" , "Intel 7" }, /* Xeon Silver (4500) */
{ 6, 15, -1, -1, 207, -1, -1, -1, { "Xeon(R) Bronze #5##", 6 }, "Xeon Bronze (Emerald Rapids-SP)" , "Intel 7" }, /* Xeon Bronze (3500) */
/* Meteor Lake CPUs (2023, Core Ultra Series 1 processors, Intel 4) => https://en.wikichip.org/wiki/intel/microarchitectures/meteor_lake */
{ 6, 10, -1, -1, 170, -1, -1, -1, { "Core(TM) Ultra 9 1##H", 10 }, "Core Ultra 9 (Meteor Lake-H)" },
{ 6, 10, -1, -1, 170, -1, -1, -1, { "Core(TM) Ultra 7 1##H", 10 }, "Core Ultra 7 (Meteor Lake-H)" },
{ 6, 10, -1, -1, 170, -1, -1, -1, { "Core(TM) Ultra 5 1##H", 10 }, "Core Ultra 5 (Meteor Lake-H)" },
{ 6, 10, -1, -1, 170, -1, -1, -1, { "Core(TM) Ultra 7 1##U", 10 }, "Core Ultra 7 (Meteor Lake-U)" },
{ 6, 10, -1, -1, 170, -1, -1, -1, { "Core(TM) Ultra 5 1##U", 10 }, "Core Ultra 5 (Meteor Lake-U)" },
{ 6, 10, -1, -1, 170, -1, -1, -1, { "Core(TM) Ultra 9 1##H", 10 }, "Core Ultra 9 (Meteor Lake-H)", "Intel 4" },
{ 6, 10, -1, -1, 170, -1, -1, -1, { "Core(TM) Ultra 7 1##H", 10 }, "Core Ultra 7 (Meteor Lake-H)", "Intel 4" },
{ 6, 10, -1, -1, 170, -1, -1, -1, { "Core(TM) Ultra 5 1##H", 10 }, "Core Ultra 5 (Meteor Lake-H)", "Intel 4" },
{ 6, 10, -1, -1, 170, -1, -1, -1, { "Core(TM) Ultra 7 1##U", 10 }, "Core Ultra 7 (Meteor Lake-U)", "Intel 4" },
{ 6, 10, -1, -1, 170, -1, -1, -1, { "Core(TM) Ultra 5 1##U", 10 }, "Core Ultra 5 (Meteor Lake-U)", "Intel 4" },
/* Arrow Lake CPUs (2024, Core Ultra Series 2 processors, TSMC N3B) => https://en.wikichip.org/wiki/intel/microarchitectures/arrow_lake */
{ 6, 6, -1, -1, 198, -1, -1, -1, { "Core(TM) Ultra 9 2##", 8 }, "Core Ultra 9 (Arrow Lake-S)" },
{ 6, 6, -1, -1, 198, -1, -1, -1, { "Core(TM) Ultra 7 2##", 8 }, "Core Ultra 7 (Arrow Lake-S)" },
{ 6, 6, -1, -1, 198, -1, -1, -1, { "Core(TM) Ultra 5 2##", 8 }, "Core Ultra 5 (Arrow Lake-S)" },
{ 6, 6, -1, -1, 181, -1, -1, -1, { "Core(TM) Ultra 7 2##U", 10 }, "Core Ultra 7 (Arrow Lake-U)" }, /* Core Ultra 7 255U + Core Ultra 7 265U */
{ 6, 6, -1, -1, 181, -1, -1, -1, { "Core(TM) Ultra 5 2##U", 10 }, "Core Ultra 5 (Arrow Lake-U)" }, /* Core Ultra 5 225U + Core Ultra 7 235U */
{ 6, 6, -1, -1, 197, -1, -1, -1, { "Core(TM) Ultra 9 2##H", 10 }, "Core Ultra 9 (Arrow Lake-H)" }, /* Core Ultra 9 285H */
{ 6, 6, -1, -1, 197, -1, -1, -1, { "Core(TM) Ultra 7 2##H", 10 }, "Core Ultra 7 (Arrow Lake-H)" }, /* Core Ultra 7 255H + Core Ultra 7 265H */
{ 6, 6, -1, -1, 197, -1, -1, -1, { "Core(TM) Ultra 5 2##H", 10 }, "Core Ultra 5 (Arrow Lake-H)" }, /* Core Ultra 5 225H + Core Ultra 7 235H */
{ 6, 6, -1, -1, 198, -1, -1, -1, { "Core(TM) Ultra 9 2##", 8 }, "Core Ultra 9 (Arrow Lake-S)", "TSMC N3B" },
{ 6, 6, -1, -1, 198, -1, -1, -1, { "Core(TM) Ultra 7 2##", 8 }, "Core Ultra 7 (Arrow Lake-S)", "TSMC N3B" },
{ 6, 6, -1, -1, 198, -1, -1, -1, { "Core(TM) Ultra 5 2##", 8 }, "Core Ultra 5 (Arrow Lake-S)", "TSMC N3B" },
{ 6, 6, -1, -1, 181, -1, -1, -1, { "Core(TM) Ultra 7 2##U", 10 }, "Core Ultra 7 (Arrow Lake-U)", "TSMC N3B" }, /* Core Ultra 7 255U + Core Ultra 7 265U */
{ 6, 6, -1, -1, 181, -1, -1, -1, { "Core(TM) Ultra 5 2##U", 10 }, "Core Ultra 5 (Arrow Lake-U)", "TSMC N3B" }, /* Core Ultra 5 225U + Core Ultra 7 235U */
{ 6, 6, -1, -1, 197, -1, -1, -1, { "Core(TM) Ultra 9 2##H", 10 }, "Core Ultra 9 (Arrow Lake-H)", "TSMC N3B" }, /* Core Ultra 9 285H */
{ 6, 6, -1, -1, 197, -1, -1, -1, { "Core(TM) Ultra 7 2##H", 10 }, "Core Ultra 7 (Arrow Lake-H)", "TSMC N3B" }, /* Core Ultra 7 255H + Core Ultra 7 265H */
{ 6, 6, -1, -1, 197, -1, -1, -1, { "Core(TM) Ultra 5 2##H", 10 }, "Core Ultra 5 (Arrow Lake-H)", "TSMC N3B" }, /* Core Ultra 5 225H + Core Ultra 7 235H */
/* Lunar Lake CPUs (2024, Core Ultra Series 2 processors, TSMC N3B) => https://en.wikichip.org/wiki/intel/microarchitectures/lunar_lake */
{ 6, 13, -1, -1, 189, -1, -1, -1, { "Core(TM) Ultra 9 2##V", 10 }, "Core Ultra 9 (Lunar Lake-V)" },
{ 6, 13, -1, -1, 189, -1, -1, -1, { "Core(TM) Ultra 7 2##V", 10 }, "Core Ultra 7 (Lunar Lake-V)" },
{ 6, 13, -1, -1, 189, -1, -1, -1, { "Core(TM) Ultra 5 2##V", 10 }, "Core Ultra 5 (Lunar Lake-V)" },
// F M S EF EM #cores L2$ L3$ Pattern Name
{ 6, 13, -1, -1, 189, -1, -1, -1, { "Core(TM) Ultra 9 2##V", 10 }, "Core Ultra 9 (Lunar Lake-V)", "TSMC N3B" },
{ 6, 13, -1, -1, 189, -1, -1, -1, { "Core(TM) Ultra 7 2##V", 10 }, "Core Ultra 7 (Lunar Lake-V)", "TSMC N3B" },
{ 6, 13, -1, -1, 189, -1, -1, -1, { "Core(TM) Ultra 5 2##V", 10 }, "Core Ultra 5 (Lunar Lake-V)", "TSMC N3B" },
// F M S EF EM #cores L2$ L3$ Pattern Codename Technology
/* Itaniums */
{ 7, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Itanium" },
{ 15, -1, -1, 16, -1, 1, -1, -1, { "", 0 }, "Itanium 2" },
{ 7, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Itanium", UNKN_STR },
{ 15, -1, -1, 16, -1, 1, -1, -1, { "", 0 }, "Itanium 2", UNKN_STR },
};

1
tests/amd/bobcat/brazos-zacate.test
View file

@ -103,4 +103,5 @@ general
-1
64 (authoritative)
E-Series (Zacate)
TSMC N40
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni monitor ssse3 cx16 syscall popcnt mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch ibs skinit wdt ts ttp tm_amd stc 100mhzsteps hwpstate constant_tsc

1
tests/amd/bulldozer/bald-eagle-x4.test
View file

@ -219,4 +219,5 @@ general
-1
128 (authoritative)
R-Series (Bald Eagle)
TSMC N28
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc xop fma3 fma4 tbm f16c cpb aperfmperf bmi1

1
tests/amd/bulldozer/godavari-x4.test
View file

@ -111,4 +111,5 @@ general
-1
128 (authoritative)
Athlon X4 (Godavari)
TSMC N28
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc xop fma3 fma4 tbm f16c cpb aperfmperf bmi1

1
tests/amd/bulldozer/kaveri-x4.test
View file

@ -223,4 +223,5 @@ general
-1
128 (authoritative)
Athlon X4 (Kaveri)
TSMC N28
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc xop fma3 fma4 tbm f16c cpb aperfmperf bmi1

1
tests/amd/bulldozer/opteron-abu-dhabi.test
View file

@ -847,4 +847,5 @@ general
-1
128 (authoritative)
Opteron (Abu Dhabi)
GF 32SHP
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc xop fma3 fma4 tbm f16c cpb aperfmperf bmi1

1
tests/amd/bulldozer/opteron-interlagos.test
View file

@ -643,4 +643,5 @@ general
-1
128 (authoritative)
Opteron (Interlagos)
GF 32SHP
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc xop fma4 cpb

1
tests/amd/bulldozer/vishera-x4.test
View file

@ -103,4 +103,5 @@ general
-1
128 (authoritative)
FX (Vishera)
GF 32SHP
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc xop fma3 fma4 tbm f16c cpb aperfmperf bmi1

1
tests/amd/bulldozer/zambezi-x3.test
View file

@ -325,4 +325,5 @@ general
-1
128 (authoritative)
FX (Zambezi)
GF 32SHP
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc xop fma4 cpb

1
tests/amd/bulldozer/zambezi-x4.test
View file

@ -103,4 +103,5 @@ general
-1
128 (authoritative)
FX (Zambezi)
GF 32SHP
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc xop fma4 cpb

1
tests/amd/jaguar/athlon-kabini.test
View file

@ -227,4 +227,5 @@ general
-1
128 (authoritative)
Athlon X4 (Kabini)
TSMC N28
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc f16c pfi bmi1

1
tests/amd/jaguar/beema-x4.test
View file

@ -223,4 +223,5 @@ general
-1
128 (authoritative)
A-Series (Beema)
GF 28SHP
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc f16c rdrand cpb pa bmi1

1
tests/amd/jaguar/kabini-x4.test
View file

@ -223,4 +223,5 @@ general
-1
128 (authoritative)
A-Series (Kabini)
TSMC N28
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc f16c pfi bmi1

1
tests/amd/jaguar/steppe-eagle-x2.test
View file

@ -129,4 +129,5 @@ general
-1
128 (authoritative)
G-Series (Steppe Eagle)
GF 28SHP
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd 100mhzsteps hwpstate constant_tsc f16c rdrand pa bmi1

1
tests/amd/k10/athlon-2-champlain-mobile.test
View file

@ -103,4 +103,5 @@ general
-1
64 (authoritative)
Athlon II (Champlain)
45 nm
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni monitor cx16 syscall popcnt mmxext 3dnow 3dnowext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd stc 100mhzsteps hwpstate constant_tsc

1
tests/amd/k10/athlon-2-kuma.test
View file

@ -103,4 +103,5 @@ general
-1
128 (authoritative)
Athlon X2 (Kuma)
65 nm
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni monitor cx16 syscall popcnt mmxext 3dnow 3dnowext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs ts ttp tm_amd stc 100mhzsteps hwpstate constant_tsc

1
tests/amd/k10/athlon-2-propus-2.test
View file

@ -103,4 +103,5 @@ general
-1
128 (authoritative)
Athlon II X4 (Propus)
45 nm
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni monitor cx16 syscall popcnt mmxext 3dnow 3dnowext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd stc 100mhzsteps hwpstate constant_tsc

1
tests/amd/k10/athlon-2-propus-3.test
View file

@ -103,4 +103,5 @@ general
-1
128 (authoritative)
Athlon II X4 (Propus)
45 nm
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni monitor cx16 syscall popcnt mmxext 3dnow 3dnowext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd stc 100mhzsteps hwpstate constant_tsc

1
tests/amd/k10/athlon-2-propus.test
View file

@ -103,4 +103,5 @@ general
-1
128 (authoritative)
Athlon II X4 (Propus)
45 nm
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni monitor cx16 syscall popcnt mmxext 3dnow 3dnowext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd stc 100mhzsteps hwpstate constant_tsc

1
tests/amd/k10/athlon-2-regor.test
View file

@ -103,4 +103,5 @@ general
-1
128 (authoritative)
Athlon II X2 (Regor)
45 nm
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni monitor cx16 syscall popcnt mmxext 3dnow 3dnowext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd stc 100mhzsteps hwpstate constant_tsc

1
tests/amd/k10/magny-cours.test
View file

@ -103,4 +103,5 @@ general
-1
128 (authoritative)
Opteron (Magny-Cours)
45 nm
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni monitor cx16 syscall popcnt mmxext 3dnow 3dnowext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd stc 100mhzsteps hwpstate constant_tsc

1
tests/amd/k10/phenom-2-deneb.test
View file

@ -103,4 +103,5 @@ general
-1
128 (authoritative)
Phenom II X4 (Deneb)
45 nm
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni monitor cx16 syscall popcnt mmxext 3dnow 3dnowext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd stc 100mhzsteps hwpstate constant_tsc

1
tests/amd/k10/phenom-2-heka.test
View file

@ -103,4 +103,5 @@ general
-1
128 (authoritative)
Phenom II X3 (Heka)
45 nm
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni monitor cx16 syscall popcnt mmxext 3dnow 3dnowext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd stc 100mhzsteps hwpstate constant_tsc

1
tests/amd/k10/phenom-2-thuban.test
View file

@ -103,4 +103,5 @@ general
-1
128 (authoritative)
Phenom II X6 (Thuban)
45 nm
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni monitor cx16 syscall popcnt mmxext 3dnow 3dnowext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd stc 100mhzsteps hwpstate constant_tsc cpb

1
tests/amd/k10/phenom-agena.test
View file

@ -99,4 +99,5 @@ general
-1
128 (authoritative)
Phenom X4 (Agena/512K)
65 nm
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni monitor cx16 syscall popcnt mmxext 3dnow 3dnowext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs ts ttp tm_amd stc 100mhzsteps hwpstate constant_tsc

1
tests/amd/k10/sempron-sargas.test
View file

@ -103,4 +103,5 @@ general
-1
128 (authoritative)
Sempron (Sargas)
45 nm
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 pni monitor cx16 syscall popcnt mmxext 3dnow 3dnowext nx fxsr_opt rdtscp lm lahf_lm svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd stc 100mhzsteps hwpstate constant_tsc

1
tests/amd/k7/athlon-thoroughbred.test
View file

@ -99,4 +99,5 @@ general
-1
64 (non-authoritative)
Athlon XP (Thoroughbred)
130 nm
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 mmx fxsr sse syscall mmxext 3dnow 3dnowext ts

1
tests/amd/k7/duron-applebred.test
View file

@ -99,4 +99,5 @@ general
-1
64 (non-authoritative)
Duron (Applebred)
130 nm
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 mmx fxsr sse syscall mmxext 3dnow 3dnowext ts

1
tests/amd/k7/sempron-barton.test
View file

@ -99,4 +99,5 @@ general
-1
64 (non-authoritative)
Sempron (Barton)
130 nm
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 mmx fxsr sse syscall mmxext 3dnow 3dnowext ts fid vid

1
tests/amd/k8/athlon-64-brisbane.test
View file

@ -99,4 +99,5 @@ general
-1
64 (non-authoritative)
Athlon 64 X2 (Brisbane/512K)
65 nm
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni cx16 syscall mmxext 3dnow 3dnowext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm 3dnowprefetch ts fid vid ttp tm_amd stc 100mhzsteps

1
tests/amd/k8/athlon-64-sherman.test
View file

@ -112,4 +112,5 @@ general
-1
64 (non-authoritative)
Athlon 64 (Sherman/512K)
65 nm
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 pni cx16 syscall mmxext 3dnow 3dnowext nx fxsr_opt rdtscp lm lahf_lm svm 3dnowprefetch ts fid vid ttp tm_amd stc 100mhzsteps

1
tests/amd/k8/athlon-64-venice.test
View file

@ -99,4 +99,5 @@ general
-1
64 (non-authoritative)
Athlon 64 (Venice/512K)
90 nm
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 pni syscall mmxext 3dnow 3dnowext nx fxsr_opt lm lahf_lm ts fid vid ttp tm_amd stc

1
tests/amd/k8/mobile-sempron-64-keene.test
View file

@ -99,4 +99,5 @@ general
-1
64 (non-authoritative)
Mobile Sempron 64 (Keene/512K)
90 nm
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 pni cx16 syscall mmxext 3dnow 3dnowext nx fxsr_opt rdtscp lm lahf_lm ts fid vid ttp tm_amd stc

1
tests/amd/k8/mobile-sempron-64-sonora.test
View file

@ -99,4 +99,5 @@ general
-1
64 (non-authoritative)
Mobile Sempron 64 (Sonora/128K)
90 nm
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 syscall mmxext 3dnow 3dnowext nx fxsr_opt lahf_lm ts fid vid ttp

1
tests/amd/k8/opteron-denmark.test
View file

@ -99,4 +99,5 @@ general
-1
64 (non-authoritative)
Opteron (Dual Core)
unknown
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni syscall mmxext 3dnow 3dnowext nx fxsr_opt lm lahf_lm cmp_legacy ts fid vid ttp

1
tests/amd/k8/sempron-64-sparta.test
View file

@ -99,4 +99,5 @@ general
-1
64 (non-authoritative)
Sempron 64 (Sparta/256K)
65 nm
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 pni cx16 syscall mmxext 3dnow 3dnowext nx fxsr_opt rdtscp lm lahf_lm 3dnowprefetch ts fid vid ttp tm_amd stc 100mhzsteps

1
tests/amd/k8/turion-64-lancaster.test
View file

@ -99,4 +99,5 @@ general
-1
64 (non-authoritative)
Turion 64 (Lancaster/1024K)
90 nm
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 pni syscall mmxext 3dnow 3dnowext nx fxsr_opt lm lahf_lm ts fid vid ttp tm_amd stc

1
tests/amd/zen+/ryzen5-picasso.test
View file

@ -75,4 +75,5 @@ general
-1
128 (authoritative)
Ryzen 5 (Picasso)
GF 12LP
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen+/ryzen7-pinnacle-ridge.test
View file

@ -75,4 +75,5 @@ general
-1
128 (authoritative)
Ryzen 7 (Pinnacle Ridge)
GF 12LP
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen+/threadripper-colfax.test
View file

@ -75,4 +75,5 @@ general
-1
128 (authoritative)
Threadripper (Colfax)
GF 12LP
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen/dali.test
View file

@ -133,4 +133,5 @@ general
-1
128 (authoritative)
Dali
GF 14LP
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen/epyc-naples.test
View file

@ -75,4 +75,5 @@ general
-1
128 (authoritative)
EPYC (Naples)
GF 14LP
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen/ryzen3-raven-ridge.test
View file

@ -107,4 +107,5 @@ general
-1
128 (authoritative)
Ryzen 3 (Raven Ridge)
GF 14LP
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen/ryzen5-raven-ridge.test
View file

@ -75,4 +75,5 @@ general
-1
128 (authoritative)
Ryzen 5 (Raven Ridge)
GF 14LP
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen/ryzen5-summit-ridge.test
View file

@ -75,4 +75,5 @@ general
-1
128 (authoritative)
Ryzen 5 (Summit Ridge)
GF 14LP
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen/ryzen7-summit-ridge.test
View file

@ -103,4 +103,5 @@ general
-1
128 (authoritative)
Ryzen 7 (Summit Ridge)
GF 14LP
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen/threadripper-whitehaven.test
View file

@ -75,4 +75,5 @@ general
-1
128 (authoritative)
Threadripper (Whitehaven)
GF 14LP
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen2/4700s.test
View file

@ -991,4 +991,5 @@ general
0
256 (authoritative)
Desktop Kit (Zen 2)
TSMC N7FF
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen2/4800s.test
View file

@ -1007,4 +1007,5 @@ general
0
256 (authoritative)
Desktop Kit (Zen 2)
TSMC N7FF
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

BIN
tests/amd/zen2/epyc-rome-dual.test.xz
View file

Binary file not shown.

BIN
tests/amd/zen2/epyc-rome.test.xz
View file

Binary file not shown.

1
tests/amd/zen2/ryzen3-mendocino.test
View file

@ -503,4 +503,5 @@ general
0
256 (authoritative)
Ryzen 3 (Mendocino)
TSMC N6
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand x2apic cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen2/ryzen5-lucienne.test
View file

@ -751,4 +751,5 @@ general
0
256 (authoritative)
Ryzen 5 (Lucienne)
TSMC N7FF
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen2/ryzen5-matisse.test
View file

@ -1003,4 +1003,5 @@ general
0
256 (authoritative)
Ryzen 5 (Matisse)
TSMC N7FF
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand x2apic cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen2/ryzen5-mendocino.test
View file

@ -503,4 +503,5 @@ general
0
256 (authoritative)
Ryzen 5 (Mendocino)
TSMC N6
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand x2apic cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen2/ryzen5-renoir.test
View file

@ -391,4 +391,5 @@ general
-1
256 (authoritative)
Ryzen 5 (Renoir)
TSMC N7FF
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen2/ryzen7-lucienne.test
View file

@ -111,4 +111,5 @@ general
-1
256 (authoritative)
Ryzen 7 (Lucienne)
TSMC N7FF
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen2/ryzen7-matisse.test
View file

@ -991,4 +991,5 @@ general
0
256 (authoritative)
Ryzen 7 (Matisse)
TSMC N7FF
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen2/ryzen7-renoir.test
View file

@ -991,4 +991,5 @@ general
0
256 (authoritative)
Ryzen 7 (Renoir)
TSMC N7FF
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen2/ryzen9-matisse.test
View file

@ -1471,4 +1471,5 @@ general
0
256 (authoritative)
Ryzen 9 (Matisse)
TSMC N7FF
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

BIN
tests/amd/zen2/threadripper-castle-peak.test.xz
View file

Binary file not shown.

1
tests/amd/zen2/van-gogh-custom-0405.test
View file

@ -527,4 +527,5 @@ general
0
256 (authoritative)
Van Gogh
TSMC N7FF
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen2/van-gogh-custom-0932.test
View file

@ -519,4 +519,5 @@ general
0
256 (authoritative)
Van Gogh
TSMC N7FF
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

BIN
tests/amd/zen3/epyc-milan.test.xz
View file

Binary file not shown.

1
tests/amd/zen3/ryzen5-vermeer.test
View file

@ -823,4 +823,5 @@ general
0
256 (authoritative)
Ryzen 5 (Vermeer)
TSMC N7FF
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand x2apic cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen3/ryzen7-cezanne.test
View file

@ -1055,4 +1055,5 @@ general
0
256 (authoritative)
Ryzen 7 (Cezanne)
TSMC N7FF
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen3/ryzen7-rembrandt-r.test
View file

@ -1055,4 +1055,5 @@ general
0
256 (authoritative)
Ryzen 7 (Rembrandt-R)
TSMC N6
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand x2apic cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen3/ryzen7-rembrandt.test
View file

@ -1103,4 +1103,5 @@ general
0
256 (authoritative)
Ryzen 7 (Rembrandt)
TSMC N6
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand x2apic cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen3/ryzen7-vermeer.test
View file

@ -1087,4 +1087,5 @@ general
0
256 (authoritative)
Ryzen 7 (Vermeer)
TSMC N7FF
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand x2apic cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen3/ryzen9-cezanne.test
View file

@ -1071,4 +1071,5 @@ general
0
256 (authoritative)
Ryzen 9 (Cezanne)
TSMC N7FF
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen3/ryzen9-rembrandt.test
View file

@ -1055,4 +1055,5 @@ general
0
256 (authoritative)
Ryzen 9 (Rembrandt)
TSMC N6
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand x2apic cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

1
tests/amd/zen3/ryzen9-vermeer.test
View file

@ -2015,4 +2015,5 @@ general
0
256 (authoritative)
Ryzen 9 (Vermeer)
TSMC N7FF
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand cpb aperfmperf avx2 bmi1 bmi2 sha_ni rdseed adx

BIN
tests/amd/zen4/epyc-genoa.test.xz
View file

Binary file not shown.

1
tests/amd/zen4/ryzen-z1-phoenix.test
View file

@ -1003,4 +1003,5 @@ general
0
256 (authoritative)
Ryzen Z1 (Phoenix)
TSMC N4
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand x2apic cpb aperfmperf avx2 bmi1 bmi2 avx512f avx512dq avx512cd sha_ni avx512bw avx512vl rdseed adx avx512vnni avx512vbmi avx512vbmi2

1
tests/amd/zen4/ryzen5-raphael.test
View file

@ -979,4 +979,5 @@ general
0
256 (authoritative)
Ryzen 5 (Raphael)
TSMC N5
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand x2apic cpb aperfmperf avx2 bmi1 bmi2 avx512f avx512dq avx512cd sha_ni avx512bw avx512vl rdseed adx avx512vnni avx512vbmi avx512vbmi2

1
tests/amd/zen4/ryzen7-hawk-point.test
View file

@ -1327,4 +1327,5 @@ general
0
256 (authoritative)
Ryzen 7 (Hawk Point)
TSMC N4
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand x2apic cpb aperfmperf avx2 bmi1 bmi2 avx512f avx512dq avx512cd sha_ni avx512bw avx512vl rdseed adx avx512vnni avx512vbmi avx512vbmi2

1
tests/amd/zen4/ryzen7-phoenix-g.test
View file

@ -1295,4 +1295,5 @@ general
0
256 (authoritative)
Ryzen 7 (Phoenix)
TSMC N4
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand cpb aperfmperf avx2 bmi1 bmi2 avx512f avx512dq avx512cd sha_ni avx512bw avx512vl rdseed adx avx512vnni avx512vbmi avx512vbmi2

1
tests/amd/zen4/ryzen7-raphael.test
View file

@ -1311,4 +1311,5 @@ general
0
256 (authoritative)
Ryzen 7 (Raphael)
TSMC N5
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand cpb aperfmperf avx2 bmi1 bmi2 avx512f avx512dq avx512cd sha_ni avx512bw avx512vl rdseed adx avx512vnni avx512vbmi avx512vbmi2

1
tests/amd/zen4/ryzen9-phoenix-h.test
View file

@ -1311,4 +1311,5 @@ performance
0
256 (authoritative)
Ryzen 9 (Phoenix)
TSMC N4
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand x2apic cpb aperfmperf avx2 bmi1 bmi2 avx512f avx512dq avx512cd sha_ni avx512bw avx512vl rdseed adx avx512vnni avx512vbmi avx512vbmi2

1
tests/amd/zen4/ryzen9-raphael.test
View file

@ -1927,4 +1927,5 @@ general
0
256 (authoritative)
Ryzen 9 (Raphael)
TSMC N5
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand x2apic cpb aperfmperf avx2 bmi1 bmi2 avx512f avx512dq avx512cd sha_ni avx512bw avx512vl rdseed adx avx512vnni avx512vbmi avx512vbmi2

BIN
tests/amd/zen4/threadripper-pro-storm-peak.test.xz
View file

Binary file not shown.

BIN
tests/amd/zen5/epyc-turin-dense.test.xz
View file

Binary file not shown.

BIN
tests/amd/zen5/epyc-turin.test.xz
View file

Binary file not shown.

1
tests/amd/zen5/ryzen7-granite-ridge.test
View file

@ -1327,4 +1327,5 @@ general
0
64 (authoritative)
Ryzen 7 (Granite Ridge)
TSMC N4
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand cpb aperfmperf avx2 bmi1 bmi2 avx512f avx512dq avx512cd sha_ni avx512bw avx512vl rdseed adx avx512vnni avx512vbmi avx512vbmi2

1
tests/amd/zen5/ryzen9-granite-ridge.test
View file

@ -2623,4 +2623,5 @@ general
0
64 (authoritative)
Ryzen 9 (Granite Ridge)
TSMC N4
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht pni pclmul monitor ssse3 cx16 sse4_1 sse4_2 syscall movbe popcnt aes xsave osxsave avx mmxext nx fxsr_opt rdtscp lm lahf_lm cmp_legacy svm abm misalignsse sse4a 3dnowprefetch osvw ibs skinit wdt ts ttp tm_amd hwpstate constant_tsc fma3 f16c rdrand cpb aperfmperf avx2 bmi1 bmi2 avx512f avx512dq avx512cd sha_ni avx512bw avx512vl rdseed adx avx512vnni avx512vbmi avx512vbmi2

2
tests/arm/armv7a/cortex-a15-qemu.txt → tests/arm/armv7a/cortex-a15-qemu.test
View file

@ -160,6 +160,7 @@ arm_id_aa64smfr0=0000000000000000
arm_id_aa64zfr0=0000000000000000
--------------------------------------------------------------------------------
ARM
ARMv7-A
general
65
4
@ -168,4 +169,5 @@ general
4
4
Eagle
32-20 nm
advmultu advmults jazelle thumb2 debugv7p1 thumbee divide lpae

2
tests/arm/armv7a/cortex-a7-qemu.txt → tests/arm/armv7a/cortex-a7-qemu.test
View file

@ -160,6 +160,7 @@ arm_id_aa64smfr0=0000000000000000
arm_id_aa64zfr0=0000000000000000
--------------------------------------------------------------------------------
ARM
ARMv7-A
general
65
0
@ -168,4 +169,5 @@ general
4
4
Kingfisher
40-28 nm
advmultu advmults jazelle thumb2 debugv7p1 thumbee divide lpae

1
tests/arm/armv8a/cortex-a53.test
View file

@ -85,4 +85,5 @@ efficiency
1
4
Apollo
28-10 nm
advsimd crc32 doublelock fp bbm

1
tests/arm/armv8a/cortex-a57-qemu.test
View file

@ -85,4 +85,5 @@ performance
1
4
Atlas
28-14 nm
advsimd crc32 doublelock fp pmull sha1 sha256 bbm

1
tests/arm/armv8a/cortex-a72.test
View file

@ -169,4 +169,5 @@ performance
4
4
Maia
28-16 nm
advmultu advmults jazelle thumb2 divide lpae crc32

1
tests/arm/armv9a/neoverse-n2-qemu.test
View file

@ -85,4 +85,5 @@ general
1
4
Perseus
5 nm
advsimd crc32 doublelock pmull sha1 lse rdm fp16 i8mm sha3 sha512 sm3 sm4 sve fcma fpaccombine jscvt pacqarma5 pauth bbm dit dotprod fhm lrcpc2 lse2 bti dpb2 frintts flagm2 mte rng sb ssbs2 bf16 dgh sve2 sve_bitperm sve_pmull128 sve_sha3 sve_sm4

3
tests/create_test.py
View file

@ -65,6 +65,9 @@ def readResultFile():
if field == "code name":
value = s[s.find("`") + 1: s.find("'")]
repdata.append(value)
if field == "technology":
value = s[s.find("`") + 1: s.find("'")]
repdata.append(value)
if field == "features":
value = s[s.find(":") + 2:]
repdata.append(value)

Some files were not shown because too many files have changed in this diff Show more