mirror of
https://github.com/anrieff/libcpuid
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102 lines
6.3 KiB
C
102 lines
6.3 KiB
C
/*
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* Copyright 2023 Veselin Georgiev,
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* anrieffNOSPAM @ mgail_DOT.com (convert to gmail)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdio.h>
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#include <string.h>
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#include <ctype.h>
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#include "libcpuid.h"
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#include "libcpuid_util.h"
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#include "libcpuid_internal.h"
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#include "recog_centaur.h"
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const struct match_entry_t cpudb_centaur[] = {
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// F M S EF EM #cores L2$ L3$ Pattern Codename Technology
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{ -1, -1, -1, -1, -1, -1, -1, -1, { "", 0 }, "Unknown Centaur CPU", "" },
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// F M S EF EM #cores L2$ L3$ Pattern Codename Technology
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/* VIA */
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// F M S EF EM #cores L2$ L3$ Pattern Codename Technology
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{ 6, -1, -1, -1, -1, -1, -1, -1, { "VIA", 2 }, "Unknown VIA CPU", "" },
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/* Samuel (2000, 180 nm) */
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{ 6, 6, -1, -1, -1, -1, -1, -1, { "VIA Samuel", 4 }, "VIA Cyrix III (Samuel)", "180 nm" },
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/* Samuel 2 (2001, 150 nm) */
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{ 6, 7, -1, -1, -1, -1, -1, -1, { "VIA Samuel 2", 6 }, "VIA C3 (Samuel 2)", "150 nm" },
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/* Ezra (2001, 130 nm) */
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{ 6, 7, -1, -1, -1, -1, -1, -1, { "VIA Ezra", 4 }, "VIA C3 (Ezra)", "130 nm" },
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{ 6, 8, -1, -1, -1, -1, -1, -1, { "VIA C3 Ezra", 6 }, "VIA C3 (Ezra-T)", "130 nm" },
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/* Nehemiah (2003, 130 nm) */
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{ 6, 9, -1, -1, -1, -1, -1, -1, { "VIA Nehemiah", 4 }, "VIA C3 (Nehemiah)", "130 nm" },
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/* Esther (2005, 90 nm) */
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{ 6, 10, -1, -1, -1, -1, -1, -1, { "VIA Esther", 4 }, "VIA C7 (Esther)", "90 nm" },
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{ 6, 13, -1, -1, -1, -1, -1, -1, { "VIA C7-M", 4 }, "VIA C7-M (Esther)", "90 nm" },
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/* Isaiah (2008, 65 nm) */
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{ 6, 15, -1, -1, -1, -1, -1, -1, { "VIA Nano", 4 }, "VIA Nano (Isaiah)", "65 nm" },
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{ 6, 15, -1, -1, -1, 1, -1, -1, { "VIA Nano", 4 }, "VIA Nano (Isaiah)", "65 nm" },
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{ 6, 15, -1, -1, -1, 2, -1, -1, { "VIA Nano", 4 }, "VIA Nano X2 (Isaiah)", "65 nm" },
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{ 6, 15, -1, -1, -1, -1, -1, -1, { "VIA QuadCore", 4 }, "VIA Nano X4 (Isaiah)", "65 nm" },
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{ 6, 15, -1, -1, -1, 4, -1, -1, { "VIA Eden X4", 6 }, "VIA Eden X4 (Isaiah)", "65 nm" },
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// F M S EF EM #cores L2$ L3$ Pattern Codename Technology
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/* Zhaoxin */
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// F M S EF EM #cores L2$ L3$ Pattern Codename Technology
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{ 7, -1, -1, -1, -1, -1, -1, -1, {"ZHAOXIN", 2 }, "Unknown Zhaoxin CPU" "" },
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/* Zhangjiang (2015, 28 nm) */
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{ 7, -1, -1, -1, 15, -1, -1, -1, { "ZHAOXIN KaisHeng KH-C", 8 }, "Zhaoxin KaisHeng (ZhangJiang)", "28 nm" }, // C+ (4000)
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{ 7, -1, -1, -1, 15, -1, -1, -1, { "ZHAOXIN KaiXian ZX-C", 8 }, "Zhaoxin KaiXian (ZhangJiang)", "28 nm" }, // C/C+ (4000)
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/* WuDaoKou (2017, 28 nm) */
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{ 7, -1, -1, -1, 27, -1, -1, -1, { "ZHAOXIN KaisHeng KH-20###", 8 }, "Zhaoxin KaisHeng (WuDaoKou)", "28 nm" }, // KH (20000)
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{ 7, -1, -1, -1, 27, -1, -1, -1, { "ZHAOXIN KaiXian KX-5###", 8 }, "Zhaoxin KaiXian (WuDaoKou)", "28 nm" }, // KX (5000)
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{ 7, -1, -1, -1, 27, -1, -1, -1, { "ZHAOXIN KaiXian KX-U5###", 8 }, "Zhaoxin KaiXian (WuDaoKou)", "28 nm" }, // KX (U5000)
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/* LuJiaZui (2019, 16 nm) */
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{ 7, -1, -1, -1, 59, -1, -1, -1, { "ZHAOXIN KaisHeng KH-30###", 8 }, "Zhaoxin KaisHeng (LuJiaZui)", "16 nm" }, // KH (30000)
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{ 7, -1, -1, -1, 59, -1, -1, -1, { "ZHAOXIN KaiXian KX-6###", 8 }, "Zhaoxin KaiXian (LuJiaZui)", "16 nm" }, // KX (6000)
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{ 7, -1, -1, -1, 59, -1, -1, -1, { "ZHAOXIN KaiXian KX-U6###", 8 }, "Zhaoxin KaiXian (LuJiaZui)", "16 nm" }, // KX (U6000)
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/* Yongfeng (2022, 16 nm) */
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{ 7, -1, -1, -1, 91, -1, -1, -1, { "ZHAOXIN KaisHeng KH-40###", 8 }, "Zhaoxin KaisHeng (Yongfeng)", "16 nm" }, // KH (40000)
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{ 7, -1, -1, -1, 91, -1, -1, -1, { "ZHAOXIN KaiXian KX-7###", 8 }, "Zhaoxin KaiXian (Yongfeng)", "16 nm" }, // KX (7000)
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// F M S EF EM #cores L2$ L3$ Pattern Codename Technology
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};
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int cpuid_identify_centaur(struct cpu_raw_data_t* raw, struct cpu_id_t* data, struct internal_id_info_t* internal)
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{
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if (raw->basic_cpuid[0][EAX] >= 4)
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decode_deterministic_cache_info_x86(raw->intel_fn4, MAX_INTELFN4_LEVEL, data, internal);
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decode_number_of_cores_x86(raw, data);
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decode_architecture_version_x86(data);
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internal->score = match_cpu_codename(cpudb_centaur, COUNT_OF(cpudb_centaur), data);
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return 0;
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}
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void cpuid_get_list_centaur(struct cpu_list_t* list)
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{
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generic_get_cpu_list(cpudb_centaur, COUNT_OF(cpudb_centaur), list);
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}
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