mirror/libcpuid
1
0
Fork 0
mirror of https://github.com/anrieff/libcpuid synced 2024-12-16 16:35:45 +00:00
Code Issues Releases Wiki Activity

DB: add Intel Ice-Lake (server)

Browse source
This commit is contained in:
The Tumultuous Unicorn Of Darkness 2023-05-08 17:09:29 +02:00
parent 01ec8df7cb
commit 3411fe6fe5
No known key found for this signature in database
GPG key ID: 1E55EE2EFF18BC1A
2 changed files with 10 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
libcpuid/recog_intel.c
View file

@ -422,10 +422,18 @@ const struct match_entry_t cpudb_intel[] = {
{ 6, 14, 12, -1, 142, 4, -1, -1, NC, CORE_|_I_|_5 ,_10xxx, "Comet Lake-U (Core i5)" }, { 6, 14, 12, -1, 142, 4, -1, -1, NC, CORE_|_I_|_5 ,_10xxx, "Comet Lake-U (Core i5)" },
{ 6, 14, 12, -1, 142, 2, -1, -1, NC, PENTIUM_ ,_10xxx, "Comet Lake-U (Pentium)" }, { 6, 14, 12, -1, 142, 2, -1, -1, NC, PENTIUM_ ,_10xxx, "Comet Lake-U (Pentium)" },
{ 6, 14, 12, -1, 142, 2, -1, -1, NC, CELERON_ ,_10xxx, "Comet Lake-U (Celeron)" }, { 6, 14, 12, -1, 142, 2, -1, -1, NC, CELERON_ ,_10xxx, "Comet Lake-U (Celeron)" },
{ 6, 12, -1, -1, 108, 4, -1, -1, NC, XEON_ , 0, "Ice Lake (Xeon-D)" },
/* Ice Lake (client) CPUs (2019, 10th Core i gen, 10nm) => https://en.wikichip.org/wiki/intel/microarchitectures/ice_lake_(client) */
{ 6, 14, -1, -1, 126, 4, -1, -1, NC, CORE_|_I_|_7 ,_10xxx, "Ice Lake (Core i7)" }, { 6, 14, -1, -1, 126, 4, -1, -1, NC, CORE_|_I_|_7 ,_10xxx, "Ice Lake (Core i7)" },
{ 6, 14, -1, -1, 126, 4, -1, -1, NC, CORE_|_I_|_5 ,_10xxx, "Ice Lake (Core i5)" }, { 6, 14, -1, -1, 126, 4, -1, -1, NC, CORE_|_I_|_5 ,_10xxx, "Ice Lake (Core i5)" },
{ 6, 14, -1, -1, 126, 2, -1, -1, NC, CORE_|_I_|_3 ,_10xxx, "Ice Lake (Core i3)" }, { 6, 14, -1, -1, 126, 2, -1, -1, NC, CORE_|_I_|_3 ,_10xxx, "Ice Lake (Core i3)" },
/* Ice Lake (server) CPUs (2021, 3rd Xeon Scalable gen, 10nm) => https://en.wikichip.org/wiki/intel/microarchitectures/ice_lake_(server) */
{ 6, 12, -1, -1, 108, 4, -1, -1, NC, XEON_ , 0, "Ice Lake-D (Xeon-D)" },
{ 6, 10, -1, -1, 106, -1, -1, -1, NC, XEON_|_W_ , _x3xx, "Ice Lake-W (Xeon W)" },
{ 6, 10, -1, -1, 106, -1, -1, -1, NC, XEON_|_PLATINIUM_, _x3xx, "Ice Lake-SP (Xeon Platinum)" },
{ 6, 10, -1, -1, 106, -1, -1, -1, NC, XEON_|_GOLD_, _x3xx, "Ice Lake-SP (Xeon Gold)" },
{ 6, 10, -1, -1, 106, -1, -1, -1, NC, XEON_|_SILVER_, _x3xx, "Ice Lake-SP (Xeon Silver)" },
{ 6, 10, -1, -1, 106, -1, -1, -1, NC, XEON_|_BRONZE_, _x3xx, "Ice Lake-SP (Xeon Bronze)" },
/* Rocket Lake CPUs (11th gen, 14nm): */ /* Rocket Lake CPUs (11th gen, 14nm): */
{ 6, 7, -1, -1, 167, -1, -1, -1, NC, CORE_|_I_|_9 ,_11xxx, "Rocket Lake (Core i9)" }, { 6, 7, -1, -1, 167, -1, -1, -1, NC, CORE_|_I_|_9 ,_11xxx, "Rocket Lake (Core i9)" },

2
tests/intel/core_10th_gen/ice-lake-xeon-d.test → tests/intel/sunny-cove/ice-lake-d-xeon-d.test
View file

@ -541,5 +541,5 @@ general
1 1
0 0
128 (non-authoritative) 128 (non-authoritative)
Ice Lake (Xeon-D) Ice Lake-D (Xeon-D)
fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 syscall xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm avx512f avx512dq avx512cd sha_ni avx512bw avx512vl rdseed adx avx512vnni avx512vbmi avx512vbmi2 hypervisor fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 syscall xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 hle rtm avx512f avx512dq avx512cd sha_ni avx512bw avx512vl rdseed adx avx512vnni avx512vbmi avx512vbmi2 hypervisor