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https://github.com/anrieff/libcpuid
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DB: add more AMD Zen 4 CPUs
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parent
09071d20f3
commit
5b63e27dc8
3 changed files with 35 additions and 23 deletions
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@ -119,6 +119,10 @@ enum _common_bits_t {
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_5 = LBIT( 4 ),
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_7 = LBIT( 5 ),
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_9 = LBIT( 6 ),
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_H = LBIT( 7 ),
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_S = LBIT( 8 ),
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_U = LBIT( 9 ),
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_X = LBIT( 10 ),
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};
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// additional detection bits for Intel CPUs:
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@ -129,19 +133,16 @@ enum _intel_bits_t {
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_I_ = LBIT( 13 ),
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XEON_ = LBIT( 14 ),
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ATOM_ = LBIT( 15 ),
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_H = LBIT( 16 ),
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_K = LBIT( 17 ),
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_X = LBIT( 18 ),
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_P = LBIT( 19 ),
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_N = LBIT( 20 ),
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_W_ = LBIT( 21 ),
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_D_ = LBIT( 22 ),
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_BRONZE_ = LBIT( 23 ),
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_SILVER_ = LBIT( 24 ),
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_GOLD_ = LBIT( 25 ),
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_PLATINIUM_ = LBIT( 26 ),
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_MAX_ = LBIT( 27 ),
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_U = LBIT( 28 ),
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_K = LBIT( 16 ),
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_P = LBIT( 17 ),
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_N = LBIT( 18 ),
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_W_ = LBIT( 19 ),
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_D_ = LBIT( 20 ),
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_BRONZE_ = LBIT( 21 ),
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_SILVER_ = LBIT( 22 ),
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_GOLD_ = LBIT( 23 ),
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_PLATINIUM_ = LBIT( 24 ),
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_MAX_ = LBIT( 25 ),
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};
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typedef enum _intel_bits_t intel_bits_t;
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@ -353,14 +353,15 @@ const struct match_entry_t cpudb_amd[] = {
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{ 15, -1, 2, 25, 97, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Raphael)" },
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{ 15, -1, 2, 25, 97, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Raphael)" },
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{ 15, -1, 2, 25, 97, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Raphael)" },
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//{ 15, -1, -1, 25, ??, -1, -1, -1, NC, RYZEN_|_9 , 0, "Ryzen 9 (Dragon Range)" },
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//{ 15, -1, -1, 25, ??, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Dragon Range)" },
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//{ 15, -1, -1, 25, ??, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Dragon Range)" },
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//{ 15, -1, -1, 25, ??, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Dragon Range)" },
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{ 15, -1, -1, 25, 116, -1, -1, -1, NC, RYZEN_|_9 , 0, "Ryzen 9 (Phoenix)" },
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{ 15, -1, -1, 25, 116, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Phoenix)" },
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{ 15, -1, -1, 25, 116, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Phoenix)" },
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{ 15, -1, -1, 25, 116, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Phoenix)" },
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{ 15, -1, -1, 25, 97, -1, -1, -1, NC, RYZEN_|_9|_H , 0, "Ryzen 9 (Dragon Range)" },
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{ 15, -1, -1, 25, 97, -1, -1, -1, NC, RYZEN_|_7|_H , 0, "Ryzen 7 (Dragon Range)" },
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{ 15, -1, -1, 25, 97, -1, -1, -1, NC, RYZEN_|_5|_H , 0, "Ryzen 5 (Dragon Range)" },
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{ 15, -1, -1, 25, 116, -1, -1, -1, NC, RYZEN_|_9|_H , 0, "Ryzen 9 (Phoenix)" },
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{ 15, -1, -1, 25, 116, -1, -1, -1, NC, RYZEN_|_7|_H , 0, "Ryzen 7 (Phoenix)" },
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{ 15, -1, -1, 25, 116, -1, -1, -1, NC, RYZEN_|_7|_U , 0, "Ryzen 7 (Phoenix)" },
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{ 15, -1, -1, 25, 116, -1, -1, -1, NC, RYZEN_|_5|_H , 0, "Ryzen 5 (Phoenix)" },
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{ 15, -1, -1, 25, 116, -1, -1, -1, NC, RYZEN_|_5|_U , 0, "Ryzen 5 (Phoenix)" },
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{ 15, -1, -1, 25, 116, -1, -1, -1, NC, RYZEN_|_3|_U , 0, "Ryzen 3 (Phoenix)" },
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/* F M S EF EM #cores L2$ L3$ BC ModelBits ModelCode Name */
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};
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@ -520,6 +521,7 @@ static struct amd_code_and_bits_t decode_amd_codename_part1(const char *bs)
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struct amd_code_and_bits_t result;
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uint64_t bits = 0;
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int i = 0;
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const size_t n = strlen(bs);
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const struct { amd_code_t c; const char *search; } code_matchtable[] = {
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{ PHENOM2, "Phenom(tm) II" },
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@ -574,6 +576,14 @@ static struct amd_code_and_bits_t decode_amd_codename_part1(const char *bs)
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case '7': bits |= _7; break;
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case '9': bits |= _9; break;
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}
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for(i = i + 7; i < n; i++) {
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switch (bs[i]) {
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case 'H': bits |= _H; break;
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case 'S': bits |= _S; break;
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case 'U': bits |= _U; break;
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case 'X': bits |= _X; break;
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}
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}
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}
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if ((i = match_pattern(bs, "C86 [357]")) != 0) {
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@ -771,10 +771,11 @@ static intel_code_and_bits_t get_brand_code_and_bits(struct cpu_id_t* data)
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switch (bs[i]) {
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case 'H': bits |= _H; break;
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case 'K': bits |= _K; break;
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case 'X': bits |= _X; break;
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case 'P': bits |= _P; break;
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case 'N': bits |= _N; break;
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case 'P': bits |= _P; break;
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case 'S': bits |= _S; break;
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case 'U': bits |= _U; break;
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case 'X': bits |= _X; break;
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}
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}
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}
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