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RDMSR: check if MSR_PERF_STATUS/MSR_TEMPERATURE_TARGET/MSR_PLATFORM_INFO are supported
Fix #185
This commit is contained in:
The Tumultuous Unicorn Of Darkness
parent
0dae8b8d92
commit
ac57f69275
1 changed files with 201 additions and 4 deletions
205
libcpuid/rdmsr.c
205
libcpuid/rdmsr.c
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@ -646,6 +646,203 @@ static int perfmsr_measure(struct msr_driver_t* handle, int msr)
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return (int) ((y - x) / (b - a));
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}
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static int msr_platform_info_supported(struct msr_info_t *info)
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{
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int i;
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static int supported = -1;
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/* Return cached result */
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if(supported >= 0)
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return supported;
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/* List of microarchitectures that provide both "Maximum Non-Turbo Ratio" and "Maximum Efficiency Ratio" values
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Please note Silvermont does not report "Maximum Efficiency Ratio" */
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const struct { int32_t ext_family; int32_t ext_model; } msr_platform_info[] = {
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/* Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture */
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{ 6, 92 },
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{ 6, 122 },
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/* Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture */
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{ 6, 26 },
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{ 6, 30 },
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{ 6, 37 },
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{ 6, 44 },
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/* Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture */
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{ 6, 42 },
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{ 6, 45 },
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/* Table 2-25. Additional MSRs Supported by 3rd Generation Intel® CoreTM Processors Based on Ivy Bridge Microarchitecture */
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{ 6, 58 },
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/* Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture) */
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{ 6, 62 },
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/* Table 2-29. Additional MSRs Supported by Processors Based on the Haswell and Haswell-E Microarchitectures */
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{ 6, 60 },
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{ 6, 63 },
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{ 6, 69 },
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{ 6, 70 },
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/* Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family Based on Broadwell Microarchitecture */
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{ 6, 61 },
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{ 6, 71 },
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{ 6, 79 },
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/* Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® CoreTM Processors, 1st—5th Generation Intel® Xeon® Scalable Processor Families, Intel® CoreTM Ultra 7 Processors, 8th Generation Intel® CoreTM i3 Processors, and Intel® Xeon® E Processors */
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/* ==> Skylake */
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{ 6, 78 },
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{ 6, 85 },
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{ 6, 94 },
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/* ==> Kaby Lake */
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{ 6, 142 },
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{ 6, 158 },
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/* ==> Coffee Lake */
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{ 6, 102 },
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{ 6, 142 },
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{ 6, 158 },
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/* ==> Cascade Lake */
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{ 6, 85 },
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/* ==> Comet Lake */
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{ 6, 142 },
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{ 6, 165 },
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/* ==> Ice Lake */
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{ 6, 106 },
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{ 6, 108 },
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{ 6, 126 },
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/* ==> Rocket Lake */
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{ 6, 167 },
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/* ==> Tremont */
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{ 6, 138 },
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{ 6, 150 },
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{ 6, 156 },
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/* ==> Tiger Lake */
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{ 6, 140 },
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/* ==> Alder Lake */
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{ 6, 151 },
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{ 6, 154 },
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{ 6, 190 },
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/* ==> Raptor Lake */
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{ 6, 183 },
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{ 6, 186 },
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{ 6, 191 },
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/* ==> Sapphire Rapids */
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{ 6, 143 },
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/* ==> Emerald Rapids */
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{ 6, 207 },
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/* ==> Meteor Lake */
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{ 6, 170 },
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/* Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature DisplayFamily_DisplayModel Value of 06_55H */
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{ 0x6, 0x55 },
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/* Table 2-56. Selected MSRs Supported by Intel® Xeon PhiTM Processors with a CPUID Signature DisplayFamily_DisplayModel Value of 06_57H or 06_85H */
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{ 0x6, 0x57 },
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{ 0x6, 0x85 },
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};
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if(info->id->vendor == VENDOR_INTEL) {
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for(i = 0; i < COUNT_OF(msr_platform_info); i++) {
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if((info->id->ext_family == msr_platform_info[i].ext_family) && (info->id->ext_model == msr_platform_info[i].ext_model)) {
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debugf(2, "Intel CPU with CPUID signature %02X_%02XH supports MSR_PLATFORM_INFO.\n", info->id->ext_family, info->id->ext_model);
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supported = 1;
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return supported;
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}
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}
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debugf(2, "Intel CPU with CPUID signature %02X_%02XH does not support MSR_PLATFORM_INFO.\n", info->id->ext_family, info->id->ext_model);
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}
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supported = 0;
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return supported;
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}
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static int msr_temperature_target_supported(struct msr_info_t *info)
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{
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/* It seems MSR_TEMPERATURE_TARGET was added with MSR_PLATFORM_INFO, i.e. since "Intel Core ix" CPUs */
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return msr_platform_info_supported(info);
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}
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static int msr_perf_status_supported(struct msr_info_t *info)
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{
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int i;
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static int supported = -1;
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/* Return cached result */
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if(supported >= 0)
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return supported;
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/* List of microarchitectures that provide "Core Voltage" values */
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const struct { int32_t ext_family; int32_t ext_model; } msr_perf_status[] = {
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/* Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture */
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{ 6, 42 },
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{ 6, 45 },
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/* ==> Ivy Bridge */
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{ 6, 58 },
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{ 6, 62 },
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/* ==> Haswell */
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{ 6, 60 },
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{ 6, 63 },
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{ 6, 69 },
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{ 6, 70 },
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/* ==> Broadwell */
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{ 6, 61 },
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{ 6, 71 },
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{ 6, 79 },
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/* ==> Skylake */
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{ 6, 78 },
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{ 6, 85 },
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{ 6, 94 },
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/* ==> Kaby Lake */
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{ 6, 142 },
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{ 6, 158 },
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/* ==> Coffee Lake */
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{ 6, 102 },
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{ 6, 142 },
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{ 6, 158 },
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/* ==> Cascade Lake */
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{ 6, 85 },
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/* ==> Comet Lake */
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{ 6, 142 },
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{ 6, 165 },
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/* ==> Ice Lake */
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{ 6, 106 },
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{ 6, 108 },
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{ 6, 126 },
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/* ==> Rocket Lake */
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{ 6, 167 },
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/* ==> Tremont */
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{ 6, 138 },
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{ 6, 150 },
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{ 6, 156 },
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/* ==> Tiger Lake */
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{ 6, 140 },
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/* ==> Alder Lake */
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{ 6, 151 },
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{ 6, 154 },
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{ 6, 190 },
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/* ==> Raptor Lake */
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{ 6, 183 },
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{ 6, 186 },
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{ 6, 191 },
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/* ==> Sapphire Rapids */
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{ 6, 143 },
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/* ==> Emerald Rapids */
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{ 6, 207 },
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/* ==> Meteor Lake */
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{ 6, 170 },
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/* Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature DisplayFamily_DisplayModel Value of 06_55H */
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{ 0x6, 0x55 },
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/* Table 2-56. Selected MSRs Supported by Intel® Xeon PhiTM Processors with a CPUID Signature DisplayFamily_DisplayModel Value of 06_57H or 06_85H */
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{ 0x6, 0x57 },
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{ 0x6, 0x85 },
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};
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if(info->id->vendor == VENDOR_INTEL) {
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for(i = 0; i < COUNT_OF(msr_perf_status); i++) {
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if((info->id->ext_family == msr_perf_status[i].ext_family) && (info->id->ext_model == msr_perf_status[i].ext_model)) {
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debugf(2, "Intel CPU with CPUID signature %02X_%02XH supports MSR_PERF_STATUS.\n", info->id->ext_family, info->id->ext_model);
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supported = 1;
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return supported;
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}
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}
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debugf(2, "Intel CPU with CPUID signature %02X_%02XH does not support MSR_PERF_STATUS.\n", info->id->ext_family, info->id->ext_model);
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}
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supported = 0;
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return supported;
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}
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static int get_amd_multipliers(struct msr_info_t *info, uint32_t pstate, double *multiplier)
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{
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int i, err;
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@ -790,7 +987,7 @@ static double get_info_min_multiplier(struct msr_info_t *info)
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uint32_t addr;
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uint64_t reg;
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if(info->id->vendor == VENDOR_INTEL) {
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if(msr_platform_info_supported(info)) {
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/* Refer links above
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Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture
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Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem
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@ -890,7 +1087,7 @@ static int get_info_temperature(struct msr_info_t *info)
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int err;
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uint64_t DigitalReadout, ReadingValid, TemperatureTarget;
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if(info->id->vendor == VENDOR_INTEL) {
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if(msr_temperature_target_supported(info)) {
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/* Refer links above
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Table 35-2. IA-32 Architectural MSRs
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IA32_THERM_STATUS[22:16] is Digital Readout
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@ -918,7 +1115,7 @@ static double get_info_voltage(struct msr_info_t *info)
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double VIDStep;
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uint64_t reg, CpuVid;
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if(info->id->vendor == VENDOR_INTEL) {
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if(msr_perf_status_supported(info)) {
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/* Refer links above
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Table 35-18. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.)
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MSR_PERF_STATUS[47:32] is Core Voltage
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@ -953,7 +1150,7 @@ static double get_info_bus_clock(struct msr_info_t *info)
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uint32_t addr;
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uint64_t reg;
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if(info->id->vendor == VENDOR_INTEL) {
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if(msr_platform_info_supported(info)) {
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/* Refer links above
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Table 35-12. MSRs in Next Generation Intel Atom Processors Based on the Goldmont Microarchitecture
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Table 35-13. MSRs in Processors Based on Intel® Microarchitecture Code Name Nehalem
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