mirror/libcpuid
1
0
Fork 0
mirror of https://github.com/anrieff/libcpuid synced 2025-06-07 00:51:40 +00:00
Code Issues Releases Wiki Activity

Add support for ARMv9.5-A CPUs

Browse source 
New AArch64 registers:
- ID_AA64DFR2_EL1
- ID_AA64FPFR0_EL1
- ID_AA64ISAR3_EL1
This commit is contained in:
The Tumultuous Unicorn Of Darkness 2025-05-01 15:21:29 +02:00
parent 9333f8c0c3
commit ae5b2a24c9
No known key found for this signature in database
GPG key ID: 1E55EE2EFF18BC1A
11 changed files with 365 additions and 15 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
drivers/arm/freebsd/cpuid.c
View file

@ -154,9 +154,12 @@ __read_reg_on_cpu(int cpu, struct read_reg_t *read_reg, u_long cmd, struct threa
case REQ_ID_AA64AFR1: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64AFR1_EL1, read_reg->value_64b); break; case REQ_ID_AA64AFR1: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64AFR1_EL1, read_reg->value_64b); break;
case REQ_ID_AA64DFR0: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64DFR0_EL1, read_reg->value_64b); break; case REQ_ID_AA64DFR0: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64DFR0_EL1, read_reg->value_64b); break;
case REQ_ID_AA64DFR1: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64DFR1_EL1, read_reg->value_64b); break; case REQ_ID_AA64DFR1: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64DFR1_EL1, read_reg->value_64b); break;
case REQ_ID_AA64DFR2: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64DFR2_EL1, read_reg->value_64b); break;
case REQ_ID_AA64FPFR0: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64FPFR0_EL1, read_reg->value_64b); break;
case REQ_ID_AA64ISAR0: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64ISAR0_EL1, read_reg->value_64b); break; case REQ_ID_AA64ISAR0: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64ISAR0_EL1, read_reg->value_64b); break;
case REQ_ID_AA64ISAR1: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64ISAR1_EL1, read_reg->value_64b); break; case REQ_ID_AA64ISAR1: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64ISAR1_EL1, read_reg->value_64b); break;
case REQ_ID_AA64ISAR2: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64ISAR2_EL1, read_reg->value_64b); break; case REQ_ID_AA64ISAR2: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64ISAR2_EL1, read_reg->value_64b); break;
case REQ_ID_AA64ISAR3: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64ISAR3_EL1, read_reg->value_64b); break;
case REQ_ID_AA64MMFR0: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64MMFR0_EL1, read_reg->value_64b); break; case REQ_ID_AA64MMFR0: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64MMFR0_EL1, read_reg->value_64b); break;
case REQ_ID_AA64MMFR1: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64MMFR1_EL1, read_reg->value_64b); break; case REQ_ID_AA64MMFR1: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64MMFR1_EL1, read_reg->value_64b); break;
case REQ_ID_AA64MMFR2: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64MMFR2_EL1, read_reg->value_64b); break; case REQ_ID_AA64MMFR2: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64MMFR2_EL1, read_reg->value_64b); break;

3
drivers/arm/linux/cpuid.c
View file

@ -111,9 +111,12 @@ static void __read_reg_on_cpu(void *info)
case REQ_ID_AA64AFR1: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64AFR1_EL1, read_reg->value_64b); break; case REQ_ID_AA64AFR1: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64AFR1_EL1, read_reg->value_64b); break;
case REQ_ID_AA64DFR0: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64DFR0_EL1, read_reg->value_64b); break; case REQ_ID_AA64DFR0: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64DFR0_EL1, read_reg->value_64b); break;
case REQ_ID_AA64DFR1: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64DFR1_EL1, read_reg->value_64b); break; case REQ_ID_AA64DFR1: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64DFR1_EL1, read_reg->value_64b); break;
case REQ_ID_AA64DFR2: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64DFR2_EL1, read_reg->value_64b); break;
case REQ_ID_AA64FPFR0: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64FPFR0_EL1, read_reg->value_64b); break;
case REQ_ID_AA64ISAR0: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64ISAR0_EL1, read_reg->value_64b); break; case REQ_ID_AA64ISAR0: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64ISAR0_EL1, read_reg->value_64b); break;
case REQ_ID_AA64ISAR1: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64ISAR1_EL1, read_reg->value_64b); break; case REQ_ID_AA64ISAR1: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64ISAR1_EL1, read_reg->value_64b); break;
case REQ_ID_AA64ISAR2: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64ISAR2_EL1, read_reg->value_64b); break; case REQ_ID_AA64ISAR2: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64ISAR2_EL1, read_reg->value_64b); break;
case REQ_ID_AA64ISAR3: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64ISAR3_EL1, read_reg->value_64b); break;
case REQ_ID_AA64MMFR0: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64MMFR0_EL1, read_reg->value_64b); break; case REQ_ID_AA64MMFR0: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64MMFR0_EL1, read_reg->value_64b); break;
case REQ_ID_AA64MMFR1: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64MMFR1_EL1, read_reg->value_64b); break; case REQ_ID_AA64MMFR1: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64MMFR1_EL1, read_reg->value_64b); break;
case REQ_ID_AA64MMFR2: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64MMFR2_EL1, read_reg->value_64b); break; case REQ_ID_AA64MMFR2: cpuid_read_sysreg(NULL, AARCH64_REG_ID_AA64MMFR2_EL1, read_reg->value_64b); break;

57
libcpuid/cpuid_main.c
View file

@ -717,6 +717,8 @@ static int cpuid_serialize_raw_data_internal(struct cpu_raw_data_t* single_raw,
fprintf(f, "arm_id_aa64afr%d=%016" PRIx64 "\n", i, raw_ptr->arm_id_aa64afr[i]); fprintf(f, "arm_id_aa64afr%d=%016" PRIx64 "\n", i, raw_ptr->arm_id_aa64afr[i]);
for (i = 0; i < MAX_ARM_ID_AA64DFR_REGS; i++) for (i = 0; i < MAX_ARM_ID_AA64DFR_REGS; i++)
fprintf(f, "arm_id_aa64dfr%d=%016" PRIx64 "\n", i, raw_ptr->arm_id_aa64dfr[i]); fprintf(f, "arm_id_aa64dfr%d=%016" PRIx64 "\n", i, raw_ptr->arm_id_aa64dfr[i]);
for (i = 0; i < MAX_ARM_ID_AA64FPFR_REGS; i++)
fprintf(f, "arm_id_aa64fpfr%d=%016" PRIx64 "\n", i, raw_ptr->arm_id_aa64fpfr[i]);
for (i = 0; i < MAX_ARM_ID_AA64ISAR_REGS; i++) for (i = 0; i < MAX_ARM_ID_AA64ISAR_REGS; i++)
fprintf(f, "arm_id_aa64isar%d=%016" PRIx64 "\n", i, raw_ptr->arm_id_aa64isar[i]); fprintf(f, "arm_id_aa64isar%d=%016" PRIx64 "\n", i, raw_ptr->arm_id_aa64isar[i]);
for (i = 0; i < MAX_ARM_ID_AA64MMFR_REGS; i++) for (i = 0; i < MAX_ARM_ID_AA64MMFR_REGS; i++)
@ -872,6 +874,9 @@ static int cpuid_deserialize_raw_data_internal(struct cpu_raw_data_t* single_raw
else if ((sscanf(line, "arm_id_aa64dfr%d=%" SCNx64, &i, &aarch64_reg) >= 2)) { else if ((sscanf(line, "arm_id_aa64dfr%d=%" SCNx64, &i, &aarch64_reg) >= 2)) {
RAW_ASSIGN_LINE_AARCH64(raw_ptr->arm_id_aa64dfr[i]); RAW_ASSIGN_LINE_AARCH64(raw_ptr->arm_id_aa64dfr[i]);
} }
else if ((sscanf(line, "arm_id_aa64fpfr%d=%" SCNx64, &i, &aarch64_reg) >= 2)) {
RAW_ASSIGN_LINE_AARCH64(raw_ptr->arm_id_aa64fpfr[i]);
}
else if ((sscanf(line, "arm_id_aa64isar%d=%" SCNx64, &i, &aarch64_reg) >= 2)) { else if ((sscanf(line, "arm_id_aa64isar%d=%" SCNx64, &i, &aarch64_reg) >= 2)) {
RAW_ASSIGN_LINE_AARCH64(raw_ptr->arm_id_aa64isar[i]); RAW_ASSIGN_LINE_AARCH64(raw_ptr->arm_id_aa64isar[i]);
} }
@ -1418,6 +1423,8 @@ int cpuid_get_raw_data_core(struct cpu_raw_data_t* data, logical_cpu_t logical_c
cpu_read_arm_register_64b(handle, REQ_ID_AA64AFR0 + i, &data->arm_id_aa64afr[i]); cpu_read_arm_register_64b(handle, REQ_ID_AA64AFR0 + i, &data->arm_id_aa64afr[i]);
for (i = 0; i < MAX_ARM_ID_AA64DFR_REGS; i++) for (i = 0; i < MAX_ARM_ID_AA64DFR_REGS; i++)
cpu_read_arm_register_64b(handle, REQ_ID_AA64DFR0 + i, &data->arm_id_aa64dfr[i]); cpu_read_arm_register_64b(handle, REQ_ID_AA64DFR0 + i, &data->arm_id_aa64dfr[i]);
for (i = 0; i < MAX_ARM_ID_AA64FPFR_REGS; i++)
cpu_read_arm_register_64b(handle, REQ_ID_AA64FPFR0 + i, &data->arm_id_aa64fpfr[i]);
for (i = 0; i < MAX_ARM_ID_AA64ISAR_REGS; i++) for (i = 0; i < MAX_ARM_ID_AA64ISAR_REGS; i++)
cpu_read_arm_register_64b(handle, REQ_ID_AA64ISAR0 + i, &data->arm_id_aa64isar[i]); cpu_read_arm_register_64b(handle, REQ_ID_AA64ISAR0 + i, &data->arm_id_aa64isar[i]);
for (i = 0; i < MAX_ARM_ID_AA64MMFR_REGS; i++) for (i = 0; i < MAX_ARM_ID_AA64MMFR_REGS; i++)
@ -1444,9 +1451,12 @@ int cpuid_get_raw_data_core(struct cpu_raw_data_t* data, logical_cpu_t logical_c
cpu_exec_mrs(AARCH64_REG_ID_AA64AFR1_EL1, data->arm_id_aa64afr[1]); cpu_exec_mrs(AARCH64_REG_ID_AA64AFR1_EL1, data->arm_id_aa64afr[1]);
cpu_exec_mrs(AARCH64_REG_ID_AA64DFR0_EL1, data->arm_id_aa64dfr[0]); cpu_exec_mrs(AARCH64_REG_ID_AA64DFR0_EL1, data->arm_id_aa64dfr[0]);
cpu_exec_mrs(AARCH64_REG_ID_AA64DFR1_EL1, data->arm_id_aa64dfr[1]); cpu_exec_mrs(AARCH64_REG_ID_AA64DFR1_EL1, data->arm_id_aa64dfr[1]);
cpu_exec_mrs(AARCH64_REG_ID_AA64DFR2_EL1, data->arm_id_aa64dfr[2]);
cpu_exec_mrs(AARCH64_REG_ID_AA64FPFR0_EL1, data->arm_id_aa64fpfr[0]);
cpu_exec_mrs(AARCH64_REG_ID_AA64ISAR0_EL1, data->arm_id_aa64isar[0]); cpu_exec_mrs(AARCH64_REG_ID_AA64ISAR0_EL1, data->arm_id_aa64isar[0]);
cpu_exec_mrs(AARCH64_REG_ID_AA64ISAR1_EL1, data->arm_id_aa64isar[1]); cpu_exec_mrs(AARCH64_REG_ID_AA64ISAR1_EL1, data->arm_id_aa64isar[1]);
cpu_exec_mrs(AARCH64_REG_ID_AA64ISAR2_EL1, data->arm_id_aa64isar[2]); cpu_exec_mrs(AARCH64_REG_ID_AA64ISAR2_EL1, data->arm_id_aa64isar[2]);
cpu_exec_mrs(AARCH64_REG_ID_AA64ISAR3_EL1, data->arm_id_aa64isar[3]);
cpu_exec_mrs(AARCH64_REG_ID_AA64MMFR0_EL1, data->arm_id_aa64mmfr[0]); cpu_exec_mrs(AARCH64_REG_ID_AA64MMFR0_EL1, data->arm_id_aa64mmfr[0]);
cpu_exec_mrs(AARCH64_REG_ID_AA64MMFR1_EL1, data->arm_id_aa64mmfr[1]); cpu_exec_mrs(AARCH64_REG_ID_AA64MMFR1_EL1, data->arm_id_aa64mmfr[1]);
cpu_exec_mrs(AARCH64_REG_ID_AA64MMFR2_EL1, data->arm_id_aa64mmfr[2]); cpu_exec_mrs(AARCH64_REG_ID_AA64MMFR2_EL1, data->arm_id_aa64mmfr[2]);
@ -1876,6 +1886,7 @@ const char* cpu_feature_level_str(cpu_feature_level_t level)
{ FEATURE_LEVEL_ARM_V9_2_A, "ARMv9.2-A" }, { FEATURE_LEVEL_ARM_V9_2_A, "ARMv9.2-A" },
{ FEATURE_LEVEL_ARM_V9_3_A, "ARMv9.3-A" }, { FEATURE_LEVEL_ARM_V9_3_A, "ARMv9.3-A" },
{ FEATURE_LEVEL_ARM_V9_4_A, "ARMv9.4-A" }, { FEATURE_LEVEL_ARM_V9_4_A, "ARMv9.4-A" },
{ FEATURE_LEVEL_ARM_V9_5_A, "ARMv9.5-A" },
}; };
unsigned i, n = COUNT_OF(matchtable); unsigned i, n = COUNT_OF(matchtable);
if (n != (NUM_FEATURE_LEVELS - FEATURE_LEVEL_ARM_V1) + (FEATURE_LEVEL_X86_64_V4 - FEATURE_LEVEL_I386) + 2) { if (n != (NUM_FEATURE_LEVELS - FEATURE_LEVEL_ARM_V1) + (FEATURE_LEVEL_X86_64_V4 - FEATURE_LEVEL_I386) + 2) {
@ -2053,14 +2064,17 @@ const char* cpu_feature_str(cpu_feature_t feature)
{ CPU_FEATURE_AVX512VBMI, "avx512vbmi" }, { CPU_FEATURE_AVX512VBMI, "avx512vbmi" },
{ CPU_FEATURE_AVX512VBMI2, "avx512vbmi2" }, { CPU_FEATURE_AVX512VBMI2, "avx512vbmi2" },
{ CPU_FEATURE_HYPERVISOR, "hypervisor" }, { CPU_FEATURE_HYPERVISOR, "hypervisor" },
/* Arm */
{ CPU_FEATURE_SWAP, "swap" }, { CPU_FEATURE_SWAP, "swap" },
{ CPU_FEATURE_THUMB, "thumb" }, { CPU_FEATURE_THUMB, "thumb" },
{ CPU_FEATURE_ADVMULTU, "advmultu" }, { CPU_FEATURE_ADVMULTU, "advmultu" },
{ CPU_FEATURE_ADVMULTS, "advmults" }, { CPU_FEATURE_ADVMULTS, "advmults" },
{ CPU_FEATURE_JAZELLE, "jazelle" }, { CPU_FEATURE_JAZELLE, "jazelle" },
/* Armv6.0 */
{ CPU_FEATURE_DEBUGV6, "debugv6" }, { CPU_FEATURE_DEBUGV6, "debugv6" },
{ CPU_FEATURE_DEBUGV6P1, "debugv6p1" }, { CPU_FEATURE_DEBUGV6P1, "debugv6p1" },
{ CPU_FEATURE_THUMB2, "thumb2" }, { CPU_FEATURE_THUMB2, "thumb2" },
/* Armv7.0 */
{ CPU_FEATURE_DEBUGV7, "debugv7" }, { CPU_FEATURE_DEBUGV7, "debugv7" },
{ CPU_FEATURE_DEBUGV7P1, "debugv7p1" }, { CPU_FEATURE_DEBUGV7P1, "debugv7p1" },
{ CPU_FEATURE_THUMBEE, "thumbee" }, { CPU_FEATURE_THUMBEE, "thumbee" },
@ -2068,6 +2082,7 @@ const char* cpu_feature_str(cpu_feature_t feature)
{ CPU_FEATURE_LPAE, "lpae" }, { CPU_FEATURE_LPAE, "lpae" },
{ CPU_FEATURE_PMUV1, "pmuv1" }, { CPU_FEATURE_PMUV1, "pmuv1" },
{ CPU_FEATURE_PMUV2, "pmuv2" }, { CPU_FEATURE_PMUV2, "pmuv2" },
/* A2.2.1 The Armv8.0 architecture extension */
{ CPU_FEATURE_ASID16, "asid16" }, { CPU_FEATURE_ASID16, "asid16" },
{ CPU_FEATURE_ADVSIMD, "advsimd" }, { CPU_FEATURE_ADVSIMD, "advsimd" },
{ CPU_FEATURE_CRC32, "crc32" }, { CPU_FEATURE_CRC32, "crc32" },
@ -2085,6 +2100,7 @@ const char* cpu_feature_str(cpu_feature_t feature)
{ CPU_FEATURE_SHA1, "sha1" }, { CPU_FEATURE_SHA1, "sha1" },
{ CPU_FEATURE_SHA256, "sha256" }, { CPU_FEATURE_SHA256, "sha256" },
{ CPU_FEATURE_NTLBPA, "ntlbpa" }, { CPU_FEATURE_NTLBPA, "ntlbpa" },
/* A2.2.2 The Armv8.1 architecture extension */
{ CPU_FEATURE_HAFDBS, "hafdbs" }, { CPU_FEATURE_HAFDBS, "hafdbs" },
{ CPU_FEATURE_HPDS, "hpds" }, { CPU_FEATURE_HPDS, "hpds" },
{ CPU_FEATURE_LOR, "lor" }, { CPU_FEATURE_LOR, "lor" },
@ -2094,6 +2110,7 @@ const char* cpu_feature_str(cpu_feature_t feature)
{ CPU_FEATURE_RDM, "rdm" }, { CPU_FEATURE_RDM, "rdm" },
{ CPU_FEATURE_VHE, "vhe" }, { CPU_FEATURE_VHE, "vhe" },
{ CPU_FEATURE_VMID16, "vmid16" }, { CPU_FEATURE_VMID16, "vmid16" },
/* A2.2.3 The Armv8.2 architecture extension */
{ CPU_FEATURE_AA32HPD, "aa32hpd" }, { CPU_FEATURE_AA32HPD, "aa32hpd" },
{ CPU_FEATURE_AA32I8MM, "aa32i8mm" }, { CPU_FEATURE_AA32I8MM, "aa32i8mm" },
{ CPU_FEATURE_DPB, "dpb" }, { CPU_FEATURE_DPB, "dpb" },
@ -2118,6 +2135,7 @@ const char* cpu_feature_str(cpu_feature_t feature)
{ CPU_FEATURE_TTCNP, "ttcnp" }, { CPU_FEATURE_TTCNP, "ttcnp" },
{ CPU_FEATURE_UAO, "uao" }, { CPU_FEATURE_UAO, "uao" },
{ CPU_FEATURE_XNX, "xnx" }, { CPU_FEATURE_XNX, "xnx" },
/* A2.2.4 The Armv8.3 architecture extension */
{ CPU_FEATURE_CCIDX, "ccidx" }, { CPU_FEATURE_CCIDX, "ccidx" },
{ CPU_FEATURE_CONSTPACFIELD, "constpacfield" }, { CPU_FEATURE_CONSTPACFIELD, "constpacfield" },
{ CPU_FEATURE_EPAC, "epac" }, { CPU_FEATURE_EPAC, "epac" },
@ -2131,6 +2149,7 @@ const char* cpu_feature_str(cpu_feature_t feature)
{ CPU_FEATURE_PACQARMA5, "pacqarma5" }, { CPU_FEATURE_PACQARMA5, "pacqarma5" },
{ CPU_FEATURE_PAUTH, "pauth" }, { CPU_FEATURE_PAUTH, "pauth" },
{ CPU_FEATURE_SPEV1P1, "spev1p1" }, { CPU_FEATURE_SPEV1P1, "spev1p1" },
/* A2.2.5 The Armv8.4 architecture extension */
{ CPU_FEATURE_AMUV1, "amuv1" }, { CPU_FEATURE_AMUV1, "amuv1" },
{ CPU_FEATURE_BBM, "bbm" }, { CPU_FEATURE_BBM, "bbm" },
{ CPU_FEATURE_DIT, "dit" }, { CPU_FEATURE_DIT, "dit" },
@ -2152,6 +2171,7 @@ const char* cpu_feature_str(cpu_feature_t feature)
{ CPU_FEATURE_TRF, "trf" }, { CPU_FEATURE_TRF, "trf" },
{ CPU_FEATURE_TTL, "ttl" }, { CPU_FEATURE_TTL, "ttl" },
{ CPU_FEATURE_TTST, "ttst" }, { CPU_FEATURE_TTST, "ttst" },
/* A2.2.6 The Armv8.5 architecture extension */
{ CPU_FEATURE_BTI, "bti" }, { CPU_FEATURE_BTI, "bti" },
{ CPU_FEATURE_CSV2, "csv2" }, { CPU_FEATURE_CSV2, "csv2" },
{ CPU_FEATURE_CSV3, "csv3" }, { CPU_FEATURE_CSV3, "csv3" },
@ -2170,6 +2190,7 @@ const char* cpu_feature_str(cpu_feature_t feature)
{ CPU_FEATURE_SPECRES, "specres" }, { CPU_FEATURE_SPECRES, "specres" },
{ CPU_FEATURE_SSBS, "ssbs" }, { CPU_FEATURE_SSBS, "ssbs" },
{ CPU_FEATURE_SSBS2, "ssbs2" }, { CPU_FEATURE_SSBS2, "ssbs2" },
/* A2.2.7 The Armv8.6 architecture extension */
{ CPU_FEATURE_AA32BF16, "aa32bf16" }, { CPU_FEATURE_AA32BF16, "aa32bf16" },
{ CPU_FEATURE_AMUV1P1, "amuv1p1" }, { CPU_FEATURE_AMUV1P1, "amuv1p1" },
{ CPU_FEATURE_BF16, "bf16" }, { CPU_FEATURE_BF16, "bf16" },
@ -2182,6 +2203,7 @@ const char* cpu_feature_str(cpu_feature_t feature)
{ CPU_FEATURE_MTPMU, "mtpmu" }, { CPU_FEATURE_MTPMU, "mtpmu" },
{ CPU_FEATURE_PAUTH2, "pauth2" }, { CPU_FEATURE_PAUTH2, "pauth2" },
{ CPU_FEATURE_TWED, "twed" }, { CPU_FEATURE_TWED, "twed" },
/* A2.2.8 The Armv8.7 architecture extension */
{ CPU_FEATURE_AFP, "afp" }, { CPU_FEATURE_AFP, "afp" },
{ CPU_FEATURE_EBF16, "ebf16" }, { CPU_FEATURE_EBF16, "ebf16" },
{ CPU_FEATURE_HCX, "hcx" }, { CPU_FEATURE_HCX, "hcx" },
@ -2197,6 +2219,7 @@ const char* cpu_feature_str(cpu_feature_t feature)
{ CPU_FEATURE_SPEV1P2, "spev1p2" }, { CPU_FEATURE_SPEV1P2, "spev1p2" },
{ CPU_FEATURE_WFXT, "wfxt" }, { CPU_FEATURE_WFXT, "wfxt" },
{ CPU_FEATURE_XS, "xs" }, { CPU_FEATURE_XS, "xs" },
/* A2.2.9 The Armv8.8 architecture extension */
{ CPU_FEATURE_CMOW, "cmow" }, { CPU_FEATURE_CMOW, "cmow" },
{ CPU_FEATURE_DEBUGV8P8, "debugv8p8" }, { CPU_FEATURE_DEBUGV8P8, "debugv8p8" },
{ CPU_FEATURE_HBC, "hbc" }, { CPU_FEATURE_HBC, "hbc" },
@ -2207,6 +2230,7 @@ const char* cpu_feature_str(cpu_feature_t feature)
{ CPU_FEATURE_SPEV1P3, "spev1p3" }, { CPU_FEATURE_SPEV1P3, "spev1p3" },
{ CPU_FEATURE_TCR2, "tcr2" }, { CPU_FEATURE_TCR2, "tcr2" },
{ CPU_FEATURE_TIDCP1, "tidcp1" }, { CPU_FEATURE_TIDCP1, "tidcp1" },
/* A2.2.10 The Armv8.9 architecture extension */
{ CPU_FEATURE_ADERR, "aderr" }, { CPU_FEATURE_ADERR, "aderr" },
{ CPU_FEATURE_AIE, "aie" }, { CPU_FEATURE_AIE, "aie" },
{ CPU_FEATURE_ANERR, "anerr" }, { CPU_FEATURE_ANERR, "anerr" },
@ -2242,6 +2266,7 @@ const char* cpu_feature_str(cpu_feature_t feature)
{ CPU_FEATURE_SPEV1P4, "spev1p4" }, { CPU_FEATURE_SPEV1P4, "spev1p4" },
{ CPU_FEATURE_SPMU, "spmu" }, { CPU_FEATURE_SPMU, "spmu" },
{ CPU_FEATURE_THE, "the" }, { CPU_FEATURE_THE, "the" },
/* A2.3.1 The Armv9.0 architecture extension */
{ CPU_FEATURE_SVE2, "sve2" }, { CPU_FEATURE_SVE2, "sve2" },
{ CPU_FEATURE_SVE_AES, "sve_aes" }, { CPU_FEATURE_SVE_AES, "sve_aes" },
{ CPU_FEATURE_SVE_BITPERM, "sve_bitperm" }, { CPU_FEATURE_SVE_BITPERM, "sve_bitperm" },
@ -2250,15 +2275,18 @@ const char* cpu_feature_str(cpu_feature_t feature)
{ CPU_FEATURE_SVE_SM4, "sve_sm4" }, { CPU_FEATURE_SVE_SM4, "sve_sm4" },
{ CPU_FEATURE_TME, "tme" }, { CPU_FEATURE_TME, "tme" },
{ CPU_FEATURE_TRBE, "trbe" }, { CPU_FEATURE_TRBE, "trbe" },
/* A2.3.3 The Armv9.2 architecture extension */
{ CPU_FEATURE_BRBE, "brbe" }, { CPU_FEATURE_BRBE, "brbe" },
{ CPU_FEATURE_RME, "rme" }, { CPU_FEATURE_RME, "rme" },
{ CPU_FEATURE_SME, "sme" }, { CPU_FEATURE_SME, "sme" },
{ CPU_FEATURE_SME_F64F64, "sme_f64f64" }, { CPU_FEATURE_SME_F64F64, "sme_f64f64" },
{ CPU_FEATURE_SME_FA64, "sme_fa64" }, { CPU_FEATURE_SME_FA64, "sme_fa64" },
{ CPU_FEATURE_SME_I16I64, "sme_i16i64" }, { CPU_FEATURE_SME_I16I64, "sme_i16i64" },
/* A2.3.4 The Armv9.3 architecture extension */
{ CPU_FEATURE_BRBEV1P1, "brbev1p1" }, { CPU_FEATURE_BRBEV1P1, "brbev1p1" },
{ CPU_FEATURE_MEC, "mec" }, { CPU_FEATURE_MEC, "mec" },
{ CPU_FEATURE_SME2, "sme2" }, { CPU_FEATURE_SME2, "sme2" },
/* A2.3.5 The Armv9.4 architecture extension */
{ CPU_FEATURE_ABLE, "able" }, { CPU_FEATURE_ABLE, "able" },
{ CPU_FEATURE_BWE, "bwe" }, { CPU_FEATURE_BWE, "bwe" },
{ CPU_FEATURE_D128, "d128" }, { CPU_FEATURE_D128, "d128" },
@ -2275,6 +2303,35 @@ const char* cpu_feature_str(cpu_feature_t feature)
{ CPU_FEATURE_SYSINSTR128, "sysinstr128" }, { CPU_FEATURE_SYSINSTR128, "sysinstr128" },
{ CPU_FEATURE_SYSREG128, "sysreg128" }, { CPU_FEATURE_SYSREG128, "sysreg128" },
{ CPU_FEATURE_TRBE_EXT, "trbe_ext" }, { CPU_FEATURE_TRBE_EXT, "trbe_ext" },
/* A2.3.6 The Armv9.5 architecture extension */
{ CPU_FEATURE_ASID2, "asid2" },
{ CPU_FEATURE_BWE2, "bwe2" },
{ CPU_FEATURE_CPA, "cpa" },
{ CPU_FEATURE_CPA2, "cpa2" },
{ CPU_FEATURE_E2H0, "e2h0" },
{ CPU_FEATURE_E3DSE, "e3dse" },
{ CPU_FEATURE_ETS3, "ets3" },
{ CPU_FEATURE_FAMINMAX, "faminmax" },
{ CPU_FEATURE_FGWTE3, "fgwte3" },
{ CPU_FEATURE_FP8, "fp8" },
{ CPU_FEATURE_FP8DOT2, "fp8dot2" },
{ CPU_FEATURE_FP8DOT4, "fp8dot4" },
{ CPU_FEATURE_FP8FMA, "fp8fma" },
{ CPU_FEATURE_FPMR, "fpmr" },
{ CPU_FEATURE_HACDBS, "hacdbs" },
{ CPU_FEATURE_HDBSS, "hdbss" },
{ CPU_FEATURE_LUT, "lut" },
{ CPU_FEATURE_PAUTH_LR, "pauth_lr" },
{ CPU_FEATURE_RME_GPC2, "rme_gpc2" },
{ CPU_FEATURE_SME_F8F16, "sme_f8f16" },
{ CPU_FEATURE_SME_F8F32, "sme_f8f32" },
{ CPU_FEATURE_SME_LUTV2, "sme_lutv2" },
{ CPU_FEATURE_SPMU2, "spmu2" },
{ CPU_FEATURE_SSVE_FP8DOT2, "ssve_fp8dot2" },
{ CPU_FEATURE_SSVE_FP8DOT4, "ssve_fp8dot4" },
{ CPU_FEATURE_SSVE_FP8FMA, "ssve_fp8fma" },
{ CPU_FEATURE_STEP2, "step2" },
{ CPU_FEATURE_TLBIW, "tlbiw" },
}; };
unsigned i, n = COUNT_OF(matchtable); unsigned i, n = COUNT_OF(matchtable);
if (n != NUM_CPU_FEATURES) { if (n != NUM_CPU_FEATURES) {

69
libcpuid/libcpuid.h
View file

@ -240,6 +240,7 @@ typedef enum {
FEATURE_LEVEL_ARM_V9_2_A, /*!< ARMv9.2-A */ FEATURE_LEVEL_ARM_V9_2_A, /*!< ARMv9.2-A */
FEATURE_LEVEL_ARM_V9_3_A, /*!< ARMv9.3-A */ FEATURE_LEVEL_ARM_V9_3_A, /*!< ARMv9.3-A */
FEATURE_LEVEL_ARM_V9_4_A, /*!< ARMv9.4-A */ FEATURE_LEVEL_ARM_V9_4_A, /*!< ARMv9.4-A */
FEATURE_LEVEL_ARM_V9_5_A, /*!< ARMv9.5-A */
NUM_FEATURE_LEVELS, /*!< Valid feature level ids: 0..NUM_FEATURE_LEVELS - 1 */ NUM_FEATURE_LEVELS, /*!< Valid feature level ids: 0..NUM_FEATURE_LEVELS - 1 */
FEATURE_LEVEL_UNKNOWN = -1, FEATURE_LEVEL_UNKNOWN = -1,
@ -365,6 +366,10 @@ struct cpu_raw_data_t {
* (AArch64 Debug Feature Register) */ * (AArch64 Debug Feature Register) */
uint64_t arm_id_aa64dfr[MAX_ARM_ID_AA64DFR_REGS]; uint64_t arm_id_aa64dfr[MAX_ARM_ID_AA64DFR_REGS];
/** when then CPU is ARM-based and supports ID_AA64FPFR*
* (Floating-point Feature Register) */
uint64_t arm_id_aa64fpfr[MAX_ARM_ID_AA64FPFR_REGS];
/** when then CPU is ARM-based and supports D_AA64ISAR* /** when then CPU is ARM-based and supports D_AA64ISAR*
* (AArch64 Instruction Set Attribute Register) */ * (AArch64 Instruction Set Attribute Register) */
uint64_t arm_id_aa64isar[MAX_ARM_ID_AA64ISAR_REGS]; uint64_t arm_id_aa64isar[MAX_ARM_ID_AA64ISAR_REGS];
@ -921,14 +926,17 @@ typedef enum {
CPU_FEATURE_AVX512VBMI, /*!< AVX-512 Vector Bit ManipulationInstructions (version 1) */ CPU_FEATURE_AVX512VBMI, /*!< AVX-512 Vector Bit ManipulationInstructions (version 1) */
CPU_FEATURE_AVX512VBMI2, /*!< AVX-512 Vector Bit ManipulationInstructions (version 2) */ CPU_FEATURE_AVX512VBMI2, /*!< AVX-512 Vector Bit ManipulationInstructions (version 2) */
CPU_FEATURE_HYPERVISOR, /*!< Hypervisor present (always zero on physical CPUs) */ CPU_FEATURE_HYPERVISOR, /*!< Hypervisor present (always zero on physical CPUs) */
/* Arm */
CPU_FEATURE_SWAP, /*!< ARM: Swap instructions in the ARM instruction set */ CPU_FEATURE_SWAP, /*!< ARM: Swap instructions in the ARM instruction set */
CPU_FEATURE_THUMB, /*!< ARM: Thumb instruction set support */ CPU_FEATURE_THUMB, /*!< ARM: Thumb instruction set support */
CPU_FEATURE_ADVMULTU, /*!< ARM: Advanced unsigned Multiply instructions */ CPU_FEATURE_ADVMULTU, /*!< ARM: Advanced unsigned Multiply instructions */
CPU_FEATURE_ADVMULTS, /*!< ARM: Advanced signed Multiply instructions */ CPU_FEATURE_ADVMULTS, /*!< ARM: Advanced signed Multiply instructions */
CPU_FEATURE_JAZELLE, /*!< ARM: Jazelle extension support */ CPU_FEATURE_JAZELLE, /*!< ARM: Jazelle extension support */
/* Armv6.0 */
CPU_FEATURE_DEBUGV6, /*!< ARM: Support for v6 Debug architecture */ CPU_FEATURE_DEBUGV6, /*!< ARM: Support for v6 Debug architecture */
CPU_FEATURE_DEBUGV6P1, /*!< ARM: Support for v6.1 Debug architecture */ CPU_FEATURE_DEBUGV6P1, /*!< ARM: Support for v6.1 Debug architecture */
CPU_FEATURE_THUMB2, /*!< ARM: Thumb-2, instruction set support */ CPU_FEATURE_THUMB2, /*!< ARM: Thumb-2, instruction set support */
/* Armv7.0 */
CPU_FEATURE_DEBUGV7, /*!< ARM: Support for v7 Debug architecture */ CPU_FEATURE_DEBUGV7, /*!< ARM: Support for v7 Debug architecture */
CPU_FEATURE_DEBUGV7P1, /*!< ARM: Support for v7.1 Debug architecture */ CPU_FEATURE_DEBUGV7P1, /*!< ARM: Support for v7.1 Debug architecture */
CPU_FEATURE_THUMBEE, /*!< ARM: ThumbEE instruction set support */ CPU_FEATURE_THUMBEE, /*!< ARM: ThumbEE instruction set support */
@ -936,6 +944,7 @@ typedef enum {
CPU_FEATURE_LPAE, /*!< ARM: Large Physical Address Extension */ CPU_FEATURE_LPAE, /*!< ARM: Large Physical Address Extension */
CPU_FEATURE_PMUV1, /*!< ARM: PMU extension version 1 */ CPU_FEATURE_PMUV1, /*!< ARM: PMU extension version 1 */
CPU_FEATURE_PMUV2, /*!< ARM: PMU extension version 2 */ CPU_FEATURE_PMUV2, /*!< ARM: PMU extension version 2 */
/* A2.2.1 The Armv8.0 architecture extension */
CPU_FEATURE_ASID16, /*!< ARM: 16 bit ASID */ CPU_FEATURE_ASID16, /*!< ARM: 16 bit ASID */
CPU_FEATURE_ADVSIMD, /*!< ARM: Advanced SIMD Extension */ CPU_FEATURE_ADVSIMD, /*!< ARM: Advanced SIMD Extension */
CPU_FEATURE_CRC32, /*!< ARM: CRC32 instructions */ CPU_FEATURE_CRC32, /*!< ARM: CRC32 instructions */
@ -953,6 +962,7 @@ typedef enum {
CPU_FEATURE_SHA1, /*!< ARM: Advanced SIMD SHA1 instructions */ CPU_FEATURE_SHA1, /*!< ARM: Advanced SIMD SHA1 instructions */
CPU_FEATURE_SHA256, /*!< ARM: Advanced SIMD SHA256 instructions */ CPU_FEATURE_SHA256, /*!< ARM: Advanced SIMD SHA256 instructions */
CPU_FEATURE_NTLBPA, /*!< ARM: Intermediate caching of translation table walks */ CPU_FEATURE_NTLBPA, /*!< ARM: Intermediate caching of translation table walks */
/* A2.2.2 The Armv8.1 architecture extension */
CPU_FEATURE_HAFDBS, /*!< ARM: Hardware management of the Access flag and dirty state */ CPU_FEATURE_HAFDBS, /*!< ARM: Hardware management of the Access flag and dirty state */
CPU_FEATURE_HPDS, /*!< ARM: Hierarchical permission disables in translations tables */ CPU_FEATURE_HPDS, /*!< ARM: Hierarchical permission disables in translations tables */
CPU_FEATURE_LOR, /*!< ARM: Limited ordering regions */ CPU_FEATURE_LOR, /*!< ARM: Limited ordering regions */
@ -962,6 +972,7 @@ typedef enum {
CPU_FEATURE_RDM, /*!< ARM: Advanced SIMD rounding double multiply accumulate instructions */ CPU_FEATURE_RDM, /*!< ARM: Advanced SIMD rounding double multiply accumulate instructions */
CPU_FEATURE_VHE, /*!< ARM: Virtualization Host Extensions */ CPU_FEATURE_VHE, /*!< ARM: Virtualization Host Extensions */
CPU_FEATURE_VMID16, /*!< ARM: 16-bit VMID */ CPU_FEATURE_VMID16, /*!< ARM: 16-bit VMID */
/* A2.2.3 The Armv8.2 architecture extension */
CPU_FEATURE_AA32HPD, /*!< ARM: AArch32 Hierarchical permission disables */ CPU_FEATURE_AA32HPD, /*!< ARM: AArch32 Hierarchical permission disables */
CPU_FEATURE_AA32I8MM, /*!< ARM: AArch32 Int8 matrix multiplication instructions */ CPU_FEATURE_AA32I8MM, /*!< ARM: AArch32 Int8 matrix multiplication instructions */
CPU_FEATURE_DPB, /*!< ARM: DC CVAP instruction */ CPU_FEATURE_DPB, /*!< ARM: DC CVAP instruction */
@ -977,8 +988,8 @@ typedef enum {
CPU_FEATURE_LVA, /*!< ARM: Large VA support */ CPU_FEATURE_LVA, /*!< ARM: Large VA support */
CPU_FEATURE_PAN2, /*!< ARM: AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN */ CPU_FEATURE_PAN2, /*!< ARM: AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN */
CPU_FEATURE_RAS, /*!< ARM: Reliability, Availability and Serviceability (RAS) Extension */ CPU_FEATURE_RAS, /*!< ARM: Reliability, Availability and Serviceability (RAS) Extension */
CPU_FEATURE_SHA3, /*!< ARM: Advanced SIMD SHA3 instructions (ARMv8.2 architecture extension) */ CPU_FEATURE_SHA3, /*!< ARM: Advanced SIMD SHA3 instructions */
CPU_FEATURE_SHA512, /*!< ARM: Advanced SIMD SHA512 instructions (ARMv8.1 architecture extension) */ CPU_FEATURE_SHA512, /*!< ARM: Advanced SIMD SHA512 instructions */
CPU_FEATURE_SM3, /*!< ARM: Advanced SIMD SM3 instructions */ CPU_FEATURE_SM3, /*!< ARM: Advanced SIMD SM3 instructions */
CPU_FEATURE_SM4, /*!< ARM: Advanced SIMD SM4 instructions */ CPU_FEATURE_SM4, /*!< ARM: Advanced SIMD SM4 instructions */
CPU_FEATURE_SPE, /*!< ARM: Statistical Profiling Extension */ CPU_FEATURE_SPE, /*!< ARM: Statistical Profiling Extension */
@ -986,6 +997,7 @@ typedef enum {
CPU_FEATURE_TTCNP, /*!< ARM: Translation table Common not private translations */ CPU_FEATURE_TTCNP, /*!< ARM: Translation table Common not private translations */
CPU_FEATURE_UAO, /*!< ARM: Unprivileged Access Override control */ CPU_FEATURE_UAO, /*!< ARM: Unprivileged Access Override control */
CPU_FEATURE_XNX, /*!< ARM: Translation table stage 2 Unprivileged Execute-never */ CPU_FEATURE_XNX, /*!< ARM: Translation table stage 2 Unprivileged Execute-never */
/* A2.2.4 The Armv8.3 architecture extension */
CPU_FEATURE_CCIDX, /*!< ARM: Extended cache index */ CPU_FEATURE_CCIDX, /*!< ARM: Extended cache index */
CPU_FEATURE_CONSTPACFIELD, /*!< ARM: PAC algorithm enhancement */ CPU_FEATURE_CONSTPACFIELD, /*!< ARM: PAC algorithm enhancement */
CPU_FEATURE_EPAC, /*!< ARM: Enhanced pointer authentication */ CPU_FEATURE_EPAC, /*!< ARM: Enhanced pointer authentication */
@ -999,6 +1011,7 @@ typedef enum {
CPU_FEATURE_PACQARMA5, /*!< ARM: Pointer authentication - QARMA5 algorithm */ CPU_FEATURE_PACQARMA5, /*!< ARM: Pointer authentication - QARMA5 algorithm */
CPU_FEATURE_PAUTH, /*!< ARM: Pointer authentication */ CPU_FEATURE_PAUTH, /*!< ARM: Pointer authentication */
CPU_FEATURE_SPEV1P1, /*!< ARM: Statistical Profiling Extension version 1 */ CPU_FEATURE_SPEV1P1, /*!< ARM: Statistical Profiling Extension version 1 */
/* A2.2.5 The Armv8.4 architecture extension */
CPU_FEATURE_AMUV1, /*!< ARM: Activity Monitors Extension version 1 */ CPU_FEATURE_AMUV1, /*!< ARM: Activity Monitors Extension version 1 */
CPU_FEATURE_BBM, /*!< ARM: Translation table break-before-make levels */ CPU_FEATURE_BBM, /*!< ARM: Translation table break-before-make levels */
CPU_FEATURE_DIT, /*!< ARM: Data Independent Timing instructions */ CPU_FEATURE_DIT, /*!< ARM: Data Independent Timing instructions */
@ -1020,6 +1033,7 @@ typedef enum {
CPU_FEATURE_TRF, /*!< ARM: Self-hosted Trace extensions */ CPU_FEATURE_TRF, /*!< ARM: Self-hosted Trace extensions */
CPU_FEATURE_TTL, /*!< ARM: Translation Table Level */ CPU_FEATURE_TTL, /*!< ARM: Translation Table Level */
CPU_FEATURE_TTST, /*!< ARM: Small translation tables */ CPU_FEATURE_TTST, /*!< ARM: Small translation tables */
/* A2.2.6 The Armv8.5 architecture extension */
CPU_FEATURE_BTI, /*!< ARM: Branch Target Identification */ CPU_FEATURE_BTI, /*!< ARM: Branch Target Identification */
CPU_FEATURE_CSV2, /*!< ARM: Cache Speculation Variant 2 */ CPU_FEATURE_CSV2, /*!< ARM: Cache Speculation Variant 2 */
CPU_FEATURE_CSV3, /*!< ARM: Cache Speculation Variant 3 */ CPU_FEATURE_CSV3, /*!< ARM: Cache Speculation Variant 3 */
@ -1038,6 +1052,7 @@ typedef enum {
CPU_FEATURE_SPECRES, /*!< ARM: Speculation restriction instructions */ CPU_FEATURE_SPECRES, /*!< ARM: Speculation restriction instructions */
CPU_FEATURE_SSBS, /*!< ARM: Speculative Store Bypass Safe */ CPU_FEATURE_SSBS, /*!< ARM: Speculative Store Bypass Safe */
CPU_FEATURE_SSBS2, /*!< ARM: MRS and MSR instructions for SSBS version 2 */ CPU_FEATURE_SSBS2, /*!< ARM: MRS and MSR instructions for SSBS version 2 */
/* A2.2.7 The Armv8.6 architecture extension */
CPU_FEATURE_AA32BF16, /*!< ARM: AArch32 BFloat16 instructions */ CPU_FEATURE_AA32BF16, /*!< ARM: AArch32 BFloat16 instructions */
CPU_FEATURE_AMUV1P1, /*!< ARM: Activity Monitors Extension version 1.1 */ CPU_FEATURE_AMUV1P1, /*!< ARM: Activity Monitors Extension version 1.1 */
CPU_FEATURE_BF16, /*!< ARM: AArch64 BFloat16 instructions */ CPU_FEATURE_BF16, /*!< ARM: AArch64 BFloat16 instructions */
@ -1045,13 +1060,14 @@ typedef enum {
CPU_FEATURE_ECV, /*!< ARM: Enhanced Counter Virtualization */ CPU_FEATURE_ECV, /*!< ARM: Enhanced Counter Virtualization */
CPU_FEATURE_FGT, /*!< ARM: Fine Grain Traps */ CPU_FEATURE_FGT, /*!< ARM: Fine Grain Traps */
CPU_FEATURE_HPMN0, /*!< ARM: Setting of MDCR_EL2.HPMN to zero */ CPU_FEATURE_HPMN0, /*!< ARM: Setting of MDCR_EL2.HPMN to zero */
CPU_FEATURE_MPAMV0P1, /*!< ARM: Memory Partitioning and Monitoring version 0.1 */ CPU_FEATURE_MPAMV0P1, /*!< ARM: Memory Partitioning and Monitoring extension version 0.1 */
CPU_FEATURE_MPAMV1P1, /*!< ARM: Memory Partitioning and Monitoring version 1.1 */ CPU_FEATURE_MPAMV1P1, /*!< ARM: Memory Partitioning and Monitoring extension version 1.1 */
CPU_FEATURE_MTPMU, /*!< ARM: Multi-threaded PMU extensions */ CPU_FEATURE_MTPMU, /*!< ARM: Multi-threaded PMU extensions */
CPU_FEATURE_PAUTH2, /*!< ARM: Enhancements to pointer authentication */ CPU_FEATURE_PAUTH2, /*!< ARM: Enhancements to pointer authentication */
CPU_FEATURE_TWED, /*!< ARM: Delayed Trapping of WFE */ CPU_FEATURE_TWED, /*!< ARM: Delayed Trapping of WFE */
/* A2.2.8 The Armv8.7 architecture extension */
CPU_FEATURE_AFP, /*!< ARM: Alternate floating-point behavior */ CPU_FEATURE_AFP, /*!< ARM: Alternate floating-point behavior */
CPU_FEATURE_EBF16, /*!< ARM: AArch64 Extended BFloat16 instructions */ CPU_FEATURE_EBF16, /*!< ARM: AArch64 Extended BFloat16 behaviors */
CPU_FEATURE_HCX, /*!< ARM: Support for the HCRX_EL2 register */ CPU_FEATURE_HCX, /*!< ARM: Support for the HCRX_EL2 register */
CPU_FEATURE_LPA2, /*!< ARM: Larger physical address for 4KB and 16KB translation granules */ CPU_FEATURE_LPA2, /*!< ARM: Larger physical address for 4KB and 16KB translation granules */
CPU_FEATURE_LS64, /*!< ARM: Support for 64-byte loads and stores without status */ CPU_FEATURE_LS64, /*!< ARM: Support for 64-byte loads and stores without status */
@ -1065,6 +1081,7 @@ typedef enum {
CPU_FEATURE_SPEV1P2, /*!< ARM: Statistical Profiling Extensions version 1.2 */ CPU_FEATURE_SPEV1P2, /*!< ARM: Statistical Profiling Extensions version 1.2 */
CPU_FEATURE_WFXT, /*!< ARM: WFE and WFI instructions with timeout */ CPU_FEATURE_WFXT, /*!< ARM: WFE and WFI instructions with timeout */
CPU_FEATURE_XS, /*!< ARM: XS attribute */ CPU_FEATURE_XS, /*!< ARM: XS attribute */
/* A2.2.9 The Armv8.8 architecture extension */
CPU_FEATURE_CMOW, /*!< ARM: Control for cache maintenance permission */ CPU_FEATURE_CMOW, /*!< ARM: Control for cache maintenance permission */
CPU_FEATURE_DEBUGV8P8, /*!< ARM: Debug v8.8 */ CPU_FEATURE_DEBUGV8P8, /*!< ARM: Debug v8.8 */
CPU_FEATURE_HBC, /*!< ARM: Hinted conditional branches */ CPU_FEATURE_HBC, /*!< ARM: Hinted conditional branches */
@ -1075,6 +1092,7 @@ typedef enum {
CPU_FEATURE_SPEV1P3, /*!< ARM: Statistical Profiling Extensions version 1.3 */ CPU_FEATURE_SPEV1P3, /*!< ARM: Statistical Profiling Extensions version 1.3 */
CPU_FEATURE_TCR2, /*!< ARM: Support for TCR2_ELx */ CPU_FEATURE_TCR2, /*!< ARM: Support for TCR2_ELx */
CPU_FEATURE_TIDCP1, /*!< ARM: EL0 use of IMPLEMENTATION DEFINED functionality */ CPU_FEATURE_TIDCP1, /*!< ARM: EL0 use of IMPLEMENTATION DEFINED functionality */
/* A2.2.10 The Armv8.9 architecture extension */
CPU_FEATURE_ADERR, /*!< ARM: Asynchronous Device Error Exceptions */ CPU_FEATURE_ADERR, /*!< ARM: Asynchronous Device Error Exceptions */
CPU_FEATURE_AIE, /*!< ARM: Memory Attribute Index Enhancement */ CPU_FEATURE_AIE, /*!< ARM: Memory Attribute Index Enhancement */
CPU_FEATURE_ANERR, /*!< ARM: Asynchronous Normal Error Exceptions */ CPU_FEATURE_ANERR, /*!< ARM: Asynchronous Normal Error Exceptions */
@ -1104,29 +1122,33 @@ typedef enum {
CPU_FEATURE_S1PIE, /*!< ARM: Stage 1 permission indirections */ CPU_FEATURE_S1PIE, /*!< ARM: Stage 1 permission indirections */
CPU_FEATURE_S1POE, /*!< ARM: Stage 1 permission overlays */ CPU_FEATURE_S1POE, /*!< ARM: Stage 1 permission overlays */
CPU_FEATURE_S2PIE, /*!< ARM: Stage 2 permission indirections */ CPU_FEATURE_S2PIE, /*!< ARM: Stage 2 permission indirections */
CPU_FEATURE_S2POE, /*!< ARM: Stage 1 permission overlays */ CPU_FEATURE_S2POE, /*!< ARM: Stage 2 permission overlays */
CPU_FEATURE_SPECRES2, /*!< ARM: Enhanced speculation restriction instructions */ CPU_FEATURE_SPECRES2, /*!< ARM: Enhanced speculation restriction instructions */
CPU_FEATURE_SPE_DPFZS, /*!< ARM: Disable Cycle Counter on SPE Freeze */ CPU_FEATURE_SPE_DPFZS, /*!< ARM: Disable Cycle Counter on SPE Freeze */
CPU_FEATURE_SPEV1P4, /*!< ARM: Statistical Profiling Extension version 1.4 */ CPU_FEATURE_SPEV1P4, /*!< ARM: Statistical Profiling Extension version 1.4 */
CPU_FEATURE_SPMU, /*!< ARM: System Performance Monitors Extension */ CPU_FEATURE_SPMU, /*!< ARM: System Performance Monitors Extension */
CPU_FEATURE_THE, /*!< ARM: Translation Hardening Extension */ CPU_FEATURE_THE, /*!< ARM: Translation Hardening Extension */
/* A2.3.1 The Armv9.0 architecture extension */
CPU_FEATURE_SVE2, /*!< ARM: Scalable Vector Extension version 2 */ CPU_FEATURE_SVE2, /*!< ARM: Scalable Vector Extension version 2 */
CPU_FEATURE_SVE_AES, /*!< ARM: Scalable Vector AES instructions */ CPU_FEATURE_SVE_AES, /*!< ARM: Scalable Vector AES instructions */
CPU_FEATURE_SVE_BITPERM, /*!< ARM: Scalable Vector Bit Permutes instructions */ CPU_FEATURE_SVE_BITPERM, /*!< ARM: Scalable Vector Bit Permutes instructions */
CPU_FEATURE_SVE_PMULL128, /*!< ARM: Scalable Vector PMULL instructions */ CPU_FEATURE_SVE_PMULL128, /*!< ARM: SVE single-vector Advanced Encryption Standard and 128-bit polynomial multiply long instructions */
CPU_FEATURE_SVE_SHA3, /*!< ARM: Scalable Vector SHA3 instructions */ CPU_FEATURE_SVE_SHA3, /*!< ARM: Scalable Vector SHA3 instructions */
CPU_FEATURE_SVE_SM4, /*!< ARM: Scalable Vector SM4 instructions */ CPU_FEATURE_SVE_SM4, /*!< ARM: Scalable Vector SM4 instructions */
CPU_FEATURE_TME, /*!< ARM: Transactional Memory Extension */ CPU_FEATURE_TME, /*!< ARM: Transactional Memory Extension */
CPU_FEATURE_TRBE, /*!< ARM: Trace Buffer Extension */ CPU_FEATURE_TRBE, /*!< ARM: Trace Buffer Extension */
/* A2.3.3 The Armv9.2 architecture extension */
CPU_FEATURE_BRBE, /*!< ARM: Branch Record Buffer Extension */ CPU_FEATURE_BRBE, /*!< ARM: Branch Record Buffer Extension */
CPU_FEATURE_RME, /*!< ARM: Realm Management Extension */ CPU_FEATURE_RME, /*!< ARM: Realm Management Extension */
CPU_FEATURE_SME, /*!< ARM: Scalable Matrix Extension */ CPU_FEATURE_SME, /*!< ARM: Scalable Matrix Extension */
CPU_FEATURE_SME_F64F64, /*!< ARM: Double-precision floating-point outer product instructions */ CPU_FEATURE_SME_F64F64, /*!< ARM: Double-precision floating-point outer product instructions */
CPU_FEATURE_SME_FA64, /*!< ARM: Full A64 instruction set support in Streaming SVE mode */ CPU_FEATURE_SME_FA64, /*!< ARM: Full A64 instruction set support in Streaming SVE mode */
CPU_FEATURE_SME_I16I64, /*!< ARM: 16-bit to 64-bit integer widening outer product instructions */ CPU_FEATURE_SME_I16I64, /*!< ARM: 16-bit to 64-bit integer widening outer product instructions */
/* A2.3.4 The Armv9.3 architecture extension */
CPU_FEATURE_BRBEV1P1, /*!< ARM: Branch Record Buffer Extension version 1.1 */ CPU_FEATURE_BRBEV1P1, /*!< ARM: Branch Record Buffer Extension version 1.1 */
CPU_FEATURE_MEC, /*!< ARM: Memory Encryption Contexts */ CPU_FEATURE_MEC, /*!< ARM: Memory Encryption Contexts */
CPU_FEATURE_SME2, /*!< ARM: Scalable Matrix Extensions version 2 */ CPU_FEATURE_SME2, /*!< ARM: Scalable Matrix Extensions version 2 */
/* A2.3.5 The Armv9.4 architecture extension */
CPU_FEATURE_ABLE, /*!< ARM: Address Breakpoint Linking Extension */ CPU_FEATURE_ABLE, /*!< ARM: Address Breakpoint Linking Extension */
CPU_FEATURE_BWE, /*!< ARM: Breakpoint and watchpoint enhancements */ CPU_FEATURE_BWE, /*!< ARM: Breakpoint and watchpoint enhancements */
CPU_FEATURE_D128, /*!< ARM: 128-bit Translation Tables, 56 bit PA */ CPU_FEATURE_D128, /*!< ARM: 128-bit Translation Tables, 56 bit PA */
@ -1137,12 +1159,41 @@ typedef enum {
CPU_FEATURE_LVA3, /*!< ARM: 56-bit VA */ CPU_FEATURE_LVA3, /*!< ARM: 56-bit VA */
CPU_FEATURE_SEBEP, /*!< ARM: Synchronous Exception-based Event Profiling */ CPU_FEATURE_SEBEP, /*!< ARM: Synchronous Exception-based Event Profiling */
CPU_FEATURE_SME2P1, /*!< ARM: Scalable Matrix Extension version 2.1 */ CPU_FEATURE_SME2P1, /*!< ARM: Scalable Matrix Extension version 2.1 */
CPU_FEATURE_SME_F16F16, /*!< ARM: Non-widening half-precision FP16 to FP16 arithmetic for SME2. */ CPU_FEATURE_SME_F16F16, /*!< ARM: Non-widening half-precision FP16 to FP16 arithmetic for SME2 */
CPU_FEATURE_SVE2P1, /*!< ARM: Scalable Vector Extensions version 2.1 */ CPU_FEATURE_SVE2P1, /*!< ARM: Scalable Vector Extensions version 2.1 */
CPU_FEATURE_SVE_B16B16, /*!< ARM: Non-widening BFloat16 to BFloat16 arithmetic for SVE2 and SME2. */ CPU_FEATURE_SVE_B16B16, /*!< ARM: Non-widening BFloat16 to BFloat16 arithmetic for SVE2 and SME2 */
CPU_FEATURE_SYSINSTR128, /*!< ARM: 128-bit System instructions */ CPU_FEATURE_SYSINSTR128, /*!< ARM: 128-bit System instructions */
CPU_FEATURE_SYSREG128, /*!< ARM: 128-bit System registers */ CPU_FEATURE_SYSREG128, /*!< ARM: 128-bit System registers */
CPU_FEATURE_TRBE_EXT, /*!< ARM: Trace Buffer external mode */ CPU_FEATURE_TRBE_EXT, /*!< ARM: Trace Buffer external mode */
/* A2.3.6 The Armv9.5 architecture extension */
CPU_FEATURE_ASID2, /*!< ARM: Support for concurrent use of two ASIDs */
CPU_FEATURE_BWE2, /*!< ARM: Breakpoint and watchpoint enhancements 2 */
CPU_FEATURE_CPA, /*!< ARM: Instruction-only Checked Pointer Arithmetic */
CPU_FEATURE_CPA2, /*!< ARM: Checked Pointer Arithmetic */
CPU_FEATURE_E2H0, /*!< ARM: Programming of HCR_EL2.E2H. */
CPU_FEATURE_E3DSE, /*!< ARM: Delegated SError exception injection */
CPU_FEATURE_ETS3, /*!< ARM: Enhanced Translation Synchronization */
CPU_FEATURE_FAMINMAX, /*!< ARM: Floating-point maximum and minimum absolute value instructions */
CPU_FEATURE_FGWTE3, /*!< ARM: Fine-Grained Write Trap EL3 */
CPU_FEATURE_FP8, /*!< ARM: FP8 convert instructions */
CPU_FEATURE_FP8DOT2, /*!< ARM: FP8 2-way dot product to half-precision instructions */
CPU_FEATURE_FP8DOT4, /*!< ARM: FP8 4-way dot product to single-precision instructions */
CPU_FEATURE_FP8FMA, /*!< ARM: FP8 multiply-accumulate to half-precision and single-precision instructions */
CPU_FEATURE_FPMR, /*!< ARM: Floating-point Mode Register */
CPU_FEATURE_HACDBS, /*!< ARM: Hardware accelerator for cleaning Dirty state */
CPU_FEATURE_HDBSS, /*!< ARM: Hardware Dirty state tracking structure */
CPU_FEATURE_LUT, /*!< ARM: Lookup table instructions with 2-bit and 4-bit indices */
CPU_FEATURE_PAUTH_LR, /*!< ARM: Pointer authentication instructions that allow signing of LR using SP and PC as diversifiers */
CPU_FEATURE_RME_GPC2, /*!< ARM: RME Granule Protection Check 2 Extension */
CPU_FEATURE_SME_F8F16, /*!< ARM: SME2 ZA-targeting FP8 multiply-accumulate, dot product, and outer product to half-precision instructions */
CPU_FEATURE_SME_F8F32, /*!< ARM: SME2 ZA-targeting FP8 multiply-accumulate, dot product, and outer product to single-precision instructions */
CPU_FEATURE_SME_LUTV2, /*!< ARM: Lookup table instructions with 4-bit indices and 8-bit elements */
CPU_FEATURE_SPMU2, /*!< ARM: System Performance Monitors Extension version 2 */
CPU_FEATURE_SSVE_FP8DOT2, /*!< ARM: SVE FP8 2-way dot product to half-precision instructions in Streaming SVE mode */
CPU_FEATURE_SSVE_FP8DOT4, /*!< ARM: SVE2 FP8 4-way dot product to single-precision instructions in Streaming SVE mode */
CPU_FEATURE_SSVE_FP8FMA, /*!< ARM: SVE2 FP8 multiply-accumulate to half-precision and single-precision instructions in Streaming SVE mode */
CPU_FEATURE_STEP2, /*!< ARM: Enhanced Software Step Extension */
CPU_FEATURE_TLBIW, /*!< ARM: TLBI VMALL for Dirty state */
/* termination: */ /* termination: */
NUM_CPU_FEATURES, NUM_CPU_FEATURES,
} cpu_feature_t; } cpu_feature_t;

6
libcpuid/libcpuid_arm_driver.h
View file

@ -53,9 +53,12 @@
#define AARCH64_REG_ID_AA64AFR1_EL1 "S3_0_C0_C5_5" #define AARCH64_REG_ID_AA64AFR1_EL1 "S3_0_C0_C5_5"
#define AARCH64_REG_ID_AA64DFR0_EL1 "S3_0_C0_C5_0" #define AARCH64_REG_ID_AA64DFR0_EL1 "S3_0_C0_C5_0"
#define AARCH64_REG_ID_AA64DFR1_EL1 "S3_0_C0_C5_1" #define AARCH64_REG_ID_AA64DFR1_EL1 "S3_0_C0_C5_1"
#define AARCH64_REG_ID_AA64DFR2_EL1 "S3_0_C0_C5_2"
#define AARCH64_REG_ID_AA64FPFR0_EL1 "S3_0_C0_C4_7"
#define AARCH64_REG_ID_AA64ISAR0_EL1 "S3_0_C0_C6_0" #define AARCH64_REG_ID_AA64ISAR0_EL1 "S3_0_C0_C6_0"
#define AARCH64_REG_ID_AA64ISAR1_EL1 "S3_0_C0_C6_1" #define AARCH64_REG_ID_AA64ISAR1_EL1 "S3_0_C0_C6_1"
#define AARCH64_REG_ID_AA64ISAR2_EL1 "S3_0_C0_C6_2" #define AARCH64_REG_ID_AA64ISAR2_EL1 "S3_0_C0_C6_2"
#define AARCH64_REG_ID_AA64ISAR3_EL1 "S3_0_C0_C6_3"
#define AARCH64_REG_ID_AA64MMFR0_EL1 "S3_0_C0_C7_0" #define AARCH64_REG_ID_AA64MMFR0_EL1 "S3_0_C0_C7_0"
#define AARCH64_REG_ID_AA64MMFR1_EL1 "S3_0_C0_C7_1" #define AARCH64_REG_ID_AA64MMFR1_EL1 "S3_0_C0_C7_1"
#define AARCH64_REG_ID_AA64MMFR2_EL1 "S3_0_C0_C7_2" #define AARCH64_REG_ID_AA64MMFR2_EL1 "S3_0_C0_C7_2"
@ -95,9 +98,12 @@ typedef enum {
REQ_ID_AA64AFR1, REQ_ID_AA64AFR1,
REQ_ID_AA64DFR0, REQ_ID_AA64DFR0,
REQ_ID_AA64DFR1, REQ_ID_AA64DFR1,
REQ_ID_AA64DFR2,
REQ_ID_AA64FPFR0,
REQ_ID_AA64ISAR0, REQ_ID_AA64ISAR0,
REQ_ID_AA64ISAR1, REQ_ID_AA64ISAR1,
REQ_ID_AA64ISAR2, REQ_ID_AA64ISAR2,
REQ_ID_AA64ISAR3,
REQ_ID_AA64MMFR0, REQ_ID_AA64MMFR0,
REQ_ID_AA64MMFR1, REQ_ID_AA64MMFR1,
REQ_ID_AA64MMFR2, REQ_ID_AA64MMFR2,

5
libcpuid/libcpuid_constants.h
View file

@ -51,8 +51,9 @@
#define MAX_ARM_ID_MMFR_REGS 6 #define MAX_ARM_ID_MMFR_REGS 6
#define MAX_ARM_ID_PFR_REGS 3 #define MAX_ARM_ID_PFR_REGS 3
#define MAX_ARM_ID_AA64AFR_REGS 2 #define MAX_ARM_ID_AA64AFR_REGS 2
#define MAX_ARM_ID_AA64DFR_REGS 2 #define MAX_ARM_ID_AA64DFR_REGS 3
#define MAX_ARM_ID_AA64ISAR_REGS 3 #define MAX_ARM_ID_AA64FPFR_REGS 1
#define MAX_ARM_ID_AA64ISAR_REGS 4
#define MAX_ARM_ID_AA64MMFR_REGS 5 #define MAX_ARM_ID_AA64MMFR_REGS 5
#define MAX_ARM_ID_AA64PFR_REGS 3 #define MAX_ARM_ID_AA64PFR_REGS 3
#define MAX_ARM_ID_AA64SMFR_REGS 1 #define MAX_ARM_ID_AA64SMFR_REGS 1

229
libcpuid/recog_arm.c
View file

@ -2523,6 +2523,235 @@ static void load_arm_features(struct cpu_raw_data_t* raw, struct cpu_id_t* data,
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 } { .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
} }
}, },
[CPU_FEATURE_ASID2] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_4_A,
.ver_mandatory = FEATURE_LEVEL_ARM_V9_5_A,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64mmfr[4], .highbit = 11, .lowbit = 8, .value = 0b0001 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_BWE2] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_4_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64dfr[2], .highbit = 7, .lowbit = 4, .value = 0b0010 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_CPA] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_4_A,
.ver_mandatory = FEATURE_LEVEL_ARM_V9_5_A,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64isar[3], .highbit = 3, .lowbit = 0, .value = 0b0001 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_CPA2] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_4_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64isar[3], .highbit = 3, .lowbit = 0, .value = 0b0001 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_E2H0] = {
.ver_optional = FEATURE_LEVEL_ARM_V8_0_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64mmfr[4], .highbit = 27, .lowbit = 24, .value = 0b0000 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_E3DSE] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_4_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64mmfr[4], .highbit = 39, .lowbit = 36, .value = 0b0001 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_ETS3] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_4_A,
.ver_mandatory = FEATURE_LEVEL_ARM_V9_5_A,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64mmfr[1], .highbit = 39, .lowbit = 36, .value = 0b0011 },
{ .aarch32_reg = &raw->arm_id_mmfr[5], .aarch64_reg = NULL, .highbit = 3, .lowbit = 0, .value = 0b0011 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_FAMINMAX] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_2_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64isar[3], .highbit = 7, .lowbit = 4, .value = 0b0001 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_FGWTE3] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_4_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64mmfr[4], .highbit = 19, .lowbit = 16, .value = 0b0001 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_FP8] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_2_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64fpfr[0], .highbit = 31, .lowbit = 31, .value = 0b1 },
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64fpfr[0], .highbit = 1, .lowbit = 1, .value = 0b1 },
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64fpfr[0], .highbit = 0, .lowbit = 0, .value = 0b1 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_FP8DOT2] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_2_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64fpfr[0], .highbit = 28, .lowbit = 28, .value = 0b1 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_FP8DOT4] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_2_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64fpfr[0], .highbit = 29, .lowbit = 29, .value = 0b1 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_FP8FMA] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_2_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64fpfr[0], .highbit = 30, .lowbit = 30, .value = 0b1 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_FPMR] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_2_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64pfr[2], .highbit = 35, .lowbit = 32, .value = 0b0001 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_HACDBS] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_4_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64mmfr[4], .highbit = 15, .lowbit = 12, .value = 0b0001 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_HDBSS] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_4_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64mmfr[1], .highbit = 3, .lowbit = 0, .value = 0b0100 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_LUT] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_2_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64isar[2], .highbit = 59, .lowbit = 56, .value = 0b0001 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_PAUTH_LR] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_4_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64isar[1], .highbit = 7, .lowbit = 3, .value = 0b0110 },
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64isar[1], .highbit = 11, .lowbit = 8, .value = 0b0110 },
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64isar[2], .highbit = 15, .lowbit = 12, .value = 0b0110 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_RME_GPC2] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_4_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64pfr[0], .highbit = 55, .lowbit = 52, .value = 0b0010 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_SME_F8F16] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_2_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64smfr[0], .highbit = 41, .lowbit = 41, .value = 0b1 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_SME_F8F32] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_2_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64smfr[0], .highbit = 40, .lowbit = 40, .value = 0b1 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_SME_LUTV2] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_2_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64smfr[0], .highbit = 60, .lowbit = 60, .value = 0b1 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_SPMU2] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_4_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64dfr[1], .highbit = 35, .lowbit = 32, .value = 0b0010 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_SSVE_FP8DOT2] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_2_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64smfr[0], .highbit = 28, .lowbit = 28, .value = 0b1 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_SSVE_FP8DOT4] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_2_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64smfr[0], .highbit = 29, .lowbit = 29, .value = 0b1 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_SSVE_FP8FMA] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_2_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64smfr[0], .highbit = 30, .lowbit = 30, .value = 0b1 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_STEP2] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_4_A,
.ver_mandatory = FEATURE_LEVEL_ARM_V9_5_A,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64dfr[2], .highbit = 3, .lowbit = 0, .value = 0b0001 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
[CPU_FEATURE_TLBIW] = {
.ver_optional = FEATURE_LEVEL_ARM_V9_4_A,
.ver_mandatory = -1,
.fields = {
{ .aarch32_reg = NULL, .aarch64_reg = &raw->arm_id_aa64isar[3], .highbit = 11, .lowbit = 8, .value = 0b0001 },
{ .aarch32_reg = NULL, .aarch64_reg = NULL, .highbit = 0, .lowbit = 0, .value = 0 }
}
},
}; };
for (feature = 0; feature < NUM_CPU_FEATURES; feature++) for (feature = 0; feature < NUM_CPU_FEATURES; feature++)

2
tests/arm/armv8a/cortex-a53.test
View file

@ -86,4 +86,4 @@ efficiency
4 4
Apollo Apollo
28-10 nm 28-10 nm
advsimd crc32 doublelock fp bbm advsimd crc32 doublelock fp bbm e2h0

2
tests/arm/armv8a/cortex-a57.test
View file

@ -86,4 +86,4 @@ performance
4 4
Atlas Atlas
28-14 nm 28-14 nm
advsimd crc32 doublelock fp pmull sha1 sha256 bbm advsimd crc32 doublelock fp pmull sha1 sha256 bbm e2h0

2
tests/arm/armv9a/neoverse-n2.test
View file

@ -86,4 +86,4 @@ general
4 4
Perseus Perseus
5 nm 5 nm
advsimd crc32 doublelock pmull sha1 lse rdm fp16 i8mm sha3 sha512 sm3 sm4 sve fcma fpaccombine jscvt pacqarma5 pauth bbm dit dotprod fhm lrcpc2 lse2 bti dpb2 frintts flagm2 mte rng sb ssbs2 bf16 dgh sve2 sve_bitperm sve_pmull128 sve_sha3 sve_sm4 advsimd crc32 doublelock pmull sha1 lse rdm fp16 i8mm sha3 sha512 sm3 sm4 sve fcma fpaccombine jscvt pacqarma5 pauth bbm dit dotprod fhm lrcpc2 lse2 bti dpb2 frintts flagm2 mte rng sb ssbs2 bf16 dgh sve2 sve_bitperm sve_pmull128 sve_sha3 sve_sm4 e2h0

2
tests/create_test.py
View file

@ -14,7 +14,7 @@ def readRawFile():
"basic_cpuid", "ext_cpuid", "intel_fn4", "intel_fn11", "amd_fn8000001dh", # x86 "basic_cpuid", "ext_cpuid", "intel_fn4", "intel_fn11", "amd_fn8000001dh", # x86
"arm_midr", "arm_mpidr", "arm_revidr", # ARM common "arm_midr", "arm_mpidr", "arm_revidr", # ARM common
"arm_id_afr", "arm_id_dfr", "arm_id_isar", "arm_id_mmfr", "arm_id_pfr", # ARM (AArch32) "arm_id_afr", "arm_id_dfr", "arm_id_isar", "arm_id_mmfr", "arm_id_pfr", # ARM (AArch32)
"arm_id_aa64afr", "arm_id_aa64dfr", "arm_id_aa64isar", "arm_id_aa64mmfr", "arm_id_aa64pfr", "arm_id_aa64smfr", "arm_id_aa64zfr" # ARM (AArch64) "arm_id_aa64afr", "arm_id_aa64dfr", "arm_id_aa64fpfr", "arm_id_aa64isar", "arm_id_aa64mmfr", "arm_id_aa64pfr", "arm_id_aa64smfr", "arm_id_aa64zfr" # ARM (AArch64)
] ]
ignore = ["MSR Register"] ignore = ["MSR Register"]
good = False good = False