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DB: add Intel Alder Lake-H, fix Alder Lake-P
According to Wikipedia (https://en.wikipedia.org/wiki/Alder_Lake#Alder_Lake-H), CPU names ending with 'H' or 'HK' are part of 'Alder Lake-H'. Only CPU names ending with 'P' are part of 'Alder Lake-P'
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4 changed files with 12 additions and 8 deletions
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@ -126,6 +126,7 @@ enum _intel_bits_t {
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_H = LBIT( 16 ),
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_K = LBIT( 17 ),
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_X = LBIT( 18 ),
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_P = LBIT( 19 ),
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};
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typedef enum _intel_bits_t intel_bits_t;
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@ -447,10 +447,12 @@ const struct match_entry_t cpudb_intel[] = {
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{ 6, 7, -1, -1, 151, -1, -1, -1, NC, CORE_|_I_|_9|_H|_X, _12xxx, "Alder Lake-HX (Core i9)" },
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{ 6, 7, -1, -1, 151, -1, -1, -1, NC, CORE_|_I_|_7|_H|_X, _12xxx, "Alder Lake-HX (Core i7)" },
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{ 6, 7, -1, -1, 151, -1, -1, -1, NC, CORE_|_I_|_5|_H|_X, _12xxx, "Alder Lake-HX (Core i5)" },
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{ 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_9 , _12xxx, "Alder Lake-P (Core i9)" },
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{ 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_7 , _12xxx, "Alder Lake-P (Core i7)" },
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{ 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_5 , _12xxx, "Alder Lake-P (Core i5)" },
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{ 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_3 , _12xxx, "Alder Lake-P (Core i3)" },
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{ 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_7|_P , _12xxx, "Alder Lake-P (Core i7)" },
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{ 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_5|_P , _12xxx, "Alder Lake-P (Core i5)" },
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{ 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_3|_P , _12xxx, "Alder Lake-P (Core i3)" },
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{ 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_9|_H , _12xxx, "Alder Lake-H (Core i9)" },
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{ 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_7|_H , _12xxx, "Alder Lake-H (Core i7)" },
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{ 6, 10, -1, -1, 154, -1, -1, -1, NC, CORE_|_I_|_5|_H , _12xxx, "Alder Lake-H (Core i5)" },
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/* Raptor Lake CPUs (2022, 13th gen, 7nm) => https://en.wikichip.org/wiki/intel/microarchitectures/raptor_lake */
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{ 6, 7, -1, -1, 183, -1, -1, -1, NC, CORE_|_I_|_9 ,_13xxx, "Raptor Lake-S (Core i9)" },
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@ -737,6 +739,7 @@ static intel_code_and_bits_t get_brand_code_and_bits(struct cpu_id_t* data)
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case 'H': bits |= _H; break;
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case 'K': bits |= _K; break;
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case 'X': bits |= _X; break;
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case 'P': bits |= _P; break;
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}
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}
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}
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@ -1377,7 +1377,7 @@ performance
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1
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0
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128 (non-authoritative)
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Alder Lake-P (Core i7)
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Alder Lake-H (Core i7)
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fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx
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--------------------------------------------------------------------------------
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x86
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@ -1410,5 +1410,5 @@ efficiency
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1
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0
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128 (non-authoritative)
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Alder Lake-P (Core i7)
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Alder Lake-H (Core i7)
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fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx
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@ -1377,7 +1377,7 @@ performance
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1
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0
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128 (non-authoritative)
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Alder Lake-P (Core i9)
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Alder Lake-H (Core i9)
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fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx
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--------------------------------------------------------------------------------
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x86
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@ -1410,5 +1410,5 @@ efficiency
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1
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0
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128 (non-authoritative)
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Alder Lake-P (Core i9)
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Alder Lake-H (Core i9)
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fpu vme de pse tsc msr pae mce cx8 apic mtrr sep pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni pclmul dts64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 xd movbe popcnt aes xsave osxsave avx rdtscp lm lahf_lm abm constant_tsc fma3 f16c rdrand x2apic avx2 bmi1 bmi2 sha_ni rdseed adx
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