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64 commits

Author SHA1 Message Date
wdlkmpx
f26c1151f0 Fix issue with HyperThreading status in old cpus
Early P4 processors come with the HT flag, but that feature
is not enabled.

This makes it work the way it should.
2016-04-24 17:28:16 +00:00
wdlkmpx
fa9640b3a2 tests: add p4 celeron willamette-128
1.8GHz
Specs:
http://www.cpu-world.com/CPUs/Celeron/Intel-Celeron%201800%20-%20RK80531RC033128%20(BX80531P180G128).html
2016-04-24 17:26:44 +00:00
wdlkmpx
75c3c36cbb tests: add intel p4 prescott with HT enabled
This is from a Pentium 4 Prescott 3.20GHz processor
Specs:
http://www.cpu-world.com/CPUs/Pentium_4/Intel-Pentium%204%203.2%20GHz%20-%20RK80546PG0881M%20(BX80546PG3200E).html
2016-04-24 17:26:03 +00:00
wdlkmpx
5f420362c6 P4 Celeron: more precise descriptions
According to wikipedia, cpu-world and some cpu-z screenshots, these processors
do have a code name and it's willamette, northwood, prescott or cedar mill

Signed-off-by: Veselin Georgiev <anrieff@gmail.com>
2016-04-19 00:57:11 +03:00
Veselin Georgiev
4e3b633bee Fix tests due to X0rg's codename changes. 2015-09-13 18:38:59 +03:00
Veselin Georgiev
153a6a7c7d Add support for detecting Xeon Ivy Bridge.
Based on report #7 from the sourceforge bugtrack page.
2015-09-03 09:33:38 +03:00
Veselin Georgiev
94fc6ae36a Modify the table matcher a bit. Put some weights on the different fields.
Priously all fields in the matchtable were treated equal in importance.
With this change, the cache size a taken with half the weight in the decision.

Also add detection entries for some more recent Haswells, and the respective
tests. These are an i5 Haswell from a Mac Book Pro, and a i7 Haswel from
Thinkpad T540.
2015-04-17 01:21:30 +03:00
Veselin Georgiev
046d2ca2ab Better support for AVX, AVX2, BMI1 and BMI2 instruction set detection.
- Detect AVX and AVX2 on both Intel and AMD CPUs
- Detect BMI1 and BMI2 instruction sets (BMI2 is only on Haswell, BMI1 is
  also present on Bulldozers).
- Fix tests to reflect changes.
2015-04-16 20:54:37 +03:00
Veselin Georgiev
fa2083a992 Add support for detecting AVX2. Confirmed to detect on Haswell i3. 2014-09-24 00:03:11 +03:00
Veselin Georgiev
ce02f0bc96 Fix broken tests, where rdtscp in recent Intel chips is missing.
As described in previous commit.
2014-09-23 15:21:02 +03:00
Veselin Georgiev
ece31fb8d3 Add a test for Atom N2800 (codename Cedarview). 2014-08-20 11:25:52 +03:00
Veselin Georgiev
d80ae596ab Fix bogus tests in the Atom category
- Atom Dual-core (Diamondville) is renamed to just Atom (Diamondville)
- The test with Atom D425 is named "Pineview", while the one with
  Atom D525 was incorrectly named "Cedarview". Moving the latter to
  atom-pineview-2.test and fixing its codename.
2014-08-20 11:22:25 +03:00
Veselin Georgiev
f883e2b592 Add recognition support for Haswell i3, i5 and i7.
Add a test based on a Haswell i3 (Core i3-4130).
2014-07-18 21:00:48 +03:00
Veselin Georgiev
019170b65f Refactor the tests: put each test case in a separate file
Instead of one big pile of tests in tests_stash.txt, keep each CPU
example raw data/parsed data in a file, ordered in a tree by
manufacturer and microarchitecture. The 64 .test files have been
extracted from tests_stash.txt. The add_test script is changed to
create_test and it doesn't append to test_stash.txt, instead it
spits out data to be saved in a .test file.

run_tests.py is not refactored yet, to be done in a subsequent commit.
2014-07-15 19:59:35 +03:00