7 commits

Author	SHA1	Message	Date
Xorg	4b06a9a23e	Detect ABM feature on Intel CPUs ... Resolve #144	2020-05-18 21:11:01 +02:00
Xorg	fb1deb1fef	Tests: update all tests to add fields for L1I	2020-05-10 17:02:45 +00:00
Veselin Georgiev	f52c02d394	Update all tests: add fields for L4 cache size, assoc. and line size.	2016-07-07 00:44:45 +03:00
Veselin Georgiev	046d2ca2ab	Better support for AVX, AVX2, BMI1 and BMI2 instruction set detection. ... - Detect AVX and AVX2 on both Intel and AMD CPUs - Detect BMI1 and BMI2 instruction sets (BMI2 is only on Haswell, BMI1 is also present on Bulldozers). - Fix tests to reflect changes.	2015-04-16 20:54:37 +03:00
Veselin Georgiev	fa2083a992	Add support for detecting AVX2. Confirmed to detect on Haswell i3.	2014-09-24 00:03:11 +03:00
Veselin Georgiev	ce02f0bc96	Fix broken tests, where rdtscp in recent Intel chips is missing. ... As described in previous commit.	2014-09-23 15:21:02 +03:00
Veselin Georgiev	f883e2b592	Add recognition support for Haswell i3, i5 and i7. ... Add a test based on a Haswell i3 (Core i3-4130).	2014-07-18 21:00:48 +03:00