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Author SHA1 Message Date
Leslie-Fang
8f91df526d add support to feature intel avx512_vnni 2019-08-08 22:06:23 +08:00
Veselin Georgiev
88d98cedd3
Merge pull request #127 from fastogt/master 
AARCH64 stub
 2019-07-14 21:38:31 +03:00
topilski
b2e5b6ae2e AARCH64 stub 2019-07-13 21:10:34 +03:00
Veselin Georgiev
96810180a0
Merge pull request #126 from X0rg/master 
Fix for Zen 2
 2019-07-12 11:20:06 +03:00
Xorg
eeec951534 Ignore convert_instlatx64 binary 2019-07-11 22:49:29 +02:00
Xorg
848354a3f1 Tests: Add more Matisse CPUs 2019-07-11 22:49:08 +02:00
Xorg
bf7f57f519 Fix SSE unit size for Zen 2 CPUs 
Related to #125
 2019-07-11 22:29:27 +02:00
Veselin Georgiev
ab3bc3defe
Merge pull request #125 from X0rg/master 
More test files for AMD Zen CPUs
 2019-07-11 08:34:24 +03:00
Xorg
5aedd53624 Add more test files for AMD Zen CPUs 
Dumps found on http://instlatx64.atw.hu/
 2019-07-07 20:03:45 +02:00
Xorg
081c354d17 DB: Add AMD Ryzen 3000 2019-07-07 19:38:46 +02:00
Veselin Georgiev
7a0701d452
Merge pull request #123 from hygonsoc/master 
Add Hygon Dhyana support for libcpuid
 2019-04-14 02:16:48 +03:00
hygonsoc
9f0012b74b add Hygon Dhyana C86 7seris test file 
Signed-off-by: hygonsoc <hygonsoc@gmail.com>
 2019-04-13 23:08:41 +08:00
hygonsoc
8c0a01890c Add Hygon Dhyana detect support 
Signed-off-by: hygonsoc <hygonsoc@gmail.com>
 2019-04-13 23:08:03 +08:00
Veselin Georgiev
1168b8dd68
Merge pull request #121 from X0rg/master 
Minor fixes for RDMSR
 2019-02-18 06:42:06 +02:00
Xorg
c683dfb084 RDMSR: Replace unsafe sprintf() by safe snprintf() 2019-02-17 15:41:44 +01:00
Xorg
32d1ac4aff RDMSR: Fix minor mistake in msr_serialize_raw_data() 
- Allow to set filename as NULL
- Replace printf() by fprintf()
- Use a switch case instead multiple if statements
 2019-02-17 15:26:44 +01:00
Veselin Georgiev
a6123e8139 Fixed issue #105: New Release version 
The version is 0.4.1 (instead of suggested 0.5.0) since it
introduces no backwards-incompatible changes.

Only version is actually changed, no code modifications.
 2019-02-05 22:43:52 +02:00
Veselin Georgiev
84423b63b9
Merge pull request #120 from X0rg/master 
Fix Ryzen core count calculation
 2018-11-04 23:25:46 +02:00
Xorg
92d3a77105 RDMSR: Fix casts in get_amd_multipliers() 
Resolves #94
 2018-11-04 17:13:58 +01:00
Xorg
3a8343c77c Fix Ryzen core count calculation 
Close X0rg/CPU-X#86
 2018-11-03 21:30:01 +01:00
Veselin Georgiev
c5a0e9fd63
Merge pull request #119 from X0rg/master 
Improve AMD database
 2018-10-23 07:40:02 +03:00
Xorg
bd44d509c9 Add more amd_bits_t 
- Improve cpudb_amd[] (Zen part)
- Improve decode_amd_codename_part1()
- Detection of AMD EPYC (Naples)
 2018-10-22 23:22:12 +02:00
Veselin Georgiev
3a82b47b1f
Merge pull request #118 from X0rg/master 
Update CPUs database
 2018-10-22 18:17:02 +03:00
Xorg
ee32a4a735 DB: Add missing patterns in decode_amd_ryzen_model_code() 
Forgotten in d8a273f17a
 2018-10-21 09:59:15 +02:00
Xorg
5187986bd1 DB: Add more Coffee Lake 
Coffee Lake S: https://en.wikichip.org/wiki/intel/cores/coffee_lake_s#Coffee_Lake_S_Processors
Coffee Lake Refresh: https://en.wikichip.org/wiki/intel/cores/coffee_lake_r
 2018-10-21 09:36:07 +02:00
Xorg
bbafbb7ac4 DB: Add Zen+ Threadripper (Colfax) 
https://en.wikichip.org/wiki/amd/cores/colfax#Colfax_Processors
 2018-10-21 09:15:21 +02:00
Xorg
62405e235c DB: Fix Threadripper codename 
According to WikiChip, Whitehaven is used for Ryzen Threadripper
https://en.wikichip.org/wiki/amd/cores/whitehaven
 2018-10-21 09:09:12 +02:00
Xorg
21c5d3512b DB: Add more Pinnacle Ridge 
https://en.wikichip.org/wiki/amd/cores/pinnacle_ridge#Pinnacle_Ridge_Processors
 2018-10-21 08:57:29 +02:00
Xorg
d8a273f17a DB: Add more Raven Ridge 
https://en.wikichip.org/wiki/amd/cores/raven_ridge#Raven_Ridge_Processors
 2018-10-21 08:55:35 +02:00
Veselin Georgiev
e91eeaf995
Merge pull request #117 from X0rg/master 
Detect Kaby Lake-U
 2018-09-28 02:02:45 +03:00
Xorg
7358232cc4 DB: Add Kaby Lake-U 2018-09-23 22:06:53 +02:00
Veselin Georgiev
ebf912d671
Merge pull request #116 from X0rg/master 
Detect Skylake-X
 2018-08-09 13:05:13 +03:00
Xorg
218015a983 Tests: Add Pentium 4405U 2018-08-08 15:02:08 +02:00
Xorg
9c382e33b3 DB: Add Skylake-X CPUs 2018-08-08 14:51:38 +02:00
Xorg
c2645d0dff Force Python 2.7 in all Python scripts 
/usr/bin/python is Python 3.7 on Arch Linux, so it doesn't work
 2018-08-08 13:54:14 +02:00
Veselin Georgiev
7faea1ace8 Fix issue #115: INLINE_ASM_SUPPORTED Visual Studio x86 
Reintroduce the INLINE_ASM_SUPPORTED macro for MSVC/x86
 2018-07-22 03:55:28 +03:00
Veselin Georgiev
0d09f3caf2
Merge pull request #113 from proller/master 
Use linux line endings for  asm-bits.c, asm-bits.h and msrdriver.c
 2018-06-25 10:17:48 +03:00
Veselin Georgiev
aae06ecb7a
Merge pull request #114 from orivej/stdint 
Do not depend on config.h in public headers
 2018-06-25 10:12:54 +03:00
Orivej Desh
1331b6e9b8 Do not depend on config.h in public headers 
config.h is not installed with libcpuid, and even if it were HAVE_CONFIG_H could
not be used to check for its availability.
 2018-06-23 17:56:52 +00:00
proller
3756db41b0 Also msrdriver.c 2018-06-21 21:22:52 +03:00
proller
4d4eeb6893 Use linux line endings for asm-bits.c asm-bits.h 2018-06-21 20:19:27 +03:00
Veselin Georgiev
05c8078d25
Merge pull request #112 from fastogt/master 
Clang + stubs for arm
 2018-05-18 00:13:27 +03:00
topilski
7d8819905f Less warnings 2018-05-17 09:19:14 +03:00
topilski
7e92710d7c Review 2018-05-17 08:50:42 +03:00
Veselin Georgiev
45d04a9e4a Fix P-III Celeron misdetected as plain P-III (misreport id #8) 
Reported via http://libcpuid.sourceforge.net/bugreport.php
The test in particular has no brand string, which was causing the
misdetection (as is the case with a lot of other models, libcpuid
relies on accurate brand string being programmed by the BIOS in
order to do the detection).

The actual CPU was a Pentium-III based Celeron (SL54Q), but it
was detected as "Pentium III (Coppermine)".

A bit of historical trivia: for the related Tualatin models, if
the BIOS doesn't enter a brand string, there might be NO WAY to
tell a regular P-3 and a P-3 Celeron apart: P-3s have variants
with 256KiB and 512KiB L2 cache, while the Celerons are 256 KiB, so
a 256KiB regular P3 is no different than its corresponding Celeron.
Only the FSB is different, but there's no way to detect this via
CPUID.

For the Coppermines its an easier case: Celerons are always 128KiB,
and Pentia are 256KiB, so I've added this distinction in the tables.
 2018-05-02 11:05:25 +03:00
Veselin Georgiev
671fa8a750
Merge pull request #111 from X0rg/master 
DB: Add Pinnable Ridge CPUs
 2018-04-24 08:25:13 +03:00
Xorg
4e4ccb9d1d DB: Add Pinnable Ridge CPUs 2018-04-23 21:05:47 +02:00
Veselin Georgiev
c86fd1d0be
Merge pull request #110 from themusicgod1/master 
lintian + qemu
 2018-04-23 21:17:53 +03:00
anonymous
d35968e8b7 suggested corrections - argument order & removal of ? 2018-04-23 17:19:24 +00:00
anonymous
53bcf98c0f Merge http://github.com/themusicgod1/libcpuid 2018-04-21 23:19:26 -04:00