7 commits

Author	SHA1	Message	Date
Veselin Georgiev	87f3052a7b	Add a test with L4 cache (courtesy of @phprus). ... The test is a snapshot of a Haswell i7 (a.k.a. "Crystalwell") core. This is the only test in the test DB right now which has lines for L4 cache size, associativity and cacheline size different than "-1". Also update create_test.py to accommodate for the new fields.	2016-07-07 00:53:03 +03:00
Veselin Georgiev	f52c02d394	Update all tests: add fields for L4 cache size, assoc. and line size.	2016-07-07 00:44:45 +03:00
Veselin Georgiev	94fc6ae36a	Modify the table matcher a bit. Put some weights on the different fields. ... Priously all fields in the matchtable were treated equal in importance. With this change, the cache size a taken with half the weight in the decision. Also add detection entries for some more recent Haswells, and the respective tests. These are an i5 Haswell from a Mac Book Pro, and a i7 Haswel from Thinkpad T540.	2015-04-17 01:21:30 +03:00
Veselin Georgiev	046d2ca2ab	Better support for AVX, AVX2, BMI1 and BMI2 instruction set detection. ... - Detect AVX and AVX2 on both Intel and AMD CPUs - Detect BMI1 and BMI2 instruction sets (BMI2 is only on Haswell, BMI1 is also present on Bulldozers). - Fix tests to reflect changes.	2015-04-16 20:54:37 +03:00
Veselin Georgiev	fa2083a992	Add support for detecting AVX2. Confirmed to detect on Haswell i3.	2014-09-24 00:03:11 +03:00
Veselin Georgiev	ce02f0bc96	Fix broken tests, where rdtscp in recent Intel chips is missing. ... As described in previous commit.	2014-09-23 15:21:02 +03:00
Veselin Georgiev	f883e2b592	Add recognition support for Haswell i3, i5 and i7. ... Add a test based on a Haswell i3 (Core i3-4130).	2014-07-18 21:00:48 +03:00