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535 commits

Author SHA1 Message Date
Veselin Georgiev
58569cb77b Ignore .vcxproj.user files generated by MSVS2010. 2016-07-10 03:00:20 +02:00
Veselin Georgiev
c9ff6036a2 Ignore build directories for the VC10 projects. 2016-07-10 02:59:23 +02:00
Veselin Georgiev
bb9f03f2ba Replace VC9 project files with improved ones for VC10.
The new project files are for Microsoft Visual Studio 2010.

The configurations now support building both 32- and 64-bit targets,
and the "Release DLL" target is supported much like in the vc71 project.

The output layout is as follows:

32-bit, Debug static library goes to libcpuid/x32/Debug
32-bit, Release static library goes to libcpuid/x32/Release
32-bit, DLL (only release) goes to libcpuid/x32/ReleaseDLL. It includes
the .dll and the export library .lib as well.
64-bit DLL goes to libcpuid/x64/ReleaseDLL.

and so forth.
2016-07-10 02:51:23 +02:00
Veselin Georgiev
1b1e858df4 Ignore temp/local files by MSVS2010. 2016-07-10 02:24:21 +02:00
Veselin Georgiev
647d737db8 Set version to 0.3.0 in libcpuid.h, update release date. 2016-07-09 06:54:07 +03:00
Veselin Georgiev
91dad77e6e Similar to the previous commit: additions to the VC9 project file. 2016-07-09 06:53:12 +03:00
Veselin Georgiev
03d54ae61c Port to MSVC7.1: C89 compliance and project updates. 2016-07-09 05:48:35 +03:00
Veselin Georiev
568db71156 Fix a bunch of warnings (emitted from MSVC). 2016-07-09 05:24:12 +03:00
Veselin Georiev
296b1efe7a Rename ATOM enum value as it clashes with some Windows headers. 2016-07-09 05:24:12 +03:00
Veselin Georgiev
87f3052a7b Add a test with L4 cache (courtesy of @phprus).
The test is a snapshot of a Haswell i7 (a.k.a. "Crystalwell") core.
This is the only test in the test DB right now which has lines for
L4 cache size, associativity and cacheline size different than "-1".

Also update create_test.py to accommodate for the new fields.
2016-07-07 00:53:03 +03:00
Veselin Georgiev
f52c02d394 Update all tests: add fields for L4 cache size, assoc. and line size. 2016-07-07 00:44:45 +03:00
Veselin Georgiev
612d2135f6 Merge pull request #49 from X0rg/master
Fix & Athlon 64 FX X2
2016-06-16 12:44:12 +01:00
Xorg
298539b4b0 Add Athlon 64 FX X2 (Toledo) in database 2016-06-16 12:58:42 +02:00
Xorg
bc84f0c71d cpu_msrinfo(): Fix value of CPU_INVALID_VALUE in 'double' subfunctions
It returns 0x7FFFFFFF instead of 0x3FFFFFFF
0x3FFFFFFF is a 29-bit value, but become a 36-bit value when multiplied by 100, causing a value out-of-range
2016-06-16 12:40:41 +02:00
Xorg
c64f8bcc60 Ignore more files in repo 2016-06-16 12:22:04 +02:00
Veselin Georgiev
3f51d3ca25 Add detection of L4 cache. 2016-06-09 15:42:57 +03:00
Veselin Georgiev
571fe75d88 Remove redundant MSRINFO_DEFINED macro. 2016-06-06 11:38:40 +03:00
Veselin Georgiev
24d7c318d0 Resolve warnings on Mac OS X. 2016-06-06 01:50:05 +03:00
Veselin Georgiev
dbf9991553 Merge pull request #48 from X0rg/master
MSRs rework and man-pages
2016-06-05 14:39:57 +01:00
Xorg
ec445b0a54 Add load_driver() support for GNU/Linux & FreeBSD in cpu_msr_driver_open_core() 2016-06-05 14:10:19 +02:00
Xorg
023f0307f0 Minor changes for cpu_msrinfo() 2016-06-05 13:16:15 +02:00
Veselin Georgiev
7320ee9f29 Change configure.ac AGE (as per the comments in issue #46).
The new library generated under linux is libcpuid.so.13.0.0, which
makes it clear it's binary incompatible with the old version
(libcpuid.so.11.1.2).
2016-06-05 13:57:06 +03:00
Xorg
462ec75c79 Fix Doxygen warnings, don't warn if undocmented 2016-06-05 12:19:49 +02:00
Xorg
8fda5a74f1 Generate and install man-pages if Doxygen is installed 2016-06-05 12:09:59 +02:00
Xorg
240a862c45 Fix warnings
recog_intel.c:589:22: warning: implicit conversion from enumeration type 'enum _common_codes_t' to different enumeration type 'intel_code_t' (aka 'enum _intel_code_t')
recog_amd.c:449:9: warning: implicit conversion from enumeration type 'enum _common_codes_t' to different enumeration type 'amd_code_t' (aka 'enum _amd_code_t')
2016-06-05 11:07:00 +02:00
Xorg
cba9a1e19a Replace hardcoded addresses by define in cpu_msrinfo() 2016-06-04 20:52:27 +02:00
Xorg
e631e62ce6 Silent rules in configure.ac
Less useless output to easily see warnings
2016-06-04 20:36:58 +02:00
Xorg
9059fb6ff5 Add INFO_BUS_CLOCK in cpu_msrinfo() as a more generic term (same as INFO_BCLK)
BCLK is specific to Intel
2016-06-04 20:31:01 +02:00
Xorg
eeb7a6f3c7 Report CPU minimum multiplier (INFO_MIN_MULTIPLIER) in cpu_msrinfo() 2016-06-04 20:11:09 +02:00
Xorg
24cd11fea9 In cpu_msrinfo(), add experimental support for AMD CPUs for INFO_CUR_MULTIPLIER, INFO_MAX_MULTIPLIER and INFO_BCLK
get_amd_multipliers() allow to share a maximum of code
2016-06-04 19:50:21 +02:00
Xorg
14cfc77b17 Improve/clean code for cpu_msrinfo()
* Add AMD and Intel doc links
* Use 'return' only if there is no error; on error, the end-function 'return CPU_INVALID_VALUE' is used
* Add more comments about MSRs
* Simplify a lot of things
* Avoid cpu_rdmsr_range() to override cpu_rdmsr() error
* Remove int casting in cpu_msrinfo()
2016-06-04 17:51:48 +02:00
Xorg
8fc0cc0d4a Use internal code for MSR, replace cpuid_get_vendor() by id->vendor 2016-06-04 14:13:24 +02:00
Xorg
1ef4615d8f Use cpu_id_t in cpu_msrinfo()
It can be useful to have more informations on CPU
2016-06-04 13:16:41 +02:00
Veselin Georgiev
5f99a4528c Change version to 0.3.0 throughout the project. Update ChangeLog. 2016-06-03 21:15:37 +03:00
Xorg
5467504680 Use cpu_ident_internal() in cpu_msrinfo() 2016-06-03 15:58:45 +02:00
Xorg
93cdd0de75 Merge upstream changes
Conflicts:
	libcpuid/rdmsr.c
2016-06-03 14:36:24 +02:00
Veselin Georgiev
c31b5c0ae8 Add up to 8 entries for CPUID leaf 04; push version to 0.3.0.
This is a backwards-incompatible binary change, which increases
sizeof(cpu_raw_data_t). Specifically, the cpu_raw_data_t::intel_fn4
array is increased from 4 to 8 elements, because on recent Hasells
(Crystalwell) there is a Level 4 cache, which should be encoded in
CPUID eax=4 ecx=4. However, we were only storing levels for eax=4
for ecx <= 3. Thus the raw data didn't have the relevant info.

There will be further changes to this, specifically to store
and print the level 4 cache in cpuid_tool.
2016-06-03 04:35:01 +03:00
Veselin Georgiev
3f36114b19 Fix a few legit warnings (passing 'int*', where 'uint64*' is expected). 2016-06-03 03:34:08 +03:00
Veselin Georgiev
a2550463a9 Reorganize library a bit.
- Expose intel_code_t and amd_code_t enums - they are no longer
  limited to just recog_{intel,amd}.c.
- Add libcpuid_internal.h lists those enums and provides the,
  cpu_ident_internal() function, which is the same as cpu_identify(),
  but also has a third parameter - a internal_id_info_t structure,
  which holds detection internals.

All of this is intended to be used in rdmsr, which needs to know
specifics on what CPU it is running.
2016-06-03 03:30:36 +03:00
Xorg
77575736dd Move code from cpu_msrinfo() in subfunctions 2016-05-27 14:02:24 +02:00
Veselin Georgiev
86cf1df62c Update Readme.md with documentation links. 2016-05-22 23:35:30 +03:00
Veselin Georgiev
7fd52f01d6 Ignore generated Doxyfile. 2016-05-22 23:22:57 +03:00
Veselin Georgiev
db65e9a6b0 Fix a few Doxygen warnings and errors. Beautify docs a bit.
Also rename Doxyfile to Doxyfile.in, add it in configure and replace
version and pathspec in it with macros.
2016-05-22 23:20:16 +03:00
Veselin Georgiev
8c629d76b4 Fix minor issues with comments/documentation.
Also add a comment about the upcoming version 0.2.3. A date is not
stated, as this will be done when the actual release happens (and
I will collect any further patches up to that moment). I expect the
release to be over the next weekend.
2016-05-22 22:52:58 +03:00
Veselin Georgiev
00f349a7a3 Fix issue #45: OS X compilation error 2016-05-21 16:10:39 +03:00
Veselin Georgiev
7c7a0fea8b Merge pull request #43 from X0rg/master
Changes for MSR
2016-05-19 22:09:51 +01:00
Xorg
b067c68073 Use unsigned type instead of uint8_t as parameter for cpu_msr_driver_open_core() 2016-05-19 08:46:19 +02:00
Veselin Georgiev
14d6a9d875 Fix cpu_clock_by_ic() for Skylake (it was 1.6 times too high).
The reason and fix is similar to what we did previously for Bulldozer.
2016-05-19 01:37:45 +03:00
Veselin Georgiev
7b9fe29cef Support for Skylake.
- Detection of hle, rtm, avx512* and sha-ni instructions
- Detection for Skylake
- Add test with Skylake i5
2016-05-19 01:37:45 +03:00
Veselin Georgiev
3a977a4f99 Add detection support for the AMD TBM instructions. Update Vishera test. 2016-05-19 01:37:45 +03:00