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648 commits

Author SHA1 Message Date
Xorg
faf958c3c9
DB: add Cannon Lake CPUs 2020-05-09 13:28:11 +02:00
Xorg
af5019acec
DB: clarify Intel Generations 2020-05-09 13:02:26 +02:00
Veselin Georgiev
9d22c61611
Merge pull request #141 from X0rg/master
Fixes for AMD Zen 2 CPUs
2020-05-04 21:35:42 +03:00
Xorg
46e86331bb
tests: remove duplicate addresses in RAW part 2020-05-03 17:12:33 +02:00
Xorg
afbd7ae56d
tests: fix convert_instlatx64 tool 2020-05-03 17:09:54 +02:00
Xorg
848394ee46
Fix L3 cache associativity detection on AMD Zen 2 CPUs 2020-05-03 17:07:43 +02:00
Veselin Georgiev
f2ab8b7ef2
Merge pull request #139 from kreuzerkrieg/Fix_Win_x64_Build
Fix Win64 build
2020-02-12 00:11:27 +02:00
kreuzerkrieg
f729a74b41 Fix CMake 2020-02-11 12:29:31 +02:00
Veselin Georgiev
5f6a9bf5b0
Merge pull request #138 from kreuzerkrieg/AddCMake
Add CMake support
2020-02-06 11:22:54 +02:00
kreuzerkrieg
9eacb1a36e Add CMake 2020-02-06 11:12:29 +02:00
kreuzerkrieg
12de298ff7 Add CMake 2020-02-06 10:32:25 +02:00
Veselin Georgiev
7b360635aa
Merge pull request #137 from eloaders/master
DB: Add Threadripper (Castle Peak)
2020-01-02 21:12:19 +02:00
eloaders
5f7f3c26cc DB: Add Threadripper (Castle Peak) 2019-12-31 10:58:20 +01:00
Veselin Georgiev
a7d14afb61
Merge pull request #132 from enzo1982/arch
Fix compilation on non-x86/ARM architectures.
2019-10-29 22:07:32 +02:00
Veselin Georgiev
37fabe8dd8
Merge pull request #131 from enzo1982/haiku
Add support for get_total_cpus on Haiku.
2019-10-29 22:06:30 +02:00
Robert Kausch
67d18833c4 Fix compilation on non-x86/ARM architectures. 2019-10-29 20:49:08 +01:00
Robert Kausch
2159f73eaa Add support for get_total_cpus on Haiku. 2019-10-29 20:38:55 +01:00
Veselin Georgiev
69ed754010
Merge pull request #130 from sunweaver/pr/some-typo-fixes
Some typo fixes in human readable text.
2019-10-01 18:06:45 +03:00
Mike Gabriel
47418f1e71 Some typo fixes in human readable text. 2019-10-01 13:04:01 +02:00
Veselin Georgiev
f6e4e23796 Add Xeon CLX (Cascade lake-based) using data from PR #129
Kudos to Leslie-Fang for providing it!
2019-08-09 11:18:20 +03:00
Veselin Georgiev
c4c86835a0
Merge pull request #129 from Leslie-Fang/master
add support to feature intel avx512_vnni
2019-08-09 11:12:03 +03:00
Leslie-Fang
8f91df526d add support to feature intel avx512_vnni 2019-08-08 22:06:23 +08:00
Veselin Georgiev
88d98cedd3
Merge pull request #127 from fastogt/master
AARCH64 stub
2019-07-14 21:38:31 +03:00
topilski
b2e5b6ae2e AARCH64 stub 2019-07-13 21:10:34 +03:00
Veselin Georgiev
96810180a0
Merge pull request #126 from X0rg/master
Fix for Zen 2
2019-07-12 11:20:06 +03:00
Xorg
eeec951534 Ignore convert_instlatx64 binary 2019-07-11 22:49:29 +02:00
Xorg
848354a3f1 Tests: Add more Matisse CPUs 2019-07-11 22:49:08 +02:00
Xorg
bf7f57f519 Fix SSE unit size for Zen 2 CPUs
Related to #125
2019-07-11 22:29:27 +02:00
Veselin Georgiev
ab3bc3defe
Merge pull request #125 from X0rg/master
More test files for AMD Zen CPUs
2019-07-11 08:34:24 +03:00
Xorg
5aedd53624 Add more test files for AMD Zen CPUs
Dumps found on http://instlatx64.atw.hu/
2019-07-07 20:03:45 +02:00
Xorg
081c354d17 DB: Add AMD Ryzen 3000 2019-07-07 19:38:46 +02:00
Veselin Georgiev
7a0701d452
Merge pull request #123 from hygonsoc/master
Add Hygon Dhyana support for libcpuid
2019-04-14 02:16:48 +03:00
hygonsoc
9f0012b74b add Hygon Dhyana C86 7seris test file
Signed-off-by: hygonsoc <hygonsoc@gmail.com>
2019-04-13 23:08:41 +08:00
hygonsoc
8c0a01890c Add Hygon Dhyana detect support
Signed-off-by: hygonsoc <hygonsoc@gmail.com>
2019-04-13 23:08:03 +08:00
Veselin Georgiev
1168b8dd68
Merge pull request #121 from X0rg/master
Minor fixes for RDMSR
2019-02-18 06:42:06 +02:00
Xorg
c683dfb084 RDMSR: Replace unsafe sprintf() by safe snprintf() 2019-02-17 15:41:44 +01:00
Xorg
32d1ac4aff RDMSR: Fix minor mistake in msr_serialize_raw_data()
- Allow to set filename as NULL
- Replace printf() by fprintf()
- Use a switch case instead multiple if statements
2019-02-17 15:26:44 +01:00
Veselin Georgiev
a6123e8139 Fixed issue #105: New Release version
The version is 0.4.1 (instead of suggested 0.5.0) since it
introduces no backwards-incompatible changes.

Only version is actually changed, no code modifications.
2019-02-05 22:43:52 +02:00
Veselin Georgiev
84423b63b9
Merge pull request #120 from X0rg/master
Fix Ryzen core count calculation
2018-11-04 23:25:46 +02:00
Xorg
92d3a77105 RDMSR: Fix casts in get_amd_multipliers()
Resolves #94
2018-11-04 17:13:58 +01:00
Xorg
3a8343c77c Fix Ryzen core count calculation
Close X0rg/CPU-X#86
2018-11-03 21:30:01 +01:00
Veselin Georgiev
c5a0e9fd63
Merge pull request #119 from X0rg/master
Improve AMD database
2018-10-23 07:40:02 +03:00
Xorg
bd44d509c9 Add more amd_bits_t
- Improve cpudb_amd[] (Zen part)
- Improve decode_amd_codename_part1()
- Detection of AMD EPYC (Naples)
2018-10-22 23:22:12 +02:00
Veselin Georgiev
3a82b47b1f
Merge pull request #118 from X0rg/master
Update CPUs database
2018-10-22 18:17:02 +03:00
Xorg
ee32a4a735 DB: Add missing patterns in decode_amd_ryzen_model_code()
Forgotten in d8a273f17a
2018-10-21 09:59:15 +02:00
Xorg
5187986bd1 DB: Add more Coffee Lake
Coffee Lake S: https://en.wikichip.org/wiki/intel/cores/coffee_lake_s#Coffee_Lake_S_Processors
Coffee Lake Refresh: https://en.wikichip.org/wiki/intel/cores/coffee_lake_r
2018-10-21 09:36:07 +02:00
Xorg
bbafbb7ac4 DB: Add Zen+ Threadripper (Colfax)
https://en.wikichip.org/wiki/amd/cores/colfax#Colfax_Processors
2018-10-21 09:15:21 +02:00
Xorg
62405e235c DB: Fix Threadripper codename
According to WikiChip, Whitehaven is used for Ryzen Threadripper
https://en.wikichip.org/wiki/amd/cores/whitehaven
2018-10-21 09:09:12 +02:00
Xorg
21c5d3512b DB: Add more Pinnacle Ridge
https://en.wikichip.org/wiki/amd/cores/pinnacle_ridge#Pinnacle_Ridge_Processors
2018-10-21 08:57:29 +02:00
Xorg
d8a273f17a DB: Add more Raven Ridge
https://en.wikichip.org/wiki/amd/cores/raven_ridge#Raven_Ridge_Processors
2018-10-21 08:55:35 +02:00