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Author SHA1 Message Date
Xorg
ee32a4a735 DB: Add missing patterns in decode_amd_ryzen_model_code() 
Forgotten in d8a273f17a
 2018-10-21 09:59:15 +02:00
Xorg
5187986bd1 DB: Add more Coffee Lake 
Coffee Lake S: https://en.wikichip.org/wiki/intel/cores/coffee_lake_s#Coffee_Lake_S_Processors
Coffee Lake Refresh: https://en.wikichip.org/wiki/intel/cores/coffee_lake_r
 2018-10-21 09:36:07 +02:00
Xorg
bbafbb7ac4 DB: Add Zen+ Threadripper (Colfax) 
https://en.wikichip.org/wiki/amd/cores/colfax#Colfax_Processors
 2018-10-21 09:15:21 +02:00
Xorg
62405e235c DB: Fix Threadripper codename 
According to WikiChip, Whitehaven is used for Ryzen Threadripper
https://en.wikichip.org/wiki/amd/cores/whitehaven
 2018-10-21 09:09:12 +02:00
Xorg
21c5d3512b DB: Add more Pinnacle Ridge 
https://en.wikichip.org/wiki/amd/cores/pinnacle_ridge#Pinnacle_Ridge_Processors
 2018-10-21 08:57:29 +02:00
Xorg
d8a273f17a DB: Add more Raven Ridge 
https://en.wikichip.org/wiki/amd/cores/raven_ridge#Raven_Ridge_Processors
 2018-10-21 08:55:35 +02:00
Veselin Georgiev
e91eeaf995
Merge pull request #117 from X0rg/master 
Detect Kaby Lake-U
 2018-09-28 02:02:45 +03:00
Xorg
7358232cc4 DB: Add Kaby Lake-U 2018-09-23 22:06:53 +02:00
Veselin Georgiev
ebf912d671
Merge pull request #116 from X0rg/master 
Detect Skylake-X
 2018-08-09 13:05:13 +03:00
Xorg
218015a983 Tests: Add Pentium 4405U 2018-08-08 15:02:08 +02:00
Xorg
9c382e33b3 DB: Add Skylake-X CPUs 2018-08-08 14:51:38 +02:00
Xorg
c2645d0dff Force Python 2.7 in all Python scripts 
/usr/bin/python is Python 3.7 on Arch Linux, so it doesn't work
 2018-08-08 13:54:14 +02:00
Veselin Georgiev
7faea1ace8 Fix issue #115: INLINE_ASM_SUPPORTED Visual Studio x86 
Reintroduce the INLINE_ASM_SUPPORTED macro for MSVC/x86
 2018-07-22 03:55:28 +03:00
Veselin Georgiev
0d09f3caf2
Merge pull request #113 from proller/master 
Use linux line endings for  asm-bits.c, asm-bits.h and msrdriver.c
 2018-06-25 10:17:48 +03:00
Veselin Georgiev
aae06ecb7a
Merge pull request #114 from orivej/stdint 
Do not depend on config.h in public headers
 2018-06-25 10:12:54 +03:00
Orivej Desh
1331b6e9b8 Do not depend on config.h in public headers 
config.h is not installed with libcpuid, and even if it were HAVE_CONFIG_H could
not be used to check for its availability.
 2018-06-23 17:56:52 +00:00
proller
3756db41b0 Also msrdriver.c 2018-06-21 21:22:52 +03:00
proller
4d4eeb6893 Use linux line endings for asm-bits.c asm-bits.h 2018-06-21 20:19:27 +03:00
Veselin Georgiev
05c8078d25
Merge pull request #112 from fastogt/master 
Clang + stubs for arm
 2018-05-18 00:13:27 +03:00
topilski
7d8819905f Less warnings 2018-05-17 09:19:14 +03:00
topilski
7e92710d7c Review 2018-05-17 08:50:42 +03:00
Veselin Georgiev
45d04a9e4a Fix P-III Celeron misdetected as plain P-III (misreport id #8) 
Reported via http://libcpuid.sourceforge.net/bugreport.php
The test in particular has no brand string, which was causing the
misdetection (as is the case with a lot of other models, libcpuid
relies on accurate brand string being programmed by the BIOS in
order to do the detection).

The actual CPU was a Pentium-III based Celeron (SL54Q), but it
was detected as "Pentium III (Coppermine)".

A bit of historical trivia: for the related Tualatin models, if
the BIOS doesn't enter a brand string, there might be NO WAY to
tell a regular P-3 and a P-3 Celeron apart: P-3s have variants
with 256KiB and 512KiB L2 cache, while the Celerons are 256 KiB, so
a 256KiB regular P3 is no different than its corresponding Celeron.
Only the FSB is different, but there's no way to detect this via
CPUID.

For the Coppermines its an easier case: Celerons are always 128KiB,
and Pentia are 256KiB, so I've added this distinction in the tables.
 2018-05-02 11:05:25 +03:00
Veselin Georgiev
671fa8a750
Merge pull request #111 from X0rg/master 
DB: Add Pinnable Ridge CPUs
 2018-04-24 08:25:13 +03:00
Xorg
4e4ccb9d1d DB: Add Pinnable Ridge CPUs 2018-04-23 21:05:47 +02:00
Veselin Georgiev
c86fd1d0be
Merge pull request #110 from themusicgod1/master 
lintian + qemu
 2018-04-23 21:17:53 +03:00
anonymous
d35968e8b7 suggested corrections - argument order & removal of ? 2018-04-23 17:19:24 +00:00
anonymous
53bcf98c0f Merge http://github.com/themusicgod1/libcpuid 2018-04-21 23:19:26 -04:00
anonymous
d9c4769c44 fixed lintian errors - changed section, fixed doxygen building of manpage 2018-04-21 23:18:19 -04:00
anonymous
a9c739d312 virtual machine test 2018-04-21 01:00:30 +00:00
Veselin Georgiev
aa28586183 Fix issue #108: Hints for building on NetBSD 
Add @brucelilly's suggestions to the Readme
 2018-04-16 10:45:15 +03:00
Veselin Georgiev
e93afea7f2
Merge pull request #106 from X0rg/master 
DB: Add Raven Ridge APUs and Threadripper CPUs
 2018-03-21 00:08:29 +02:00
Xorg
f1e1ad58e7 DB: Add Raven Ridge APUs and Threadripper CPUs 2018-03-20 19:52:40 +01:00
Veselin Georgiev
f178de98f3 Fix issue #104: Intel Coffee Lake and Kaby Lake 
Add support for detecting Coffee Lake i[357]s. Test included.
Thanks to @X0rg for reporting and to @exdeus for the raw cpu data.

The detection here relies on Kaby and Coffee lakes having different
number of cores for the equivalent brand:

i3: 2 cores in Kaby, 4 in Coffee
i5 and i7: 4 cores in Kaby, 6 in Coffee.
 2018-02-04 13:37:36 +02:00
Veselin Georgiev
2f4c21e3a7 Fixed issue #103: Intel Xeon Scalable not recognised "code name". 
Table entry added, test added, thanks to @phprus for reporting.
 2018-01-28 02:06:37 +02:00
Veselin Georgiev
2f1031543c Fix issue #101: Package should not use obsolete m4 macros 2017-10-23 16:59:57 +03:00
Veselin Georgiev
57298c650c Merge pull request #93 from X0rg/master 
Fixes for #91
 2017-05-04 13:36:19 +01:00
Xorg
dd702cd253 RDMSR: enhance AMD APUs detection 
As suggested in #91
 2017-05-04 07:32:02 +02:00
Xorg
f8c7ee44e0 RDMSR: Use SVI2 step for AMD family 15h model 10h and above 2017-05-04 07:22:33 +02:00
Veselin Georgiev
98661492af Related to #91: Make bits available in libcpuid_internal.h 
Along with some interop changes, as the Intel/AMD bits were sometimes
very similar or totally coinciding.
 2017-05-04 03:51:41 +03:00
Veselin Georgiev
a196e8d1bf Related to #91: Add detection of AMD APUs. 
It is very simple detection - if the brand string contains " APU ",
the _APU_ bit in amd_code_and_bits_t::bits is set.

Simplify one other line as well.
 2017-05-04 03:37:09 +03:00
Xorg
5a02be091a RDMSR: use double instead of uint64_t for AMD CPU multipliers 
Multipliers can be a decimal number, like 7.5x
 2017-04-30 21:08:15 +02:00
Xorg
84f95c8ad0 RDMSR: fix VID range for AMD family 15h and above 
Fix #91
 2017-04-30 20:21:31 +02:00
Xorg
58b8eabd7c RDMSR: fix multipliers computed by get_amd_multipliers() 
This change should affect only 15h family
Fix #91
 2017-04-30 19:17:32 +02:00
Veselin Georgiev
b0cc93a253 Merge pull request #92 from X0rg/master 
AMD Ryzen support (RDMSR)
 2017-04-26 15:50:02 +01:00
Xorg
6574ce29e8 RDMSR: add Ryzen support 
Close #86
 2017-04-26 15:40:46 +02:00
Veselin Georgiev
b9a85805d2 Add "Multiprecision Computing Toolbox for MATLAB" to libcpuid users. 
As suggested in issue #89.
 2017-04-04 17:31:03 +03:00
Veselin Georgiev
8fe734c493 Fix previous commit based on comments in issue #89 thread. 
This should be correct now.
 2017-04-04 06:18:47 +03:00
Veselin Georgiev
88483aaba0 Possibly fix #89: Build failes with MSVC 
Fix non-C89 constructs. Not really verified to compile fine on MSVC,
since I don't have one right now, but will check later.
 2017-04-03 13:24:57 +03:00
Veselin Georgiev
94507ded22 Fixed issue #86: AMD Ryzen support 
Also add a test of Ryzen 7 (1800X).
 2017-03-20 02:28:28 +02:00
Veselin Georgiev
779b403aa0 Matchtable refactoring for AMD (see previous commit). 2017-03-20 01:47:28 +02:00