2021-09-15 23:24:19 +00:00
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#ifndef ULTRA64_CONTROLLER_H
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#define ULTRA64_CONTROLLER_H
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2020-03-17 04:31:30 +00:00
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2021-12-01 00:08:57 +00:00
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#include "message.h"
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2020-03-17 04:31:30 +00:00
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2022-07-30 19:41:32 +00:00
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/**
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* Controller channel
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* Each game controller channel has 4 error bits that are defined in bit 6-7 of
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* the Rx and Tx data size area bytes. Programmers need to clear these bits
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* when setting the Tx/Rx size area values for a channel
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*/
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#define CHNL_ERR_NORESP 0x80 /* Bit 7 (Rx): No response error */
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#define CHNL_ERR_OVERRUN 0x40 /* Bit 6 (Rx): Overrun error */
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#define CHNL_ERR_FRAME 0x80 /* Bit 7 (Tx): Frame error */
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#define CHNL_ERR_COLLISION 0x40 /* Bit 6 (Tx): Collision error */
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#define CHNL_ERR_MASK 0xC0 /* Bit 6-7: channel errors */
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#define CHNL_ERR(readFormat) (((readFormat).rxsize & CHNL_ERR_MASK) >> 4)
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2020-06-17 11:16:30 +00:00
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#define BLOCKSIZE 32
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#define MAXCONTROLLERS 4
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2020-07-07 00:15:01 +00:00
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#define PFS_ONE_PAGE 8
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#define PFS_PAGE_SIZE (BLOCKSIZE*PFS_ONE_PAGE)
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2020-06-17 11:16:30 +00:00
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2020-04-19 01:40:27 +00:00
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#define CONT_CMD_REQUEST_STATUS 0
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#define CONT_CMD_READ_BUTTON 1
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#define CONT_CMD_READ_MEMPACK 2
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#define CONT_CMD_WRITE_MEMPACK 3
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#define CONT_CMD_READ_EEPROM 4
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#define CONT_CMD_WRITE_EEPROM 5
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#define CONT_CMD_RESET 0xFF
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#define CONT_CMD_REQUEST_STATUS_TX 1
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#define CONT_CMD_READ_BUTTON_TX 1
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#define CONT_CMD_READ_MEMPACK_TX 3
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#define CONT_CMD_WRITE_MEMPACK_TX 35
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#define CONT_CMD_READ_EEPROM_TX 2
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#define CONT_CMD_WRITE_EEPROM_TX 10
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#define CONT_CMD_RESET_TX 1
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#define CONT_CMD_REQUEST_STATUS_RX 3
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#define CONT_CMD_READ_BUTTON_RX 4
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#define CONT_CMD_READ_MEMPACK_RX 33
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#define CONT_CMD_WRITE_MEMPACK_RX 1
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#define CONT_CMD_READ_EEPROM_RX 8
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#define CONT_CMD_WRITE_EEPROM_RX 1
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#define CONT_CMD_RESET_RX 3
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#define CONT_CMD_NOP 0xFF
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#define CONT_CMD_END 0xFE // Indicates end of a command
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#define CONT_CMD_EXE 1 // Set pif ram status byte to this to do a command
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2022-07-30 19:41:32 +00:00
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#define CONT_CMD_SKIP_CHNL 0 // Skip channel
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2020-04-19 01:40:27 +00:00
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2020-10-03 15:22:44 +00:00
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#define CONT_ERR_NO_CONTROLLER PFS_ERR_NOPACK /* 1 */
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#define CONT_ERR_CONTRFAIL CONT_OVERRUN_ERROR /* 4 */
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#define CONT_ERR_INVALID PFS_ERR_INVALID /* 5 */
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#define CONT_ERR_DEVICE PFS_ERR_DEVICE /* 11 */
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#define CONT_ERR_NOT_READY 12
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#define CONT_ERR_VOICE_MEMORY 13
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#define CONT_ERR_VOICE_WORD 14
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#define CONT_ERR_VOICE_NO_RESPONSE 15
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2020-04-19 01:40:27 +00:00
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#define DIR_STATUS_EMPTY 0
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#define DIR_STATUS_UNKNOWN 1
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#define DIR_STATUS_OCCUPIED 2
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#define PFS_FORCE 1
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#define PFS_DELETE 1
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#define PFS_LABEL_AREA 7
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#define PFS_ERR_NOPACK 1
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/* controller errors */
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#define CONT_NO_RESPONSE_ERROR 0x8
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#define CONT_OVERRUN_ERROR 0x4
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/* Controller type */
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#define CONT_ABSOLUTE 0x0001
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#define CONT_RELATIVE 0x0002
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#define CONT_JOYPORT 0x0004
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#define CONT_EEPROM 0x8000
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#define CONT_EEP16K 0x4000
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#define CONT_TYPE_MASK 0x1F07
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#define CONT_TYPE_NORMAL 0x0005
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#define CONT_TYPE_MOUSE 0x0002
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#define CONT_TYPE_VOICE 0x0100
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/* Controller status */
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#define CONT_CARD_ON 0x01
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#define CONT_CARD_PULL 0x02
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#define CONT_ADDR_CRC_ER 0x04
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#define CONT_EEPROM_BUSY 0x80
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2022-07-30 19:41:32 +00:00
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/* Accessory detection */
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#define CONT_ADDR_DETECT 0x8000
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// Rumble
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#define CONT_ADDR_RUMBLE 0xC000
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// Controller Pak / Transfer Pak
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#define CONT_ADDR_GB_POWER 0x8000 // Same as the detection address, but semantically different
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#define CONT_ADDR_GB_BANK 0xA000
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#define CONT_ADDR_GB_STATUS 0xB000
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// Addresses sent to controller accessories are in blocks, not bytes
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#define CONT_BLOCKS(x) ((x) / BLOCKSIZE)
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// Block addresses of the above
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#define CONT_BLOCK_DETECT CONT_BLOCKS(CONT_ADDR_DETECT)
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#define CONT_BLOCK_RUMBLE CONT_BLOCKS(CONT_ADDR_RUMBLE)
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#define CONT_BLOCK_GB_POWER CONT_BLOCKS(CONT_ADDR_GB_POWER)
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#define CONT_BLOCK_GB_BANK CONT_BLOCKS(CONT_ADDR_GB_BANK)
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#define CONT_BLOCK_GB_STATUS CONT_BLOCKS(CONT_ADDR_GB_STATUS)
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2020-06-17 11:16:30 +00:00
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/* Buttons */
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2020-10-03 15:22:44 +00:00
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#define BTN_CRIGHT 0x0001
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#define BTN_CLEFT 0x0002
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#define BTN_CDOWN 0x0004
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#define BTN_CUP 0x0008
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#define BTN_R 0x0010
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#define BTN_L 0x0020
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#define BTN_DRIGHT 0x0100
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#define BTN_DLEFT 0x0200
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#define BTN_DDOWN 0x0400
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#define BTN_DUP 0x0800
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#define BTN_START 0x1000
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#define BTN_Z 0x2000
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#define BTN_B 0x4000
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#define BTN_A 0x8000
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2020-04-14 17:17:25 +00:00
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2022-02-11 23:23:57 +00:00
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typedef union {
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struct {
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/* 0x00 */ u32 ram[15];
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/* 0x3C */ u32 status;
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2022-02-11 23:23:57 +00:00
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};
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u64 force_structure_alignment;
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} OSPifRam; // size = 0x40
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2020-04-14 17:17:25 +00:00
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typedef struct {
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2022-01-23 23:09:02 +00:00
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/* 0x00 */ u16 type;
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/* 0x02 */ u8 status;
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/* 0x03 */ u8 errno;
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} OSContStatus; // size = 0x04
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typedef struct {
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/* 0x00 */ u16 button;
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/* 0x02 */ s8 stick_x;
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/* 0x03 */ s8 stick_y;
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/* 0x04 */ u8 errno;
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} OSContPad; // size = 0x06
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typedef struct {
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/* 0x00 */ void* address;
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/* 0x04 */ u8 databuffer[32];
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/* 0x24 */ u8 addressCrc;
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/* 0x25 */ u8 dataCrc;
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/* 0x26 */ u8 errno;
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} OSContRamIo; // size = 0x28
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typedef struct {
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/* 0x00 */ u8 align;
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/* 0x01 */ u8 txsize;
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/* 0x02 */ u8 rxsize;
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2022-07-30 19:41:32 +00:00
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/* 0x03 */ u8 cmd;
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/* 0x04 */ u8 typeh;
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/* 0x05 */ u8 typel;
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/* 0x06 */ u8 status;
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/* 0x07 */ u8 align1;
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2022-07-30 19:41:32 +00:00
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} __OSContRequesFormat; // size = 0x8
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typedef struct {
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/* 0x00 */ u8 txsize;
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/* 0x01 */ u8 rxsize;
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/* 0x02 */ u8 cmd;
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/* 0x03 */ u8 typeh;
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/* 0x04 */ u8 typel;
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/* 0x05 */ u8 status;
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2022-07-30 19:41:32 +00:00
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} __OSContRequesFormatShort; // size = 0x6
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typedef struct {
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/* 0x00 */ u8 unk_00;
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/* 0x01 */ u8 txsize;
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/* 0x02 */ u8 rxsize;
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/* 0x03 */ u8 cmd;
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/* 0x04 */ u8 hi;
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/* 0x05 */ u8 lo;
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/* 0x06 */ u8 data[BLOCKSIZE];
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/* 0x26 */ u8 datacrc;
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2022-07-30 19:41:32 +00:00
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} __OSContRamReadFormat; // size = 0x27
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#define READFORMAT(ptr) ((__OSContRamReadFormat*)(ptr))
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typedef struct {
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/* 0x00 */ u8 align;
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/* 0x01 */ u8 txsize;
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/* 0x02 */ u8 rxsize;
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2022-07-30 19:41:32 +00:00
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/* 0x03 */ u8 cmd;
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/* 0x04 */ u16 button;
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/* 0x06 */ s8 joyX;
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/* 0x07 */ s8 joyY;
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2022-07-30 19:41:32 +00:00
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} __OSContReadFormat; // size = 0x8
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#endif
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