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Decompile code_801067F0, 80106860, 801068B0 (#89)

* Decompile code_801067F0, 80106860, 801068B0

* clang format

* Remove unnecessary casts
This commit is contained in:
Synray 2020-04-23 01:59:25 -07:00 committed by GitHub
parent 0a59863457
commit 4d3d264624
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
9 changed files with 61 additions and 159 deletions

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@ -1,40 +0,0 @@
.include "macro.inc"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purposee registers
.section .text
.align 4
glabel func_801067F0
/* B7D990 801067F0 27BDFFF8 */ addiu $sp, $sp, -8
/* B7D994 801067F4 44802000 */ mtc1 $zero, $f4
/* B7D998 801067F8 00000000 */ nop
/* B7D99C 801067FC 46047032 */ c.eq.s $f14, $f4
/* B7D9A0 80106800 00000000 */ nop
/* B7D9A4 80106804 45000004 */ bc1f .L80106818
/* B7D9A8 80106808 00000000 */ nop
/* B7D9AC 8010680C 44800000 */ mtc1 $zero, $f0
/* B7D9B0 80106810 1000000F */ b .L80106850
/* B7D9B4 80106814 00000000 */ nop
.L80106818:
/* B7D9B8 80106818 460E6183 */ div.s $f6, $f12, $f14
/* B7D9BC 8010681C 4600320D */ trunc.w.s $f8, $f6
/* B7D9C0 80106820 440F4000 */ mfc1 $t7, $f8
/* B7D9C4 80106824 00000000 */ nop
/* B7D9C8 80106828 AFAF0004 */ sw $t7, 4($sp)
/* B7D9CC 8010682C 8FB80004 */ lw $t8, 4($sp)
/* B7D9D0 80106830 44985000 */ mtc1 $t8, $f10
/* B7D9D4 80106834 00000000 */ nop
/* B7D9D8 80106838 46805420 */ cvt.s.w $f16, $f10
/* B7D9DC 8010683C 460E8482 */ mul.s $f18, $f16, $f14
/* B7D9E0 80106840 10000003 */ b .L80106850
/* B7D9E4 80106844 46126001 */ sub.s $f0, $f12, $f18
/* B7D9E8 80106848 10000001 */ b .L80106850
/* B7D9EC 8010684C 00000000 */ nop
.L80106850:
/* B7D9F0 80106850 03E00008 */ jr $ra
/* B7D9F4 80106854 27BD0008 */ addiu $sp, $sp, 8

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@ -1,34 +0,0 @@
.include "macro.inc"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purposee registers
.section .text
.align 4
glabel func_80106860
/* B7DA00 80106860 27BDFFF8 */ addiu $sp, $sp, -8
/* B7DA04 80106864 AFA40004 */ sw $a0, 4($sp)
/* B7DA08 80106868 00C03825 */ move $a3, $a2
/* B7DA0C 8010686C 10E00009 */ beqz $a3, .L80106894
/* B7DA10 80106870 24C6FFFF */ addiu $a2, $a2, -1
.L80106874:
/* B7DA14 80106874 8FAE0004 */ lw $t6, 4($sp)
/* B7DA18 80106878 A1C50000 */ sb $a1, ($t6)
/* B7DA1C 8010687C 8FAF0004 */ lw $t7, 4($sp)
/* B7DA20 80106880 25F80001 */ addiu $t8, $t7, 1
/* B7DA24 80106884 AFB80004 */ sw $t8, 4($sp)
/* B7DA28 80106888 00C03825 */ move $a3, $a2
/* B7DA2C 8010688C 14E0FFF9 */ bnez $a3, .L80106874
/* B7DA30 80106890 24C6FFFF */ addiu $a2, $a2, -1
.L80106894:
/* B7DA34 80106894 10000003 */ b .L801068A4
/* B7DA38 80106898 00801025 */ move $v0, $a0
/* B7DA3C 8010689C 10000001 */ b .L801068A4
/* B7DA40 801068A0 00000000 */ nop
.L801068A4:
/* B7DA44 801068A4 03E00008 */ jr $ra
/* B7DA48 801068A8 27BD0008 */ addiu $sp, $sp, 8

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@ -1,81 +0,0 @@
.include "macro.inc"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purposee registers
.section .text
.align 4
glabel func_801068B0
/* B7DA50 801068B0 27BDFFF0 */ addiu $sp, $sp, -0x10
/* B7DA54 801068B4 AFA4000C */ sw $a0, 0xc($sp)
/* B7DA58 801068B8 AFA50008 */ sw $a1, 8($sp)
/* B7DA5C 801068BC 8FAE000C */ lw $t6, 0xc($sp)
/* B7DA60 801068C0 8FAF0008 */ lw $t7, 8($sp)
/* B7DA64 801068C4 15CF0003 */ bne $t6, $t7, .L801068D4
/* B7DA68 801068C8 00000000 */ nop
/* B7DA6C 801068CC 10000034 */ b .L801069A0
/* B7DA70 801068D0 00801025 */ move $v0, $a0
.L801068D4:
/* B7DA74 801068D4 8FB8000C */ lw $t8, 0xc($sp)
/* B7DA78 801068D8 8FB90008 */ lw $t9, 8($sp)
/* B7DA7C 801068DC 0319082B */ sltu $at, $t8, $t9
/* B7DA80 801068E0 10200013 */ beqz $at, .L80106930
/* B7DA84 801068E4 00000000 */ nop
/* B7DA88 801068E8 00C03825 */ move $a3, $a2
/* B7DA8C 801068EC 10E0000E */ beqz $a3, .L80106928
/* B7DA90 801068F0 24C6FFFF */ addiu $a2, $a2, -1
.L801068F4:
/* B7DA94 801068F4 8FA80008 */ lw $t0, 8($sp)
/* B7DA98 801068F8 8FAA000C */ lw $t2, 0xc($sp)
/* B7DA9C 801068FC 91090000 */ lbu $t1, ($t0)
/* B7DAA0 80106900 A1490000 */ sb $t1, ($t2)
/* B7DAA4 80106904 8FAD0008 */ lw $t5, 8($sp)
/* B7DAA8 80106908 8FAB000C */ lw $t3, 0xc($sp)
/* B7DAAC 8010690C 25AE0001 */ addiu $t6, $t5, 1
/* B7DAB0 80106910 256C0001 */ addiu $t4, $t3, 1
/* B7DAB4 80106914 AFAC000C */ sw $t4, 0xc($sp)
/* B7DAB8 80106918 AFAE0008 */ sw $t6, 8($sp)
/* B7DABC 8010691C 00C03825 */ move $a3, $a2
/* B7DAC0 80106920 14E0FFF4 */ bnez $a3, .L801068F4
/* B7DAC4 80106924 24C6FFFF */ addiu $a2, $a2, -1
.L80106928:
/* B7DAC8 80106928 10000019 */ b .L80106990
/* B7DACC 8010692C 00000000 */ nop
.L80106930:
/* B7DAD0 80106930 8FAF000C */ lw $t7, 0xc($sp)
/* B7DAD4 80106934 01E6C021 */ addu $t8, $t7, $a2
/* B7DAD8 80106938 2719FFFF */ addiu $t9, $t8, -1
/* B7DADC 8010693C AFB9000C */ sw $t9, 0xc($sp)
/* B7DAE0 80106940 8FA80008 */ lw $t0, 8($sp)
/* B7DAE4 80106944 01064821 */ addu $t1, $t0, $a2
/* B7DAE8 80106948 252AFFFF */ addiu $t2, $t1, -1
/* B7DAEC 8010694C AFAA0008 */ sw $t2, 8($sp)
/* B7DAF0 80106950 00C03825 */ move $a3, $a2
/* B7DAF4 80106954 10E0000E */ beqz $a3, .L80106990
/* B7DAF8 80106958 24C6FFFF */ addiu $a2, $a2, -1
.L8010695C:
/* B7DAFC 8010695C 8FAB0008 */ lw $t3, 8($sp)
/* B7DB00 80106960 8FAD000C */ lw $t5, 0xc($sp)
/* B7DB04 80106964 916C0000 */ lbu $t4, ($t3)
/* B7DB08 80106968 A1AC0000 */ sb $t4, ($t5)
/* B7DB0C 8010696C 8FB80008 */ lw $t8, 8($sp)
/* B7DB10 80106970 8FAE000C */ lw $t6, 0xc($sp)
/* B7DB14 80106974 2719FFFF */ addiu $t9, $t8, -1
/* B7DB18 80106978 25CFFFFF */ addiu $t7, $t6, -1
/* B7DB1C 8010697C AFAF000C */ sw $t7, 0xc($sp)
/* B7DB20 80106980 AFB90008 */ sw $t9, 8($sp)
/* B7DB24 80106984 00C03825 */ move $a3, $a2
/* B7DB28 80106988 14E0FFF4 */ bnez $a3, .L8010695C
/* B7DB2C 8010698C 24C6FFFF */ addiu $a2, $a2, -1
.L80106990:
/* B7DB30 80106990 10000003 */ b .L801069A0
/* B7DB34 80106994 00801025 */ move $v0, $a0
/* B7DB38 80106998 10000001 */ b .L801069A0
/* B7DB3C 8010699C 00000000 */ nop
.L801069A0:
/* B7DB40 801069A0 03E00008 */ jr $ra
/* B7DB44 801069A4 27BD0010 */ addiu $sp, $sp, 0x10

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@ -2408,7 +2408,7 @@ OSThread* __osGetCurrFaultedThread();
// ? __osSpSetPc(?);
f32 absf(f32);
void* func_80106860(void* ptr, s32 val, size_t size);
// ? func_801068B0(?);
void* func_801068B0(void* dst, void* src, size_t size);
// ? func_801069B0(?);
u8 func_80106BC8(GlobalContext* globalCtx);
// ? func_80106C88(?);

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@ -106,6 +106,9 @@ build/src/code/fault.o: CFLAGS += -trapuv
build/src/code/fault.o: OPTIMIZATION := -O2 -g3
build/src/code/fault_drawer.o: CFLAGS += -trapuv
build/src/code/fault_drawer.o: OPTIMIZATION := -O2 -g3
build/src/code/code_801068B0.o: OPTIMIZATION := -g
build/src/code/code_80106860.o: OPTIMIZATION := -g
build/src/code/code_801067F0.o: OPTIMIZATION := -g
#### Main Targets ###

6
spec
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@ -566,9 +566,9 @@ beginseg
include "build/src/libultra_code/__osSpSetPc.o"
include "build/asm/code_801067D0.o"
include "build/asm/code_801067E0.o"
include "build/asm/code_801067F0.o"
include "build/asm/code_80106860.o"
include "build/asm/code_801068B0.o"
include "build/src/code/code_801067F0.o"
include "build/src/code/code_80106860.o"
include "build/src/code/code_801068B0.o"
include "build/src/code/z_message_PAL.o"
include "build/data/z_message_PAL.rodata.o"
include "build/data/z_message_PAL.bss.o"

13
src/code/code_801067F0.c Normal file
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@ -0,0 +1,13 @@
#include <ultra64.h>
#include <global.h>
// fmodf? unused
f32 func_801067F0(f32 arg0, f32 arg1) {
s32 sp4;
if (arg1 == 0.0f) {
return 0.0f;
}
sp4 = arg0 / arg1;
return arg0 - (sp4 * arg1);
}

13
src/code/code_80106860.c Normal file
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@ -0,0 +1,13 @@
#include <ultra64.h>
#include <global.h>
// memset used in __osMalloc, z_quake, z_view, and z_camera
void* func_80106860(void* ptr, s32 val, size_t size) {
u8* sp4 = ptr;
register s32 a3;
for (a3 = size--; a3 != 0; a3 = size--) {
*sp4++ = val;
}
return ptr;
}

28
src/code/code_801068B0.c Normal file
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@ -0,0 +1,28 @@
#include <ultra64.h>
#include <global.h>
// memcpy used in __osMalloc.c
void* func_801068B0(void* dst, void* src, size_t size) {
u8* spC;
u8* sp8;
register s32 a3;
spC = dst;
sp8 = src;
if (spC == sp8) {
return dst;
}
if (spC < sp8) {
for (a3 = size--; a3 != 0; a3 = size--) {
*spC++ = *sp8++;
}
} else {
spC += size - 1;
sp8 += size - 1;
for (a3 = size--; a3 != 0; a3 = size--) {
*spC-- = *sp8--;
}
}
return dst;
}