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Improve the state of handwritten assembly files (#865)

Browse source 
* Format all handwritten asm and document some

* Use c preprocessor for constants

* Fix

* Fix PI_STATUS_ERROR, some label improvements

* Avoid hi/lo for constants

* Some more comments

* Properly mark functions as functions and their sizes

* Fix merge

* Improvements

* Review suggestions, rework procedure start/end macros to be more like libreultra

* Move IPL3 symbol definitions into ipl3.s

* Fix undefined_syms, add include and language guards to asm.h and fix the comment in gbi.h

* Consistent hex capitalization, add some MIPS builtin defines to CC_CHECK to behave properly

* Add -no-pad-sections assembler option and clean up alignment in gu files and bzero

* Further suggestions and improvements

* Matrix conversion function clarifications

* Fix passing AVOID_UB to gcc

* Suggestions

* Suggestions, global interrupt mask improvements

* Further suggestions, interrupt mask comments

* Comments fixes, rdb.h

* Switch from # comments to // comments, remove unnecesary .set gp=64 directives

* Further review suggestions

* Missed one
This commit is contained in:
Tharo 2022-05-01 00:03:22 +01:00 • committed by GitHub
parent b9fded7b4e
commit 7334ffa373
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GPG key ID: 4AEE18F83AFDEB23
62 changed files with 2758 additions and 2083 deletions
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19
Makefile
View file

@ -1,5 +1,9 @@
MAKEFLAGS += --no-builtin-rules
# Ensure the build fails if a piped command fails
SHELL = /bin/bash
.SHELLFLAGS = -o pipefail -c
# Build options can either be changed by modifying the makefile, or by building with 'make SETTING=value'
# If COMPARE is 1, check the output md5sum after building
@ -32,8 +36,8 @@ endif
MIPS_BINUTILS_PREFIX ?= mips-linux-gnu-
ifeq ($(NON_MATCHING),1)
CFLAGS += -DNON_MATCHING
CPPFLAGS += -DNON_MATCHING
CFLAGS += -DNON_MATCHING -DAVOID_UB
CPPFLAGS += -DNON_MATCHING -DAVOID_UB
COMPARE := 0
endif
@ -112,10 +116,10 @@ else
OPTFLAGS := -O2
endif
ASFLAGS := -march=vr4300 -32 -Iinclude
ASFLAGS := -march=vr4300 -32 -no-pad-sections -I include
ifeq ($(COMPILER),gcc)
CFLAGS += -G 0 -nostdinc $(INC) -DAVOID_UB -march=vr4300 -mfix4300 -mabi=32 -mno-abicalls -mdivide-breaks -fno-zero-initialized-in-bss -fno-toplevel-reorder -ffreestanding -fno-common -fno-merge-constants -mno-explicit-relocs -mno-split-addresses $(CHECK_WARNINGS) -funsigned-char
CFLAGS += -G 0 -nostdinc $(INC) -march=vr4300 -mfix4300 -mabi=32 -mno-abicalls -mdivide-breaks -fno-zero-initialized-in-bss -fno-toplevel-reorder -ffreestanding -fno-common -fno-merge-constants -mno-explicit-relocs -mno-split-addresses $(CHECK_WARNINGS) -funsigned-char
MIPS_VERSION := -mips3
else
# we support Microsoft extensions such as anonymous structs, which the compiler does support but warns for their usage. Surpress the warnings with -woff.
@ -124,7 +128,9 @@ else
endif
ifeq ($(COMPILER),ido)
CC_CHECK = gcc -fno-builtin -fsyntax-only -funsigned-char -std=gnu90 -D_LANGUAGE_C -DNON_MATCHING $(INC) $(CHECK_WARNINGS)
# Have CC_CHECK pretend to be a MIPS compiler
MIPS_BUILTIN_DEFS := -D_MIPS_ISA_MIPS2=2 -D_MIPS_ISA=_MIPS_ISA_MIPS2 -D_ABIO32=1 -D_MIPS_SIM=_ABIO32 -D_MIPS_SZINT=32 -D_MIPS_SZLONG=32 -D_MIPS_SZPTR=32
CC_CHECK = gcc -fno-builtin -fsyntax-only -funsigned-char -std=gnu90 -D_LANGUAGE_C -DNON_MATCHING $(MIPS_BUILTIN_DEFS) $(INC) $(CHECK_WARNINGS)
ifeq ($(shell getconf LONG_BIT), 32)
# Work around memory allocation bug in QEMU
export QEMU_GUEST_BASE := 1
@ -277,7 +283,6 @@ $(O_FILES): | asset_files
.PHONY: o_files asset_files
build/$(SPEC): $(SPEC)
$(CPP) $(CPPFLAGS) $< > $@
@ -291,7 +296,7 @@ build/baserom/%.o: baserom/%
$(OBJCOPY) -I binary -O elf32-big $< $@
build/asm/%.o: asm/%.s
$(AS) $(ASFLAGS) $< -o $@
$(CPP) $(CPPFLAGS) -I include $< | $(AS) $(ASFLAGS) -o $@
build/data/%.o: data/%.s
$(AS) $(ASFLAGS) $< -o $@

41
asm/__osDisableInt.s
View file

@ -1,41 +0,0 @@
.include "macro.inc"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.section .text
.balign 16
glabel __osDisableInt
/* 007E80 80007280 3C0A8001 */ lui $t2, %hi(__OSGlobalIntMask) # $t2, 0x8001
/* 007E84 80007284 254AAD00 */ addiu $t2, %lo(__OSGlobalIntMask) # addiu $t2, $t2, -0x5300
/* 007E88 80007288 8D4B0000 */ lw $t3, ($t2)
/* 007E8C 8000728C 316BFF00 */ andi $t3, $t3, 0xff00
/* 007E90 80007290 40086000 */ mfc0 $t0, $12
/* 007E94 80007294 2401FFFE */ li $at, -2
/* 007E98 80007298 01014824 */ and $t1, $t0, $at
/* 007E9C 8000729C 40896000 */ mtc0 $t1, $12
/* 007EA0 800072A0 31020001 */ andi $v0, $t0, 1
/* 007EA4 800072A4 8D480000 */ lw $t0, ($t2)
/* 007EA8 800072A8 3108FF00 */ andi $t0, $t0, 0xff00
/* 007EAC 800072AC 110B000E */ beq $t0, $t3, .L800072E8
/* 007EB0 800072B0 3C0A8001 */ lui $t2, %hi(__osRunningThread) # $t2, 0x8001
/* 007EB4 800072B4 254AAD50 */ addiu $t2, %lo(__osRunningThread) # addiu $t2, $t2, -0x52b0
/* 007EB8 800072B8 8D490118 */ lw $t1, 0x118($t2)
/* 007EBC 800072BC 312AFF00 */ andi $t2, $t1, 0xff00
/* 007EC0 800072C0 01485024 */ and $t2, $t2, $t0
/* 007EC4 800072C4 3C01FFFF */ lui $at, (0xFFFF00FF >> 16) # lui $at, 0xffff
/* 007EC8 800072C8 342100FF */ ori $at, (0xFFFF00FF & 0xFFFF) # ori $at, $at, 0xff
/* 007ECC 800072CC 01214824 */ and $t1, $t1, $at
/* 007ED0 800072D0 012A4825 */ or $t1, $t1, $t2
/* 007ED4 800072D4 2401FFFE */ li $at, -2
/* 007ED8 800072D8 01214824 */ and $t1, $t1, $at
/* 007EDC 800072DC 40896000 */ mtc0 $t1, $12
/* 007EE0 800072E0 00000000 */ nop
/* 007EE4 800072E4 00000000 */ nop
.L800072E8:
/* 007EE8 800072E8 03E00008 */ jr $ra
/* 007EEC 800072EC 00000000 */ nop

18
asm/__osGetCause.s
View file

@ -1,15 +1,15 @@
.include "macro.inc"
#include "ultra64/asm.h"
#include "ultra64/r4300.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
glabel __osGetCause
/* 008790 80007B90 40026800 */ mfc0 $v0, $13
/* 008794 80007B94 03E00008 */ jr $ra
/* 008798 80007B98 00000000 */ nop
LEAF(__osGetCause)
mfc0 $v0, C0_CAUSE
jr $ra
nop
END(__osGetCause)

18
asm/__osGetFpcCsr.s
View file

@ -1,15 +1,15 @@
.include "macro.inc"
#include "ultra64/asm.h"
#include "ultra64/r4300.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
glabel __osGetFpcCsr
/* 008680 80007A80 4442F800 */ cfc1 $v0, $31
/* 008684 80007A84 03E00008 */ jr $ra
/* 008688 80007A88 00000000 */ nop
LEAF(__osGetFpcCsr)
cfc1 $v0, C1_FPCSR
jr $ra
nop
END(__osGetFpcCsr)

18
asm/__osGetSR.s
View file

@ -1,15 +1,15 @@
.include "macro.inc"
#include "ultra64/asm.h"
#include "ultra64/r4300.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
glabel __osGetSR
/* 0052B0 800046B0 40026000 */ mfc0 $v0, $12
/* 0052B4 800046B4 03E00008 */ jr $ra
/* 0052B8 800046B8 00000000 */ nop
LEAF(__osGetSR)
mfc0 $v0, C0_SR
jr $ra
nop
END(__osGetSR)

136
asm/__osProbeTLB.s
View file

@ -1,62 +1,86 @@
.include "macro.inc"
#include "ultra64/asm.h"
#include "ultra64/r4300.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
glabel __osProbeTLB
/* 005C40 80005040 40085000 */ mfc0 $t0, $10
/* 005C44 80005044 310900FF */ andi $t1, $t0, 0xff
/* 005C48 80005048 2401E000 */ li $at, -8192
/* 005C4C 8000504C 00815024 */ and $t2, $a0, $at
/* 005C50 80005050 012A4825 */ or $t1, $t1, $t2
/* 005C54 80005054 40895000 */ mtc0 $t1, $10
/* 005C58 80005058 00000000 */ nop
/* 005C5C 8000505C 00000000 */ nop
/* 005C60 80005060 00000000 */ nop
/* 005C64 80005064 42000008 */ tlbp
/* 005C68 80005068 00000000 */ nop
/* 005C6C 8000506C 00000000 */ nop
/* 005C70 80005070 400B0000 */ mfc0 $t3, $0
/* 005C74 80005074 3C018000 */ lui $at, 0x8000
/* 005C78 80005078 01615824 */ and $t3, $t3, $at
/* 005C7C 8000507C 1560001A */ bnez $t3, .L800050E8
/* 005C80 80005080 00000000 */ nop
/* 005C84 80005084 42000001 */ tlbr
/* 005C88 80005088 00000000 */ nop
/* 005C8C 8000508C 00000000 */ nop
/* 005C90 80005090 00000000 */ nop
/* 005C94 80005094 400B2800 */ mfc0 $t3, $5
/* 005C98 80005098 216B2000 */ addi $t3, $t3, 0x2000
/* 005C9C 8000509C 000B5842 */ srl $t3, $t3, 1
/* 005CA0 800050A0 01646024 */ and $t4, $t3, $a0
/* 005CA4 800050A4 15800004 */ bnez $t4, .L800050B8
/* 005CA8 800050A8 216BFFFF */ addi $t3, $t3, -1
/* 005CAC 800050AC 40021000 */ mfc0 $v0, $2
/* 005CB0 800050B0 10000002 */ b .L800050BC
/* 005CB4 800050B4 00000000 */ nop
.L800050B8:
/* 005CB8 800050B8 40021800 */ mfc0 $v0, $3
.L800050BC:
/* 005CBC 800050BC 304D0002 */ andi $t5, $v0, 2
/* 005CC0 800050C0 11A00009 */ beqz $t5, .L800050E8
/* 005CC4 800050C4 00000000 */ nop
/* 005CC8 800050C8 3C013FFF */ lui $at, (0x3FFFFFC0 >> 16) # lui $at, 0x3fff
/* 005CCC 800050CC 3421FFC0 */ ori $at, (0x3FFFFFC0 & 0xFFFF) # ori $at, $at, 0xffc0
/* 005CD0 800050D0 00411024 */ and $v0, $v0, $at
/* 005CD4 800050D4 00021180 */ sll $v0, $v0, 6
/* 005CD8 800050D8 008B6824 */ and $t5, $a0, $t3
/* 005CDC 800050DC 004D1020 */ add $v0, $v0, $t5
/* 005CE0 800050E0 10000002 */ b .L800050EC
/* 005CE4 800050E4 00000000 */ nop
.L800050E8:
/* 005CE8 800050E8 2402FFFF */ li $v0, -1
.L800050EC:
/* 005CEC 800050EC 40885000 */ mtc0 $t0, $10
/* 005CF0 800050F0 03E00008 */ jr $ra
/* 005CF4 800050F4 00000000 */ nop
/**
* u32 __osProbeTLB(void* vaddr);
*
* Searches the TLB for the physical address associated with
* the virtual address `vaddr`.
*
* Returns the physical address if found, or -1 if not found.
*/
LEAF(__osProbeTLB)
// Set C0_ENTRYHI based on supplied vaddr
mfc0 $t0, C0_ENTRYHI
andi $t1, $t0, TLBHI_PIDMASK
li $at, TLBHI_VPN2MASK
and $t2, $a0, $at
or $t1, $t1, $t2
mtc0 $t1, C0_ENTRYHI
nop
nop
nop
// TLB probe, sets C0_INX to a value matching C0_ENTRYHI.
// If no match is found the TLBINX_PROBE bit is set to indicate this.
tlbp
nop
nop
// Read result
mfc0 $t3, C0_INX
li $at, TLBINX_PROBE
and $t3, $t3, $at
// Branch if no match was found
bnez $t3, 3f
nop
// Read TLB, sets C0_ENTRYHI, C0_ENTRYLO0, C0_ENTRYLO1 and C0_PAGEMASK for the TLB
// entry indicated by C0_INX
tlbr
nop
nop
nop
// Calculate page size = (page mask + 0x2000) >> 1
mfc0 $t3, C0_PAGEMASK
addi $t3, $t3, 0x2000
srl $t3, $t3, 1
// & with vaddr
and $t4, $t3, $a0
// Select C0_ENTRYLO0 or C0_ENTRYLO1
bnez $t4, 1f
addi $t3, $t3, -1 // make bitmask out of page size
mfc0 $v0, C0_ENTRYLO0
b 2f
nop
1:
mfc0 $v0, C0_ENTRYLO1
2:
// Check valid bit and branch if not valid
andi $t5, $v0, TLBLO_V
beqz $t5, 3f
nop
// Extract the Page Frame Number from the entry
li $at, TLBLO_PFNMASK
and $v0, $v0, $at
sll $v0, $v0, TLBLO_PFNSHIFT
// Mask vaddr with page size mask
and $t5, $a0, $t3
// Add masked vaddr to pfn to obtain the physical address
add $v0, $v0, $t5
b 4f
nop
3:
// No physical address for the supplied virtual address was found,
// return -1
li $v0, -1
4:
// Restore original C0_ENTRYHI value before returning
mtc0 $t0, C0_ENTRYHI
jr $ra
nop
END(__osProbeTLB)

19
asm/__osRestoreInt.s
View file

@ -1,19 +0,0 @@
.include "macro.inc"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.section .text
.balign 16
glabel __osRestoreInt
/* 007EF0 800072F0 40086000 */ mfc0 $t0, $12
/* 007EF4 800072F4 01044025 */ or $t0, $t0, $a0
/* 007EF8 800072F8 40886000 */ mtc0 $t0, $12
/* 007EFC 800072FC 00000000 */ nop
/* 007F00 80007300 00000000 */ nop
/* 007F04 80007304 03E00008 */ jr $ra
/* 007F08 80007308 00000000 */ nop

18
asm/__osSetCompare.s
View file

@ -1,15 +1,15 @@
.include "macro.inc"
#include "ultra64/asm.h"
#include "ultra64/r4300.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
glabel __osSetCompare
/* 007B00 80006F00 40845800 */ mtc0 $a0, $11
/* 007B04 80006F04 03E00008 */ jr $ra
/* 007B08 80006F08 00000000 */ nop
LEAF(__osSetCompare)
mtc0 $a0, C0_COMPARE
jr $ra
nop
END(__osSetCompare)

20
asm/__osSetFpcCsr.s
View file

@ -1,16 +1,16 @@
.include "macro.inc"
#include "ultra64/asm.h"
#include "ultra64/r4300.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
glabel __osSetFpcCsr
/* 008670 80007A70 4442F800 */ cfc1 $v0, $31
/* 008674 80007A74 44C4F800 */ ctc1 $a0, $31
/* 008678 80007A78 03E00008 */ jr $ra
/* 00867C 80007A7C 00000000 */ nop
LEAF(__osSetFpcCsr)
cfc1 $v0, C1_FPCSR
ctc1 $a0, C1_FPCSR
jr $ra
nop
END(__osSetFpcCsr)

20
asm/__osSetSR.s
View file

@ -1,16 +1,16 @@
.include "macro.inc"
#include "ultra64/asm.h"
#include "ultra64/r4300.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
glabel __osSetSR
/* 0052A0 800046A0 40846000 */ mtc0 $a0, $12
/* 0052A4 800046A4 00000000 */ nop
/* 0052A8 800046A8 03E00008 */ jr $ra
/* 0052AC 800046AC 00000000 */ nop
LEAF(__osSetSR)
mtc0 $a0, C0_SR
nop
jr $ra
nop
END(__osSetSR)

20
asm/__osSetWatchLo.s
View file

@ -1,16 +1,16 @@
.include "macro.inc"
#include "ultra64/asm.h"
#include "ultra64/r4300.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
glabel __osSetWatchLo
/* 009F10 80009310 40849000 */ mtc0 $a0, $18
/* 009F14 80009314 00000000 */ nop
/* 009F18 80009318 03E00008 */ jr $ra
/* 009F1C 8000931C 00000000 */ nop
LEAF(__osSetWatchLo)
mtc0 $a0, C0_WATCHLO
nop
jr $ra
nop
END(__osSetWatchLo)

173
asm/bcmp.s
View file

@ -1,94 +1,93 @@
.include "macro.inc"
#include "ultra64/asm.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
glabel bcmp
/* 0074C0 800068C0 28C10010 */ slti $at, $a2, 0x10
/* 0074C4 800068C4 14200037 */ bnez $at, .bytecmp
/* 0074C8 800068C8 00851026 */ xor $v0, $a0, $a1
/* 0074CC 800068CC 30420003 */ andi $v0, $v0, 3
/* 0074D0 800068D0 14400019 */ bnez $v0, .unalgncmp
/* 0074D4 800068D4 0004C023 */ negu $t8, $a0
/* 0074D8 800068D8 33180003 */ andi $t8, $t8, 3
/* 0074DC 800068DC 13000007 */ beqz $t8, .wordcmp
/* 0074E0 800068E0 00D83023 */ subu $a2, $a2, $t8
/* 0074E4 800068E4 00601025 */ move $v0, $v1
/* 0074E8 800068E8 88820000 */ lwl $v0, ($a0)
/* 0074EC 800068EC 88A30000 */ lwl $v1, ($a1)
/* 0074F0 800068F0 00982021 */ addu $a0, $a0, $t8
/* 0074F4 800068F4 00B82821 */ addu $a1, $a1, $t8
/* 0074F8 800068F8 14430036 */ bne $v0, $v1, .cmpdone
.wordcmp:
/* 0074FC 800068FC 2401FFFC */ li $at, -4
/* 007500 80006900 00C13824 */ and $a3, $a2, $at
/* 007504 80006904 10E00027 */ beqz $a3, .bytecmp
/* 007508 80006908 00C73023 */ subu $a2, $a2, $a3
/* 00750C 8000690C 00E43821 */ addu $a3, $a3, $a0
/* 007510 80006910 8C820000 */ lw $v0, ($a0)
.L80006914:
/* 007514 80006914 8CA30000 */ lw $v1, ($a1)
/* 007518 80006918 24840004 */ addiu $a0, $a0, 4
/* 00751C 8000691C 24A50004 */ addiu $a1, $a1, 4
/* 007520 80006920 1443002C */ bne $v0, $v1, .cmpdone
/* 007524 80006924 00000000 */ nop
/* 007528 80006928 5487FFFA */ bnel $a0, $a3, .L80006914
/* 00752C 8000692C 8C820000 */ lw $v0, ($a0)
/* 007530 80006930 1000001C */ b .bytecmp
/* 007534 80006934 00000000 */ nop
.unalgncmp:
/* 007538 80006938 00053823 */ negu $a3, $a1
/* 00753C 8000693C 30E70003 */ andi $a3, $a3, 3
/* 007540 80006940 10E0000A */ beqz $a3, .partaligncmp
/* 007544 80006944 00C73023 */ subu $a2, $a2, $a3
/* 007548 80006948 00E43821 */ addu $a3, $a3, $a0
/* 00754C 8000694C 90820000 */ lbu $v0, ($a0)
.L80006950:
/* 007550 80006950 90A30000 */ lbu $v1, ($a1)
/* 007554 80006954 24840001 */ addiu $a0, $a0, 1
/* 007558 80006958 24A50001 */ addiu $a1, $a1, 1
/* 00755C 8000695C 1443001D */ bne $v0, $v1, .cmpdone
/* 007560 80006960 00000000 */ nop
/* 007564 80006964 5487FFFA */ bnel $a0, $a3, .L80006950
/* 007568 80006968 90820000 */ lbu $v0, ($a0)
.partaligncmp:
/* 00756C 8000696C 2401FFFC */ li $at, -4
/* 007570 80006970 00C13824 */ and $a3, $a2, $at
/* 007574 80006974 10E0000B */ beqz $a3, .bytecmp
/* 007578 80006978 00C73023 */ subu $a2, $a2, $a3
/* 00757C 8000697C 00E43821 */ addu $a3, $a3, $a0
/* 007580 80006980 88820000 */ lwl $v0, ($a0)
.L80006984:
/* 007584 80006984 8CA30000 */ lw $v1, ($a1)
/* 007588 80006988 98820003 */ lwr $v0, 3($a0)
/* 00758C 8000698C 24840004 */ addiu $a0, $a0, 4
/* 007590 80006990 24A50004 */ addiu $a1, $a1, 4
/* 007594 80006994 1443000F */ bne $v0, $v1, .cmpdone
/* 007598 80006998 00000000 */ nop
/* 00759C 8000699C 5487FFF9 */ bnel $a0, $a3, .L80006984
/* 0075A0 800069A0 88820000 */ lwl $v0, ($a0)
.bytecmp:
/* 0075A4 800069A4 18C00009 */ blez $a2, .L800069CC
/* 0075A8 800069A8 00C43821 */ addu $a3, $a2, $a0
/* 0075AC 800069AC 90820000 */ lbu $v0, ($a0)
.L800069B0:
/* 0075B0 800069B0 90A30000 */ lbu $v1, ($a1)
/* 0075B4 800069B4 24840001 */ addiu $a0, $a0, 1
/* 0075B8 800069B8 24A50001 */ addiu $a1, $a1, 1
/* 0075BC 800069BC 14430005 */ bne $v0, $v1, .cmpdone
/* 0075C0 800069C0 00000000 */ nop
/* 0075C4 800069C4 5487FFFA */ bnel $a0, $a3, .L800069B0
/* 0075C8 800069C8 90820000 */ lbu $v0, ($a0)
.L800069CC:
/* 0075CC 800069CC 03E00008 */ jr $ra
/* 0075D0 800069D0 00001025 */ move $v0, $zero
LEAF(bcmp)
slti $at, $a2, 0x10
bnez $at, bytecmp
xor $v0, $a0, $a1
andi $v0, $v0, 3
bnez $v0, unaligncmp
negu $t8, $a0
andi $t8, $t8, 3
beqz $t8, wordcmp
subu $a2, $a2, $t8
move $v0, $v1
lwl $v0, ($a0)
lwl $v1, ($a1)
addu $a0, $a0, $t8
addu $a1, $a1, $t8
bne $v0, $v1, cmpne
wordcmp:
li $at, ~3
and $a3, $a2, $at
beqz $a3, bytecmp
subu $a2, $a2, $a3
addu $a3, $a3, $a0
lw $v0, ($a0)
1:
lw $v1, ($a1)
addiu $a0, $a0, 4
addiu $a1, $a1, 4
bne $v0, $v1, cmpne
nop
bnel $a0, $a3, 1b
lw $v0, ($a0)
b bytecmp
nop
unaligncmp:
negu $a3, $a1
andi $a3, $a3, 3
beqz $a3, partaligncmp
subu $a2, $a2, $a3
addu $a3, $a3, $a0
lbu $v0, ($a0)
1:
lbu $v1, ($a1)
addiu $a0, $a0, 1
addiu $a1, $a1, 1
bne $v0, $v1, cmpne
nop
bnel $a0, $a3, 1b
lbu $v0, ($a0)
partaligncmp:
li $at, ~3
and $a3, $a2, $at
beqz $a3, bytecmp
subu $a2, $a2, $a3
addu $a3, $a3, $a0
lwl $v0, ($a0)
1:
lw $v1, ($a1)
lwr $v0, 3($a0)
addiu $a0, $a0, 4
addiu $a1, $a1, 4
bne $v0, $v1, cmpne
nop
bnel $a0, $a3, 1b
lwl $v0, ($a0)
bytecmp:
blez $a2, cmpdone
addu $a3, $a2, $a0
lbu $v0, ($a0)
1:
lbu $v1, ($a1)
addiu $a0, $a0, 1
addiu $a1, $a1, 1
bne $v0, $v1, cmpne
nop
bnel $a0, $a3, 1b
lbu $v0, ($a0)
cmpdone:
jr $ra
move $v0, $zero
.cmpdone:
/* 0075D4 800069D4 03E00008 */ jr $ra
/* 0075D8 800069D8 24020001 */ li $v0, 1
cmpne:
jr $ra
li $v0, 1
END(bcmp)

413
asm/bcopy.s
View file

@ -1,230 +1,233 @@
.include "macro.inc"
#include "ultra64/asm.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
glabel bcopy
/* 007B10 80006F10 10C0001A */ beqz $a2, ret
/* 007B14 80006F14 00A03825 */ move $a3, $a1
/* 007B18 80006F18 10850018 */ beq $a0, $a1, ret
/* 007B1C 80006F1C 00A4082A */ slt $at, $a1, $a0
/* 007B20 80006F20 54200008 */ bnezl $at, goforwards
/* 007B24 80006F24 28C10010 */ slti $at, $a2, 0x10
/* 007B28 80006F28 00861020 */ add $v0, $a0, $a2
/* 007B2C 80006F2C 00A2082A */ slt $at, $a1, $v0
/* 007B30 80006F30 50200004 */ beql $at, $zero, goforwards
/* 007B34 80006F34 28C10010 */ slti $at, $a2, 0x10
/* 007B38 80006F38 1000005B */ b gobackwards
/* 007B3C 80006F3C 28C10010 */ slti $at, $a2, 0x10
/* 007B40 80006F40 28C10010 */ slti $at, $a2, 0x10
LEAF(bcopy)
beqz $a2, ret
move $a3, $a1
beq $a0, $a1, ret
slt $at, $a1, $a0
bnezl $at, goforwards
slti $at, $a2, 0x10
add $v0, $a0, $a2
slt $at, $a1, $v0
beql $at, $zero, goforwards
slti $at, $a2, 0x10
b gobackwards
slti $at, $a2, 0x10
slti $at, $a2, 0x10
goforwards:
/* 007B44 80006F44 14200005 */ bnez $at, forwards_bytecopy
/* 007B48 80006F48 00000000 */ nop
/* 007B4C 80006F4C 30820003 */ andi $v0, $a0, 3
/* 007B50 80006F50 30A30003 */ andi $v1, $a1, 3
/* 007B54 80006F54 1043000B */ beq $v0, $v1, forwalignable
/* 007B58 80006F58 00000000 */ nop
bnez $at, forwards_bytecopy
nop
andi $v0, $a0, 3
andi $v1, $a1, 3
beq $v0, $v1, forwalignable
nop
forwards_bytecopy:
/* 007B5C 80006F5C 10C00007 */ beqz $a2, ret
/* 007B60 80006F60 00000000 */ nop
/* 007B64 80006F64 00861821 */ addu $v1, $a0, $a2
.L80006F68:
/* 007B68 80006F68 80820000 */ lb $v0, ($a0)
/* 007B6C 80006F6C 24840001 */ addiu $a0, $a0, 1
/* 007B70 80006F70 24A50001 */ addiu $a1, $a1, 1
/* 007B74 80006F74 1483FFFC */ bne $a0, $v1, .L80006F68
/* 007B78 80006F78 A0A2FFFF */ sb $v0, -1($a1)
beqz $a2, ret
nop
addu $v1, $a0, $a2
99:
lb $v0, ($a0)
addiu $a0, $a0, 1
addiu $a1, $a1, 1
bne $a0, $v1, 99b
sb $v0, -1($a1)
ret:
/* 007B7C 80006F7C 03E00008 */ jr $ra
/* 007B80 80006F80 00E01025 */ move $v0, $a3
jr $ra
move $v0, $a3
forwalignable:
/* 007B84 80006F84 10400018 */ beqz $v0, forwards_32
/* 007B88 80006F88 24010001 */ li $at, 1
/* 007B8C 80006F8C 1041000F */ beq $v0, $at, forw_copy3
/* 007B90 80006F90 24010002 */ li $at, 2
/* 007B94 80006F94 50410008 */ beql $v0, $at, forw_copy2
/* 007B98 80006F98 84820000 */ lh $v0, ($a0)
/* 007B9C 80006F9C 80820000 */ lb $v0, ($a0)
/* 007BA0 80006FA0 24840001 */ addiu $a0, $a0, 1
/* 007BA4 80006FA4 24A50001 */ addiu $a1, $a1, 1
/* 007BA8 80006FA8 24C6FFFF */ addiu $a2, $a2, -1
/* 007BAC 80006FAC 1000000E */ b forwards_32
/* 007BB0 80006FB0 A0A2FFFF */ sb $v0, -1($a1)
/* 007BB4 80006FB4 84820000 */ lh $v0, ($a0)
beqz $v0, forwards_32
li $at, 1
beq $v0, $at, forw_copy3
li $at, 2
beql $v0, $at, forw_copy2
lh $v0, ($a0)
lb $v0, ($a0)
addiu $a0, $a0, 1
addiu $a1, $a1, 1
addiu $a2, $a2, -1
b forwards_32
sb $v0, -1($a1)
lh $v0, ($a0)
forw_copy2:
/* 007BB8 80006FB8 24840002 */ addiu $a0, $a0, 2
/* 007BBC 80006FBC 24A50002 */ addiu $a1, $a1, 2
/* 007BC0 80006FC0 24C6FFFE */ addiu $a2, $a2, -2
/* 007BC4 80006FC4 10000008 */ b forwards_32
/* 007BC8 80006FC8 A4A2FFFE */ sh $v0, -2($a1)
addiu $a0, $a0, 2
addiu $a1, $a1, 2
addiu $a2, $a2, -2
b forwards_32
sh $v0, -2($a1)
forw_copy3:
/* 007BCC 80006FCC 80820000 */ lb $v0, ($a0)
/* 007BD0 80006FD0 84830001 */ lh $v1, 1($a0)
/* 007BD4 80006FD4 24840003 */ addiu $a0, $a0, 3
/* 007BD8 80006FD8 24A50003 */ addiu $a1, $a1, 3
/* 007BDC 80006FDC 24C6FFFD */ addiu $a2, $a2, -3
/* 007BE0 80006FE0 A0A2FFFD */ sb $v0, -3($a1)
/* 007BE4 80006FE4 A4A3FFFE */ sh $v1, -2($a1)
lb $v0, ($a0)
lh $v1, 1($a0)
addiu $a0, $a0, 3
addiu $a1, $a1, 3
addiu $a2, $a2, -3
sb $v0, -3($a1)
sh $v1, -2($a1)
forwards:
forwards_32:
/* 007BE8 80006FE8 28C10020 */ slti $at, $a2, 0x20
/* 007BEC 80006FEC 54200016 */ bnezl $at, .L80007048
/* 007BF0 80006FF0 28C10010 */ slti $at, $a2, 0x10
/* 007BF4 80006FF4 8C820000 */ lw $v0, ($a0)
/* 007BF8 80006FF8 8C830004 */ lw $v1, 4($a0)
/* 007BFC 80006FFC 8C880008 */ lw $t0, 8($a0)
/* 007C00 80007000 8C89000C */ lw $t1, 0xc($a0)
/* 007C04 80007004 8C8A0010 */ lw $t2, 0x10($a0)
/* 007C08 80007008 8C8B0014 */ lw $t3, 0x14($a0)
/* 007C0C 8000700C 8C8C0018 */ lw $t4, 0x18($a0)
/* 007C10 80007010 8C8D001C */ lw $t5, 0x1c($a0)
/* 007C14 80007014 24840020 */ addiu $a0, $a0, 0x20
/* 007C18 80007018 24A50020 */ addiu $a1, $a1, 0x20
/* 007C1C 8000701C 24C6FFE0 */ addiu $a2, $a2, -0x20
/* 007C20 80007020 ACA2FFE0 */ sw $v0, -0x20($a1)
/* 007C24 80007024 ACA3FFE4 */ sw $v1, -0x1c($a1)
/* 007C28 80007028 ACA8FFE8 */ sw $t0, -0x18($a1)
/* 007C2C 8000702C ACA9FFEC */ sw $t1, -0x14($a1)
/* 007C30 80007030 ACAAFFF0 */ sw $t2, -0x10($a1)
/* 007C34 80007034 ACABFFF4 */ sw $t3, -0xc($a1)
/* 007C38 80007038 ACACFFF8 */ sw $t4, -8($a1)
/* 007C3C 8000703C 1000FFEA */ b forwards_32
/* 007C40 80007040 ACADFFFC */ sw $t5, -4($a1)
slti $at, $a2, 0x20
bnezl $at, forwards_16_
slti $at, $a2, 0x10
lw $v0, ($a0)
lw $v1, 4($a0)
lw $t0, 8($a0)
lw $t1, 0xC($a0)
lw $t2, 0x10($a0)
lw $t3, 0x14($a0)
lw $t4, 0x18($a0)
lw $t5, 0x1C($a0)
addiu $a0, $a0, 0x20
addiu $a1, $a1, 0x20
addiu $a2, $a2, -0x20
sw $v0, -0x20($a1)
sw $v1, -0x1C($a1)
sw $t0, -0x18($a1)
sw $t1, -0x14($a1)
sw $t2, -0x10($a1)
sw $t3, -0xC($a1)
sw $t4, -8($a1)
b forwards_32
sw $t5, -4($a1)
forwards_16:
/* 007C44 80007044 28C10010 */ slti $at, $a2, 0x10
.L80007048:
/* 007C48 80007048 5420000E */ bnezl $at, .L80007084
/* 007C4C 8000704C 28C10004 */ slti $at, $a2, 4
/* 007C50 80007050 8C820000 */ lw $v0, ($a0)
/* 007C54 80007054 8C830004 */ lw $v1, 4($a0)
/* 007C58 80007058 8C880008 */ lw $t0, 8($a0)
/* 007C5C 8000705C 8C89000C */ lw $t1, 0xc($a0)
/* 007C60 80007060 24840010 */ addiu $a0, $a0, 0x10
/* 007C64 80007064 24A50010 */ addiu $a1, $a1, 0x10
/* 007C68 80007068 24C6FFF0 */ addiu $a2, $a2, -0x10
/* 007C6C 8000706C ACA2FFF0 */ sw $v0, -0x10($a1)
/* 007C70 80007070 ACA3FFF4 */ sw $v1, -0xc($a1)
/* 007C74 80007074 ACA8FFF8 */ sw $t0, -8($a1)
/* 007C78 80007078 1000FFF2 */ b forwards_16
/* 007C7C 8000707C ACA9FFFC */ sw $t1, -4($a1)
slti $at, $a2, 0x10
forwards_16_: // fake label due to branch likely optimization
bnezl $at, forwards_4_
slti $at, $a2, 4
lw $v0, ($a0)
lw $v1, 4($a0)
lw $t0, 8($a0)
lw $t1, 0xC($a0)
addiu $a0, $a0, 0x10
addiu $a1, $a1, 0x10
addiu $a2, $a2, -0x10
sw $v0, -0x10($a1)
sw $v1, -0xC($a1)
sw $t0, -8($a1)
b forwards_16
sw $t1, -4($a1)
forwards_4:
/* 007C80 80007080 28C10004 */ slti $at, $a2, 4
.L80007084:
/* 007C84 80007084 1420FFB5 */ bnez $at, forwards_bytecopy
/* 007C88 80007088 00000000 */ nop
/* 007C8C 8000708C 8C820000 */ lw $v0, ($a0)
/* 007C90 80007090 24840004 */ addiu $a0, $a0, 4
/* 007C94 80007094 24A50004 */ addiu $a1, $a1, 4
/* 007C98 80007098 24C6FFFC */ addiu $a2, $a2, -4
/* 007C9C 8000709C 1000FFF8 */ b forwards_4
/* 007CA0 800070A0 ACA2FFFC */ sw $v0, -4($a1)
/* 007CA4 800070A4 28C10010 */ slti $at, $a2, 0x10
slti $at, $a2, 4
forwards_4_: // fake label due to branch likely optimization
bnez $at, forwards_bytecopy
nop
lw $v0, ($a0)
addiu $a0, $a0, 4
addiu $a1, $a1, 4
addiu $a2, $a2, -4
b forwards_4
sw $v0, -4($a1)
slti $at, $a2, 0x10
gobackwards:
/* 007CA8 800070A8 00862020 */ add $a0, $a0, $a2
/* 007CAC 800070AC 14200005 */ bnez $at, backwards_bytecopy
/* 007CB0 800070B0 00A62820 */ add $a1, $a1, $a2
/* 007CB4 800070B4 30820003 */ andi $v0, $a0, 3
/* 007CB8 800070B8 30A30003 */ andi $v1, $a1, 3
/* 007CBC 800070BC 1043000D */ beq $v0, $v1, backalignable
/* 007CC0 800070C0 00000000 */ nop
add $a0, $a0, $a2
bnez $at, backwards_bytecopy
add $a1, $a1, $a2
andi $v0, $a0, 3
andi $v1, $a1, 3
beq $v0, $v1, backalignable
nop
backwards_bytecopy:
/* 007CC4 800070C4 10C0FFAD */ beqz $a2, ret
/* 007CC8 800070C8 00000000 */ nop
/* 007CCC 800070CC 2484FFFF */ addiu $a0, $a0, -1
/* 007CD0 800070D0 24A5FFFF */ addiu $a1, $a1, -1
/* 007CD4 800070D4 00861823 */ subu $v1, $a0, $a2
.L800070D8:
/* 007CD8 800070D8 80820000 */ lb $v0, ($a0)
/* 007CDC 800070DC 2484FFFF */ addiu $a0, $a0, -1
/* 007CE0 800070E0 24A5FFFF */ addiu $a1, $a1, -1
/* 007CE4 800070E4 1483FFFC */ bne $a0, $v1, .L800070D8
/* 007CE8 800070E8 A0A20001 */ sb $v0, 1($a1)
/* 007CEC 800070EC 03E00008 */ jr $ra
/* 007CF0 800070F0 00E01025 */ move $v0, $a3
beqz $a2, ret
nop
addiu $a0, $a0, -1
addiu $a1, $a1, -1
subu $v1, $a0, $a2
99:
lb $v0, ($a0)
addiu $a0, $a0, -1
addiu $a1, $a1, -1
bne $a0, $v1, 99b
sb $v0, 1($a1)
jr $ra
move $v0, $a3
backalignable:
/* 007CF4 800070F4 10400018 */ beqz $v0, backwards_32
/* 007CF8 800070F8 24010003 */ li $at, 3
/* 007CFC 800070FC 1041000F */ beq $v0, $at, back_copy3
/* 007D00 80007100 24010002 */ li $at, 2
/* 007D04 80007104 50410008 */ beql $v0, $at, back_copy2
/* 007D08 80007108 8482FFFE */ lh $v0, -2($a0)
/* 007D0C 8000710C 8082FFFF */ lb $v0, -1($a0)
/* 007D10 80007110 2484FFFF */ addiu $a0, $a0, -1
/* 007D14 80007114 24A5FFFF */ addiu $a1, $a1, -1
/* 007D18 80007118 24C6FFFF */ addiu $a2, $a2, -1
/* 007D1C 8000711C 1000000E */ b backwards_32
/* 007D20 80007120 A0A20000 */ sb $v0, ($a1)
/* 007D24 80007124 8482FFFE */ lh $v0, -2($a0)
beqz $v0, backwards_32
li $at, 3
beq $v0, $at, back_copy3
li $at, 2
beql $v0, $at, back_copy2
lh $v0, -2($a0)
lb $v0, -1($a0)
addiu $a0, $a0, -1
addiu $a1, $a1, -1
addiu $a2, $a2, -1
b backwards_32
sb $v0, ($a1)
lh $v0, -2($a0)
back_copy2:
/* 007D28 80007128 2484FFFE */ addiu $a0, $a0, -2
/* 007D2C 8000712C 24A5FFFE */ addiu $a1, $a1, -2
/* 007D30 80007130 24C6FFFE */ addiu $a2, $a2, -2
/* 007D34 80007134 10000008 */ b backwards_32
/* 007D38 80007138 A4A20000 */ sh $v0, ($a1)
addiu $a0, $a0, -2
addiu $a1, $a1, -2
addiu $a2, $a2, -2
b backwards_32
sh $v0, ($a1)
back_copy3:
/* 007D3C 8000713C 8082FFFF */ lb $v0, -1($a0)
/* 007D40 80007140 8483FFFD */ lh $v1, -3($a0)
/* 007D44 80007144 2484FFFD */ addiu $a0, $a0, -3
/* 007D48 80007148 24A5FFFD */ addiu $a1, $a1, -3
/* 007D4C 8000714C 24C6FFFD */ addiu $a2, $a2, -3
/* 007D50 80007150 A0A20002 */ sb $v0, 2($a1)
/* 007D54 80007154 A4A30000 */ sh $v1, ($a1)
lb $v0, -1($a0)
lh $v1, -3($a0)
addiu $a0, $a0, -3
addiu $a1, $a1, -3
addiu $a2, $a2, -3
sb $v0, 2($a1)
sh $v1, ($a1)
backwards:
backwards_32:
/* 007D58 80007158 28C10020 */ slti $at, $a2, 0x20
/* 007D5C 8000715C 54200016 */ bnezl $at, .L800071B8
/* 007D60 80007160 28C10010 */ slti $at, $a2, 0x10
/* 007D64 80007164 8C82FFFC */ lw $v0, -4($a0)
/* 007D68 80007168 8C83FFF8 */ lw $v1, -8($a0)
/* 007D6C 8000716C 8C88FFF4 */ lw $t0, -0xc($a0)
/* 007D70 80007170 8C89FFF0 */ lw $t1, -0x10($a0)
/* 007D74 80007174 8C8AFFEC */ lw $t2, -0x14($a0)
/* 007D78 80007178 8C8BFFE8 */ lw $t3, -0x18($a0)
/* 007D7C 8000717C 8C8CFFE4 */ lw $t4, -0x1c($a0)
/* 007D80 80007180 8C8DFFE0 */ lw $t5, -0x20($a0)
/* 007D84 80007184 2484FFE0 */ addiu $a0, $a0, -0x20
/* 007D88 80007188 24A5FFE0 */ addiu $a1, $a1, -0x20
/* 007D8C 8000718C 24C6FFE0 */ addiu $a2, $a2, -0x20
/* 007D90 80007190 ACA2001C */ sw $v0, 0x1c($a1)
/* 007D94 80007194 ACA30018 */ sw $v1, 0x18($a1)
/* 007D98 80007198 ACA80014 */ sw $t0, 0x14($a1)
/* 007D9C 8000719C ACA90010 */ sw $t1, 0x10($a1)
/* 007DA0 800071A0 ACAA000C */ sw $t2, 0xc($a1)
/* 007DA4 800071A4 ACAB0008 */ sw $t3, 8($a1)
/* 007DA8 800071A8 ACAC0004 */ sw $t4, 4($a1)
/* 007DAC 800071AC 1000FFEA */ b backwards_32
/* 007DB0 800071B0 ACAD0000 */ sw $t5, ($a1)
slti $at, $a2, 0x20
bnezl $at, backwards_16_
slti $at, $a2, 0x10
lw $v0, -4($a0)
lw $v1, -8($a0)
lw $t0, -0xc($a0)
lw $t1, -0x10($a0)
lw $t2, -0x14($a0)
lw $t3, -0x18($a0)
lw $t4, -0x1c($a0)
lw $t5, -0x20($a0)
addiu $a0, $a0, -0x20
addiu $a1, $a1, -0x20
addiu $a2, $a2, -0x20
sw $v0, 0x1C($a1)
sw $v1, 0x18($a1)
sw $t0, 0x14($a1)
sw $t1, 0x10($a1)
sw $t2, 0xC($a1)
sw $t3, 8($a1)
sw $t4, 4($a1)
b backwards_32
sw $t5, ($a1)
backwards_16:
/* 007DB4 800071B4 28C10010 */ slti $at, $a2, 0x10
.L800071B8:
/* 007DB8 800071B8 5420000E */ bnezl $at, .L800071F4
/* 007DBC 800071BC 28C10004 */ slti $at, $a2, 4
/* 007DC0 800071C0 8C82FFFC */ lw $v0, -4($a0)
/* 007DC4 800071C4 8C83FFF8 */ lw $v1, -8($a0)
/* 007DC8 800071C8 8C88FFF4 */ lw $t0, -0xc($a0)
/* 007DCC 800071CC 8C89FFF0 */ lw $t1, -0x10($a0)
/* 007DD0 800071D0 2484FFF0 */ addiu $a0, $a0, -0x10
/* 007DD4 800071D4 24A5FFF0 */ addiu $a1, $a1, -0x10
/* 007DD8 800071D8 24C6FFF0 */ addiu $a2, $a2, -0x10
/* 007DDC 800071DC ACA2000C */ sw $v0, 0xc($a1)
/* 007DE0 800071E0 ACA30008 */ sw $v1, 8($a1)
/* 007DE4 800071E4 ACA80004 */ sw $t0, 4($a1)
/* 007DE8 800071E8 1000FFF2 */ b backwards_16
/* 007DEC 800071EC ACA90000 */ sw $t1, ($a1)
slti $at, $a2, 0x10
backwards_16_: // fake label due to branch likely optimization
bnezl $at, backwards_4_
slti $at, $a2, 4
lw $v0, -4($a0)
lw $v1, -8($a0)
lw $t0, -0xC($a0)
lw $t1, -0x10($a0)
addiu $a0, $a0, -0x10
addiu $a1, $a1, -0x10
addiu $a2, $a2, -0x10
sw $v0, 0xC($a1)
sw $v1, 8($a1)
sw $t0, 4($a1)
b backwards_16
sw $t1, ($a1)
backwards_4:
/* 007DF0 800071F0 28C10004 */ slti $at, $a2, 4
.L800071F4:
/* 007DF4 800071F4 1420FFB3 */ bnez $at, backwards_bytecopy
/* 007DF8 800071F8 00000000 */ nop
/* 007DFC 800071FC 8C82FFFC */ lw $v0, -4($a0)
/* 007E00 80007200 2484FFFC */ addiu $a0, $a0, -4
/* 007E04 80007204 24A5FFFC */ addiu $a1, $a1, -4
/* 007E08 80007208 24C6FFFC */ addiu $a2, $a2, -4
/* 007E0C 8000720C 1000FFF8 */ b backwards_4
/* 007E10 80007210 ACA20000 */ sw $v0, ($a1)
slti $at, $a2, 4
backwards_4_: // fake label due to branch likely optimization
bnez $at, backwards_bytecopy
nop
lw $v0, -4($a0)
addiu $a0, $a0, -4
addiu $a1, $a1, -4
addiu $a2, $a2, -4
b backwards_4
sw $v0, ($a1)
END(bcopy)

137
asm/bzero.s
View file

@ -1,84 +1,65 @@
.include "macro.inc"
#include "ultra64/asm.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
glabel bzero
/* 005050 80004450 28A1000C */ slti $at, $a1, 0xc
/* 005054 80004454 1420001D */ bnez $at, .bytezero
/* 005058 80004458 00041823 */ negu $v1, $a0
/* 00505C 8000445C 30630003 */ andi $v1, $v1, 3
/* 005060 80004460 10600003 */ beqz $v1, .blkzero
/* 005064 80004464 00A32823 */ subu $a1, $a1, $v1
/* 005068 80004468 A8800000 */ swl $zero, ($a0)
/* 00506C 8000446C 00832021 */ addu $a0, $a0, $v1
.blkzero:
/* 005070 80004470 2401FFE0 */ li $at, -32
/* 005074 80004474 00A13824 */ and $a3, $a1, $at
/* 005078 80004478 10E0000C */ beqz $a3, .wordzero
/* 00507C 8000447C 00A72823 */ subu $a1, $a1, $a3
/* 005080 80004480 00E43821 */ addu $a3, $a3, $a0
.L80004484:
/* 005084 80004484 24840020 */ addiu $a0, $a0, 0x20
/* 005088 80004488 AC80FFE0 */ sw $zero, -0x20($a0)
/* 00508C 8000448C AC80FFE4 */ sw $zero, -0x1c($a0)
/* 005090 80004490 AC80FFE8 */ sw $zero, -0x18($a0)
/* 005094 80004494 AC80FFEC */ sw $zero, -0x14($a0)
/* 005098 80004498 AC80FFF0 */ sw $zero, -0x10($a0)
/* 00509C 8000449C AC80FFF4 */ sw $zero, -0xc($a0)
/* 0050A0 800044A0 AC80FFF8 */ sw $zero, -8($a0)
/* 0050A4 800044A4 1487FFF7 */ bne $a0, $a3, .L80004484
/* 0050A8 800044A8 AC80FFFC */ sw $zero, -4($a0)
.wordzero:
/* 0050AC 800044AC 2401FFFC */ li $at, -4
/* 0050B0 800044B0 00A13824 */ and $a3, $a1, $at
/* 0050B4 800044B4 10E00005 */ beqz $a3, .bytezero
/* 0050B8 800044B8 00A72823 */ subu $a1, $a1, $a3
/* 0050BC 800044BC 00E43821 */ addu $a3, $a3, $a0
.L800044C0:
/* 0050C0 800044C0 24840004 */ addiu $a0, $a0, 4
/* 0050C4 800044C4 1487FFFE */ bne $a0, $a3, .L800044C0
/* 0050C8 800044C8 AC80FFFC */ sw $zero, -4($a0)
.bytezero:
/* 0050CC 800044CC 18A00005 */ blez $a1, .zerodone
/* 0050D0 800044D0 00000000 */ nop
/* 0050D4 800044D4 00A42821 */ addu $a1, $a1, $a0
.L800044D8:
/* 0050D8 800044D8 24840001 */ addiu $a0, $a0, 1
/* 0050DC 800044DC 1485FFFE */ bne $a0, $a1, .L800044D8
/* 0050E0 800044E0 A080FFFF */ sb $zero, -1($a0)
.zerodone:
/* 0050E4 800044E4 03E00008 */ jr $ra
/* 0050E8 800044E8 00000000 */ nop
/* 0050EC 800044EC 00000000 */ nop
/* 0050F0 800044F0 00000000 */ nop
/* 0050F4 800044F4 00000000 */ nop
/* 0050F8 800044F8 00000000 */ nop
/* 0050FC 800044FC 00000000 */ nop
/* 005100 80004500 00000000 */ nop
/* 005104 80004504 00000000 */ nop
/* 005108 80004508 00000000 */ nop
/* 00510C 8000450C 00000000 */ nop
/* 005110 80004510 00000000 */ nop
/* 005114 80004514 00000000 */ nop
/* 005118 80004518 00000000 */ nop
/* 00511C 8000451C 00000000 */ nop
/* 005120 80004520 00000000 */ nop
/* 005124 80004524 00000000 */ nop
/* 005128 80004528 00000000 */ nop
/* 00512C 8000452C 00000000 */ nop
/* 005130 80004530 00000000 */ nop
/* 005134 80004534 00000000 */ nop
/* 005138 80004538 00000000 */ nop
/* 00513C 8000453C 00000000 */ nop
/* 005140 80004540 00000000 */ nop
/* 005144 80004544 00000000 */ nop
/* 005148 80004548 00000000 */ nop
/* 00514C 8000454C 00000000 */ nop
LEAF(bzero)
slti $at, $a1, 0xC
bnez $at, bytezero
negu $v1, $a0
andi $v1, $v1, 3
beqz $v1, blkzero
subu $a1, $a1, $v1
swl $zero, ($a0)
addu $a0, $a0, $v1
blkzero:
// align backwards to 0x20
li $at, ~0x1F
and $a3, $a1, $at
// If the result is zero, the amount to zero is less than 0x20 bytes
beqz $a3, wordzero
subu $a1, $a1, $a3
// zero in blocks of 0x20 at a time
addu $a3, $a3, $a0
1:
addiu $a0, $a0, 0x20
sw $zero, -0x20($a0)
sw $zero, -0x1C($a0)
sw $zero, -0x18($a0)
sw $zero, -0x14($a0)
sw $zero, -0x10($a0)
sw $zero, -0xC($a0)
sw $zero, -8($a0)
bne $a0, $a3, 1b
sw $zero, -4($a0)
wordzero:
// align backwards to 0x4
li $at, ~3
and $a3, $a1, $at
// If the result is zero, the amount to zero is less than 0x4 bytes
beqz $a3, bytezero
subu $a1, $a1, $a3
// zero one word at a time
addu $a3, $a3, $a0
1:
addiu $a0, $a0, 4
bne $a0, $a3, 1b
sw $zero, -4($a0)
bytezero:
// test if nothing left to zero
blez $a1, zerodone
nop
// zero one byte at a time
addu $a1, $a1, $a0
1:
addiu $a0, $a0, 1
bne $a0, $a1, 1b
sb $zero, -1($a0)
zerodone:
jr $ra
nop
END(bzero)

92
asm/code_800D71F0.s
View file

@ -1,57 +1,57 @@
.include "macro.inc"
#include "ultra64/asm.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
glabel func_800D71F0
/* B4E390 800D71F0 34018800 */ li $at, 34816
/* B4E394 800D71F4 0081082A */ slt $at, $a0, $at
/* B4E398 800D71F8 14200010 */ bnez $at, .L800D723C
/* B4E39C 800D71FC 240600BC */ li $a2, 188
/* B4E3A0 800D7200 00042A02 */ srl $a1, $a0, 8
/* B4E3A4 800D7204 20A5FF78 */ addi $a1, $a1, -0x88
/* B4E3A8 800D7208 00C50019 */ multu $a2, $a1
/* B4E3AC 800D720C 308700FF */ andi $a3, $a0, 0xff
/* B4E3B0 800D7210 20E7FFC0 */ addi $a3, $a3, -0x40
/* B4E3B4 800D7214 28E10040 */ slti $at, $a3, 0x40
/* B4E3B8 800D7218 00003012 */ mflo $a2
/* B4E3BC 800D721C 54200003 */ bnezl $at, .L800D722C
/* B4E3C0 800D7220 00003012 */ mflo $a2
/* B4E3C4 800D7224 20E7FFFF */ addi $a3, $a3, -1
/* B4E3C8 800D7228 00003012 */ mflo $a2
LEAF(func_800D71F0)
li $at, 0x8800
slt $at, $a0, $at
bnez $at, .L800D723C
li $a2, 188
srl $a1, $a0, 8
addi $a1, $a1, -0x88
multu $a2, $a1
andi $a3, $a0, 0xFF
addi $a3, $a3, -0x40
slti $at, $a3, 0x40
mflo $a2
bnezl $at, .L800D722C
mflo $a2
addi $a3, $a3, -1
mflo $a2
.L800D722C:
/* B4E3CC 800D722C 20E7030A */ addi $a3, $a3, 0x30a
/* B4E3D0 800D7230 00E63820 */ add $a3, $a3, $a2
/* B4E3D4 800D7234 03E00008 */ jr $ra
/* B4E3D8 800D7238 000711C0 */ sll $v0, $a3, 7
addi $a3, $a3, 0x30A
add $a3, $a3, $a2
jr $ra
sll $v0, $a3, 7
.L800D723C:
/* B4E3DC 800D723C 00042A02 */ srl $a1, $a0, 8
/* B4E3E0 800D7240 20A5FF7F */ addi $a1, $a1, -0x81
/* B4E3E4 800D7244 00C50019 */ multu $a2, $a1
/* B4E3E8 800D7248 308700FF */ andi $a3, $a0, 0xff
/* B4E3EC 800D724C 20E7FFC0 */ addi $a3, $a3, -0x40
/* B4E3F0 800D7250 28E10040 */ slti $at, $a3, 0x40
/* B4E3F4 800D7254 00003012 */ mflo $a2
/* B4E3F8 800D7258 54200003 */ bnezl $at, .L800D7268
/* B4E3FC 800D725C 00003012 */ mflo $a2
/* B4E400 800D7260 20E7FFFF */ addi $a3, $a3, -1
/* B4E404 800D7264 00003012 */ mflo $a2
srl $a1, $a0, 8
addi $a1, $a1, -0x81
multu $a2, $a1
andi $a3, $a0, 0xFF
addi $a3, $a3, -0x40
slti $at, $a3, 0x40
mflo $a2
bnezl $at, .L800D7268
mflo $a2
addi $a3, $a3, -1
mflo $a2
.L800D7268:
/* B4E408 800D7268 00E63820 */ add $a3, $a3, $a2
/* B4E40C 800D726C 3C06800D */ lui $a2, %hi(D_800D7288) # $a2, 0x800d
/* B4E410 800D7270 00073840 */ sll $a3, $a3, 1
/* B4E414 800D7274 24C67288 */ addiu $a2, %lo(D_800D7288) # addiu $a2, $a2, 0x7288
/* B4E418 800D7278 00E63820 */ add $a3, $a3, $a2
/* B4E41C 800D727C 84E60000 */ lh $a2, ($a3)
/* B4E420 800D7280 03E00008 */ jr $ra
/* B4E424 800D7284 000611C0 */ sll $v0, $a2, 7
add $a3, $a3, $a2
lui $a2, %hi(D_800D7288)
sll $a3, $a3, 1
addiu $a2, %lo(D_800D7288)
add $a3, $a3, $a2
lh $a2, ($a3)
jr $ra
sll $v0, $a2, 7
END(func_800D71F0)
glabel D_800D7288
.incbin "baserom.z64", 0xB4E428, 0xB4EE70-0xB4E428
DATA(D_800D7288)
.incbin "baserom.z64", 0xB4E428, 0xB4EE70 - 0xB4E428
ENDDATA(D_800D7288)

44
asm/entry.s
View file

@ -1,37 +1,35 @@
.include "macro.inc"
#include "ultra64/asm.h"
#include "boot.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.set BOOT_STACK_SIZE, 0x400
.balign 16
glabel entrypoint # 0x80000400
lui $t0, %hi(_bootSegmentBssStart)
addiu $t0, %lo(_bootSegmentBssStart)
li $t1, %lo(_bootSegmentBssSize)
.L8000040C:
LEAF(entrypoint)
// Clear boot segment .bss
la $t0, _bootSegmentBssStart
#ifndef AVOID_UB
// UB: li only loads the lower 16 bits of _bootSegmentBssSize when it may be larger than this,
// so not all of bss may be cleared if it is too large
li $t1, _bootSegmentBssSize
#else
la $t1, _bootSegmentBssSize
#endif
.clear_bss:
addi $t1, $t1, -8
sw $zero, ($t0)
sw $zero, 4($t0)
bnez $t1, .L8000040C
bnez $t1, .clear_bss
addi $t0, $t0, 8
// Set up stack and enter program code
lui $t2, %hi(bootproc)
lui $sp, %hi(sBootThreadStack + BOOT_STACK_SIZE)
addiu $t2, %lo(bootproc)
jr $t2
addiu $sp, %lo(sBootThreadStack + BOOT_STACK_SIZE)
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
END(entrypoint)
.fill 0x60 - (. - entrypoint)

1536
asm/exceptasm.s
View file

File diff suppressed because it is too large Load diff

117
asm/fp.s
View file

@ -1,138 +1,165 @@
.include "macro.inc"
#include "ultra64/asm.h"
.set noreorder
.section .data
glabel qNaN0x3FFFFF
.balign 16
DATA(qNaN0x3FFFFF)
.word 0x7FBFFFFF
ENDDATA(qNaN0x3FFFFF)
glabel qNaN0x10000
DATA(qNaN0x10000)
.word 0x7F810000
ENDDATA(qNaN0x10000)
glabel sNaN0x3FFFFF
DATA(sNaN0x3FFFFF)
.word 0x7FFFFFFF
ENDDATA(sNaN0x3FFFFF)
.section .text
glabel floorf
.balign 16
LEAF(floorf)
floor.w.s $f12, $f12
jr $ra
cvt.s.w $f0, $f12
jr $ra
END(floorf)
glabel floor
LEAF(floor)
floor.w.d $f12, $f12
cvt.d.w $f0, $f12
jr $ra
cvt.d.w $f0, $f12
END(floor)
glabel lfloorf
LEAF(lfloorf)
floor.w.s $f4, $f12
mfc1 $v0, $f4
nop
jr $ra
nop
END(lfloorf)
glabel lfloor
LEAF(lfloor)
floor.w.d $f4, $f12
mfc1 $v0, $f4
jr $ra
nop
jr $ra
END(lfloor)
glabel ceilf
LEAF(ceilf)
ceil.w.s $f12, $f12
jr $ra
cvt.s.w $f0, $f12
jr $ra
END(ceilf)
glabel ceil
LEAF(ceil)
ceil.w.d $f12, $f12
cvt.d.w $f0, $f12
jr $ra
cvt.d.w $f0, $f12
END(ceil)
glabel lceilf
LEAF(lceilf)
ceil.w.s $f4, $f12
mfc1 $v0, $f4
nop
jr $ra
nop
END(lceilf)
glabel lceil
LEAF(lceil)
ceil.w.d $f4, $f12
mfc1 $v0, $f4
jr $ra
nop
jr $ra
END(lceil)
glabel truncf
LEAF(truncf)
trunc.w.s $f12, $f12
jr $ra
cvt.s.w $f0, $f12
jr $ra
END(truncf)
glabel trunc
LEAF(trunc)
trunc.w.d $f12, $f12
cvt.d.w $f0, $f12
jr $ra
cvt.d.w $f0, $f12
END(trunc)
glabel ltruncf
LEAF(ltruncf)
trunc.w.s $f4, $f12
mfc1 $v0, $f4
nop
jr $ra
nop
END(ltruncf)
glabel ltrunc
LEAF(ltrunc)
trunc.w.d $f4, $f12
mfc1 $v0, $f4
jr $ra
nop
jr $ra
END(ltrunc)
glabel nearbyintf
LEAF(nearbyintf)
round.w.s $f12, $f12
jr $ra
cvt.s.w $f0, $f12
jr $ra
END(nearbyintf)
glabel nearbyint
LEAF(nearbyint)
round.w.d $f12, $f12
cvt.d.w $f0, $f12
jr $ra
cvt.d.w $f0, $f12
END(nearbyint)
glabel lnearbyintf
LEAF(lnearbyintf)
round.w.s $f4, $f12
mfc1 $v0, $f4
nop
jr $ra
nop
END(lnearbyintf)
glabel lnearbyint
LEAF(lnearbyint)
round.w.d $f4, $f12
mfc1 $v0, $f4
nop
jr $ra
nop
END(lnearbyint)
glabel roundf
LEAF(roundf)
li.s $f4, 0.5
nop
add.s $f0, $f12, $f4
floor.w.s $f0, $f0
jr $ra
cvt.s.w $f0, $f0
jr $ra
END(roundf)
glabel round
LEAF(round)
li.d $f4, 0.5
nop
add.d $f0, $f12, $f4
floor.w.d $f0, $f0
cvt.d.w $f0, $f0
jr $ra
cvt.d.w $f0, $f0
END(round)
glabel lroundf
LEAF(lroundf)
li.s $f4, 0.5
nop
add.s $f0, $f12, $f4
floor.w.s $f0, $f0
mfc1 $v0, $f0
nop
jr $ra
nop
END(lroundf)
glabel lround
LEAF(lround)
li.d $f4, 0.5
nop
add.d $f0, $f12, $f4
floor.w.d $f0, $f0
mfc1 $v0, $f0
nop
jr $ra
nop
END(lround)

72
asm/guMtxF2L.s
View file

@ -1,42 +1,40 @@
.include "macro.inc"
#include "ultra64/asm.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
.balign 32
/* B7D670 801064D0 00000000 */ nop
/* B7D674 801064D4 00000000 */ nop
/* B7D678 801064D8 00000000 */ nop
/* B7D67C 801064DC 00000000 */ nop
glabel guMtxF2L
/* B7D680 801064E0 3C014780 */ li $at, 0x47800000 # 0.000000
/* B7D684 801064E4 44810000 */ mtc1 $at, $f0
/* B7D688 801064E8 3C19FFFF */ lui $t9, 0xffff
/* B7D68C 801064EC 24B80020 */ addiu $t8, $a1, 0x20
.L801064F0:
/* B7D690 801064F0 C4840000 */ lwc1 $f4, ($a0)
/* B7D694 801064F4 C48A0004 */ lwc1 $f10, 4($a0)
/* B7D698 801064F8 24A50004 */ addiu $a1, $a1, 4
/* B7D69C 801064FC 46002182 */ mul.s $f6, $f4, $f0
/* B7D6A0 80106500 24840008 */ addiu $a0, $a0, 8
/* B7D6A4 80106504 46005402 */ mul.s $f16, $f10, $f0
/* B7D6A8 80106508 4600320D */ trunc.w.s $f8, $f6
/* B7D6AC 8010650C 4600848D */ trunc.w.s $f18, $f16
/* B7D6B0 80106510 44084000 */ mfc1 $t0, $f8
/* B7D6B4 80106514 44099000 */ mfc1 $t1, $f18
/* B7D6B8 80106518 01195024 */ and $t2, $t0, $t9
/* B7D6BC 8010651C 00086C00 */ sll $t5, $t0, 0x10
/* B7D6C0 80106520 00095C02 */ srl $t3, $t1, 0x10
/* B7D6C4 80106524 312EFFFF */ andi $t6, $t1, 0xffff
/* B7D6C8 80106528 014B6025 */ or $t4, $t2, $t3
/* B7D6CC 8010652C 01AE7825 */ or $t7, $t5, $t6
/* B7D6D0 80106530 ACACFFFC */ sw $t4, -4($a1)
/* B7D6D4 80106534 14B8FFEE */ bne $a1, $t8, .L801064F0
/* B7D6D8 80106538 ACAF001C */ sw $t7, 0x1c($a1)
/* B7D6DC 8010653C 03E00008 */ jr $ra
/* B7D6E0 80106540 00000000 */ nop
#define MTX_INTPART 0
#define MTX_FRACPART 0x20
LEAF(guMtxF2L)
li $at, 0x47800000 // 65536.0f
mtc1 $at, $f0
li $t9, 0xFFFF0000
addiu $t8, $a1, MTX_FRACPART
1:
lwc1 $f4, ($a0)
lwc1 $f10, 4($a0)
addiu $a1, $a1, 4
mul.s $f6, $f4, $f0
addiu $a0, $a0, 8
mul.s $f16, $f10, $f0
trunc.w.s $f8, $f6
trunc.w.s $f18, $f16
mfc1 $t0, $f8
mfc1 $t1, $f18
and $t2, $t0, $t9
sll $t5, $t0, 0x10
srl $t3, $t1, 0x10
andi $t6, $t1, 0xFFFF
or $t4, $t2, $t3
or $t7, $t5, $t6
sw $t4, (MTX_INTPART-4)($a1)
bne $a1, $t8, 1b
sw $t7, (MTX_FRACPART-4)($a1)
jr $ra
nop
END(guMtxF2L)

51
asm/guMtxIdent.s
View file

@ -1,31 +1,30 @@
.include "macro.inc"
#include "ultra64/asm.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
.balign 32
glabel guMtxIdent
/* B7AD00 80103B60 20080001 */ addi $t0, $zero, 1
/* B7AD04 80103B64 00084C00 */ sll $t1, $t0, 0x10
/* B7AD08 80103B68 AC890000 */ sw $t1, ($a0)
/* B7AD0C 80103B6C AC800004 */ sw $zero, 4($a0)
/* B7AD10 80103B70 AC880008 */ sw $t0, 8($a0)
/* B7AD14 80103B74 AC80000C */ sw $zero, 0xc($a0)
/* B7AD18 80103B78 AC800010 */ sw $zero, 0x10($a0)
/* B7AD1C 80103B7C AC890014 */ sw $t1, 0x14($a0)
/* B7AD20 80103B80 AC800018 */ sw $zero, 0x18($a0)
/* B7AD24 80103B84 AC88001C */ sw $t0, 0x1c($a0)
/* B7AD28 80103B88 AC800020 */ sw $zero, 0x20($a0)
/* B7AD2C 80103B8C AC800024 */ sw $zero, 0x24($a0)
/* B7AD30 80103B90 AC800028 */ sw $zero, 0x28($a0)
/* B7AD34 80103B94 AC80002C */ sw $zero, 0x2c($a0)
/* B7AD38 80103B98 AC800030 */ sw $zero, 0x30($a0)
/* B7AD3C 80103B9C AC800034 */ sw $zero, 0x34($a0)
/* B7AD40 80103BA0 AC800038 */ sw $zero, 0x38($a0)
/* B7AD44 80103BA4 03E00008 */ jr $ra
/* B7AD48 80103BA8 AC80003C */ sw $zero, 0x3c($a0)
LEAF(guMtxIdent)
addi $t0, $zero, 1
sll $t1, $t0, 0x10
sw $t1, ($a0)
sw $zero, 4($a0)
sw $t0, 8($a0)
sw $zero, 0xc($a0)
sw $zero, 0x10($a0)
sw $t1, 0x14($a0)
sw $zero, 0x18($a0)
sw $t0, 0x1C($a0)
sw $zero, 0x20($a0)
sw $zero, 0x24($a0)
sw $zero, 0x28($a0)
sw $zero, 0x2c($a0)
sw $zero, 0x30($a0)
sw $zero, 0x34($a0)
sw $zero, 0x38($a0)
jr $ra
sw $zero, 0x3C($a0)
END(guMtxIdent)

51
asm/guMtxIdentF.s
View file

@ -1,32 +1,29 @@
.include "macro.inc"
#include "ultra64/asm.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
.balign 32
## Handwritten ASM
glabel guMtxIdentF
/* B78CE0 80101B40 3C083F80 */ lui $t0, 0x3f80
/* B78CE4 80101B44 AC880000 */ sw $t0, ($a0)
/* B78CE8 80101B48 AC800004 */ sw $zero, 4($a0)
/* B78CEC 80101B4C AC800008 */ sw $zero, 8($a0)
/* B78CF0 80101B50 AC80000C */ sw $zero, 0xc($a0)
/* B78CF4 80101B54 AC800010 */ sw $zero, 0x10($a0)
/* B78CF8 80101B58 AC880014 */ sw $t0, 0x14($a0)
/* B78CFC 80101B5C AC800018 */ sw $zero, 0x18($a0)
/* B78D00 80101B60 AC80001C */ sw $zero, 0x1c($a0)
/* B78D04 80101B64 AC800020 */ sw $zero, 0x20($a0)
/* B78D08 80101B68 AC800024 */ sw $zero, 0x24($a0)
/* B78D0C 80101B6C AC880028 */ sw $t0, 0x28($a0)
/* B78D10 80101B70 AC80002C */ sw $zero, 0x2c($a0)
/* B78D14 80101B74 AC800030 */ sw $zero, 0x30($a0)
/* B78D18 80101B78 AC800034 */ sw $zero, 0x34($a0)
/* B78D1C 80101B7C AC800038 */ sw $zero, 0x38($a0)
/* B78D20 80101B80 03E00008 */ jr $ra
/* B78D24 80101B84 AC88003C */ sw $t0, 0x3c($a0)
LEAF(guMtxIdentF)
li $t0, 0x3F800000 // 1.0f
sw $t0, ($a0)
sw $zero, 4($a0)
sw $zero, 8($a0)
sw $zero, 0xC($a0)
sw $zero, 0x10($a0)
sw $t0, 0x14($a0)
sw $zero, 0x18($a0)
sw $zero, 0x1C($a0)
sw $zero, 0x20($a0)
sw $zero, 0x24($a0)
sw $t0, 0x28($a0)
sw $zero, 0x2C($a0)
sw $zero, 0x30($a0)
sw $zero, 0x34($a0)
sw $zero, 0x38($a0)
jr $ra
sw $t0, 0x3C($a0)
END(guMtxIdentF)

70
asm/guMtxL2F.s
View file

@ -1,39 +1,41 @@
.include "macro.inc"
#include "ultra64/asm.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
.balign 32
glabel guMtxL2F
/* B7A140 80102FA0 3C013780 */ li $at, 0x37800000 # 0.000000
/* B7A144 80102FA4 44810000 */ mtc1 $at, $f0
/* B7A148 80102FA8 3C19FFFF */ li $t9, 0xFFFF0000 # 0.000000
/* B7A14C 80102FAC 24B80020 */ addiu $t8, $a1, 0x20
.L80102FB0:
/* B7A150 80102FB0 8CA80000 */ lw $t0, ($a1)
/* B7A154 80102FB4 8CA90020 */ lw $t1, 0x20($a1)
/* B7A158 80102FB8 24A50004 */ addiu $a1, $a1, 4
/* B7A15C 80102FBC 01195024 */ and $t2, $t0, $t9
/* B7A160 80102FC0 00095C02 */ srl $t3, $t1, 0x10
/* B7A164 80102FC4 014B6025 */ or $t4, $t2, $t3
/* B7A168 80102FC8 448C2000 */ mtc1 $t4, $f4
/* B7A16C 80102FCC 00086C00 */ sll $t5, $t0, 0x10
/* B7A170 80102FD0 312EFFFF */ andi $t6, $t1, 0xffff
/* B7A174 80102FD4 01AE7825 */ or $t7, $t5, $t6
/* B7A178 80102FD8 468021A0 */ cvt.s.w $f6, $f4
/* B7A17C 80102FDC 448F5000 */ mtc1 $t7, $f10
/* B7A180 80102FE0 24840008 */ addiu $a0, $a0, 8
/* B7A184 80102FE4 46805420 */ cvt.s.w $f16, $f10
/* B7A188 80102FE8 46003202 */ mul.s $f8, $f6, $f0
/* B7A18C 80102FEC 00000000 */ nop
/* B7A190 80102FF0 46008482 */ mul.s $f18, $f16, $f0
/* B7A194 80102FF4 E488FFF8 */ swc1 $f8, -8($a0)
/* B7A198 80102FF8 14B8FFED */ bne $a1, $t8, .L80102FB0
/* B7A19C 80102FFC E492FFFC */ swc1 $f18, -4($a0)
/* B7A1A0 80103000 03E00008 */ jr $ra
/* B7A1A4 80103004 00000000 */ nop
#define MTX_INTPART 0
#define MTX_FRACPART 0x20
LEAF(guMtxL2F)
li $at, 0x37800000 // 1.0f / 65536.0f
mtc1 $at, $f0
li $t9, 0xFFFF0000
addiu $t8, $a1, MTX_FRACPART
1:
lw $t0, MTX_INTPART($a1)
lw $t1, MTX_FRACPART($a1)
addiu $a1, $a1, 4
and $t2, $t0, $t9
srl $t3, $t1, 0x10
or $t4, $t2, $t3
mtc1 $t4, $f4
sll $t5, $t0, 0x10
andi $t6, $t1, 0xFFFF
or $t7, $t5, $t6
cvt.s.w $f6, $f4
mtc1 $t7, $f10
addiu $a0, $a0, 8
cvt.s.w $f16, $f10
mul.s $f8, $f6, $f0
nop
mul.s $f18, $f16, $f0
swc1 $f8, -8($a0)
bne $a1, $t8, 1b
swc1 $f18, -4($a0)
jr $ra
nop
END(guMtxL2F)

59
asm/guNormalize.s
View file

@ -1,37 +1,32 @@
.include "macro.inc"
#include "ultra64/asm.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
.balign 32
/* B7B2F0 80104150 00000000 */ nop
/* B7B2F4 80104154 00000000 */ nop
/* B7B2F8 80104158 00000000 */ nop
/* B7B2FC 8010415C 00000000 */ nop
glabel guNormalize
/* B7B300 80104160 C4840000 */ lwc1 $f4, ($a0)
/* B7B304 80104164 C4A60000 */ lwc1 $f6, ($a1)
/* B7B308 80104168 C4C80000 */ lwc1 $f8, ($a2)
/* B7B30C 8010416C 46042282 */ mul.s $f10, $f4, $f4
/* B7B310 80104170 3C083F80 */ li $t0, 0x3F800000 # 0.000000
/* B7B314 80104174 46063402 */ mul.s $f16, $f6, $f6
/* B7B318 80104178 46105480 */ add.s $f18, $f10, $f16
/* B7B31C 8010417C 46084402 */ mul.s $f16, $f8, $f8
/* B7B320 80104180 46128280 */ add.s $f10, $f16, $f18
/* B7B324 80104184 44889000 */ mtc1 $t0, $f18
/* B7B328 80104188 46005404 */ sqrt.s $f16, $f10
/* B7B32C 8010418C 46109283 */ div.s $f10, $f18, $f16
/* B7B330 80104190 460A2402 */ mul.s $f16, $f4, $f10
/* B7B334 80104194 00000000 */ nop
/* B7B338 80104198 460A3482 */ mul.s $f18, $f6, $f10
/* B7B33C 8010419C 00000000 */ nop
/* B7B340 801041A0 460A4102 */ mul.s $f4, $f8, $f10
/* B7B344 801041A4 E4900000 */ swc1 $f16, ($a0)
/* B7B348 801041A8 E4B20000 */ swc1 $f18, ($a1)
/* B7B34C 801041AC 03E00008 */ jr $ra
/* B7B350 801041B0 E4C40000 */ swc1 $f4, ($a2)
LEAF(guNormalize)
lwc1 $f4, ($a0)
lwc1 $f6, ($a1)
lwc1 $f8, ($a2)
mul.s $f10, $f4, $f4
li $t0, 0x3F800000 // 1.0f
mul.s $f16, $f6, $f6
add.s $f18, $f10, $f16
mul.s $f16, $f8, $f8
add.s $f10, $f16, $f18
mtc1 $t0, $f18
sqrt.s $f16, $f10
div.s $f10, $f18, $f16
mul.s $f16, $f4, $f10
nop
mul.s $f18, $f6, $f10
nop
mul.s $f4, $f8, $f10
swc1 $f16, ($a0)
swc1 $f18, ($a1)
jr $ra
swc1 $f4, ($a2)
END(guNormalize)

95
asm/guScale.s
View file

@ -1,53 +1,52 @@
.include "macro.inc"
#include "ultra64/asm.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
.balign 32
glabel guScale
/* B77380 801001E0 3C014780 */ li $at, 0x47800000 # 0.000000
/* B77384 801001E4 44812000 */ mtc1 $at, $f4
/* B77388 801001E8 44853000 */ mtc1 $a1, $f6
/* B7738C 801001EC AC800004 */ sw $zero, 4($a0)
/* B77390 801001F0 AC80000C */ sw $zero, 0xc($a0)
/* B77394 801001F4 46043202 */ mul.s $f8, $f6, $f4
/* B77398 801001F8 44863000 */ mtc1 $a2, $f6
/* B7739C 801001FC AC800010 */ sw $zero, 0x10($a0)
/* B773A0 80100200 AC800018 */ sw $zero, 0x18($a0)
/* B773A4 80100204 AC800024 */ sw $zero, 0x24($a0)
/* B773A8 80100208 AC80002C */ sw $zero, 0x2c($a0)
/* B773AC 8010020C AC800030 */ sw $zero, 0x30($a0)
/* B773B0 80100210 4600428D */ trunc.w.s $f10, $f8
/* B773B4 80100214 46043202 */ mul.s $f8, $f6, $f4
/* B773B8 80100218 44873000 */ mtc1 $a3, $f6
/* B773BC 8010021C AC800038 */ sw $zero, 0x38($a0)
/* B773C0 80100220 44095000 */ mfc1 $t1, $f10
/* B773C4 80100224 AC80003C */ sw $zero, 0x3c($a0)
/* B773C8 80100228 00095402 */ srl $t2, $t1, 0x10
/* B773CC 8010022C 4600428D */ trunc.w.s $f10, $f8
/* B773D0 80100230 46043202 */ mul.s $f8, $f6, $f4
/* B773D4 80100234 000A4400 */ sll $t0, $t2, 0x10
/* B773D8 80100238 00095400 */ sll $t2, $t1, 0x10
/* B773DC 8010023C 44095000 */ mfc1 $t1, $f10
/* B773E0 80100240 AC880000 */ sw $t0, ($a0)
/* B773E4 80100244 AC8A0020 */ sw $t2, 0x20($a0)
/* B773E8 80100248 00094402 */ srl $t0, $t1, 0x10
/* B773EC 8010024C 4600428D */ trunc.w.s $f10, $f8
/* B773F0 80100250 312AFFFF */ andi $t2, $t1, 0xffff
/* B773F4 80100254 AC8A0028 */ sw $t2, 0x28($a0)
/* B773F8 80100258 AC880008 */ sw $t0, 8($a0)
/* B773FC 8010025C 44095000 */ mfc1 $t1, $f10
/* B77400 80100260 00000000 */ nop
/* B77404 80100264 00095402 */ srl $t2, $t1, 0x10
/* B77408 80100268 000A4400 */ sll $t0, $t2, 0x10
/* B7740C 8010026C AC880014 */ sw $t0, 0x14($a0)
/* B77410 80100270 24080001 */ li $t0, 1
/* B77414 80100274 00095400 */ sll $t2, $t1, 0x10
/* B77418 80100278 AC8A0034 */ sw $t2, 0x34($a0)
/* B7741C 8010027C 03E00008 */ jr $ra
/* B77420 80100280 AC88001C */ sw $t0, 0x1c($a0)
LEAF(guScale)
li $at, 0x47800000 // 65536.0f
mtc1 $at, $f4
mtc1 $a1, $f6
sw $zero, 4($a0)
sw $zero, 0xC($a0)
mul.s $f8, $f6, $f4
mtc1 $a2, $f6
sw $zero, 0x10($a0)
sw $zero, 0x18($a0)
sw $zero, 0x24($a0)
sw $zero, 0x2C($a0)
sw $zero, 0x30($a0)
trunc.w.s $f10, $f8
mul.s $f8, $f6, $f4
mtc1 $a3, $f6
sw $zero, 0x38($a0)
mfc1 $t1, $f10
sw $zero, 0x3C($a0)
srl $t2, $t1, 0x10
trunc.w.s $f10, $f8
mul.s $f8, $f6, $f4
sll $t0, $t2, 0x10
sll $t2, $t1, 0x10
mfc1 $t1, $f10
sw $t0, ($a0)
sw $t2, 0x20($a0)
srl $t0, $t1, 0x10
trunc.w.s $f10, $f8
andi $t2, $t1, 0xFFFF
sw $t2, 0x28($a0)
sw $t0, 8($a0)
mfc1 $t1, $f10
nop
srl $t2, $t1, 0x10
sll $t0, $t2, 0x10
sw $t0, 0x14($a0)
li $t0, 1
sll $t2, $t1, 0x10
sw $t2, 0x34($a0)
jr $ra
sw $t0, 0x1C($a0)
END(guScale)

117
asm/guTranslate.s
View file

@ -1,66 +1,61 @@
.include "macro.inc"
#include "ultra64/asm.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
.balign 32
/* B7CDB0 80105C10 00000000 */ nop
/* B7CDB4 80105C14 00000000 */ nop
/* B7CDB8 80105C18 00000000 */ nop
/* B7CDBC 80105C1C 00000000 */ nop
glabel guTranslate
/* B7CDC0 80105C20 3C014780 */ li $at, 0x47800000 # 0.000000
/* B7CDC4 80105C24 44812000 */ mtc1 $at, $f4
/* B7CDC8 80105C28 44853000 */ mtc1 $a1, $f6
/* B7CDCC 80105C2C AC800000 */ sw $zero, ($a0)
/* B7CDD0 80105C30 AC800014 */ sw $zero, 0x14($a0)
/* B7CDD4 80105C34 46043202 */ mul.s $f8, $f6, $f4
/* B7CDD8 80105C38 44863000 */ mtc1 $a2, $f6
/* B7CDDC 80105C3C AC800008 */ sw $zero, 8($a0)
/* B7CDE0 80105C40 AC800004 */ sw $zero, 4($a0)
/* B7CDE4 80105C44 AC80000C */ sw $zero, 0xc($a0)
/* B7CDE8 80105C48 AC800010 */ sw $zero, 0x10($a0)
/* B7CDEC 80105C4C AC800020 */ sw $zero, 0x20($a0)
/* B7CDF0 80105C50 4600428D */ trunc.w.s $f10, $f8
/* B7CDF4 80105C54 46043202 */ mul.s $f8, $f6, $f4
/* B7CDF8 80105C58 44873000 */ mtc1 $a3, $f6
/* B7CDFC 80105C5C AC800024 */ sw $zero, 0x24($a0)
/* B7CE00 80105C60 44095000 */ mfc1 $t1, $f10
/* B7CE04 80105C64 AC800028 */ sw $zero, 0x28($a0)
/* B7CE08 80105C68 AC80002C */ sw $zero, 0x2c($a0)
/* B7CE0C 80105C6C 00095402 */ srl $t2, $t1, 0x10
/* B7CE10 80105C70 4600428D */ trunc.w.s $f10, $f8
/* B7CE14 80105C74 46043202 */ mul.s $f8, $f6, $f4
/* B7CE18 80105C78 000A4400 */ sll $t0, $t2, 0x10
/* B7CE1C 80105C7C AC800030 */ sw $zero, 0x30($a0)
/* B7CE20 80105C80 440B5000 */ mfc1 $t3, $f10
/* B7CE24 80105C84 AC800034 */ sw $zero, 0x34($a0)
/* B7CE28 80105C88 000B5402 */ srl $t2, $t3, 0x10
/* B7CE2C 80105C8C 4600428D */ trunc.w.s $f10, $f8
/* B7CE30 80105C90 010A4025 */ or $t0, $t0, $t2
/* B7CE34 80105C94 AC880018 */ sw $t0, 0x18($a0)
/* B7CE38 80105C98 00094400 */ sll $t0, $t1, 0x10
/* B7CE3C 80105C9C 000B5400 */ sll $t2, $t3, 0x10
/* B7CE40 80105CA0 44095000 */ mfc1 $t1, $f10
/* B7CE44 80105CA4 000A5402 */ srl $t2, $t2, 0x10
/* B7CE48 80105CA8 010A4025 */ or $t0, $t0, $t2
/* B7CE4C 80105CAC AC880038 */ sw $t0, 0x38($a0)
/* B7CE50 80105CB0 00095402 */ srl $t2, $t1, 0x10
/* B7CE54 80105CB4 000A4400 */ sll $t0, $t2, 0x10
/* B7CE58 80105CB8 25080001 */ addiu $t0, $t0, 1
/* B7CE5C 80105CBC AC88001C */ sw $t0, 0x1c($a0)
/* B7CE60 80105CC0 3C080001 */ lui $t0, 1
/* B7CE64 80105CC4 35080000 */ ori $t0, $t0, 0
/* B7CE68 80105CC8 AC880000 */ sw $t0, ($a0)
/* B7CE6C 80105CCC AC880014 */ sw $t0, 0x14($a0)
/* B7CE70 80105CD0 3C080000 */ lui $t0, (0x00000001 >> 16) # lui $t0, 0
/* B7CE74 80105CD4 35080001 */ ori $t0, (0x00000001 & 0xFFFF) # ori $t0, $t0, 1
/* B7CE78 80105CD8 00095400 */ sll $t2, $t1, 0x10
/* B7CE7C 80105CDC AC8A003C */ sw $t2, 0x3c($a0)
/* B7CE80 80105CE0 03E00008 */ jr $ra
/* B7CE84 80105CE4 AC880008 */ sw $t0, 8($a0)
LEAF(guTranslate)
li $at, 0x47800000 // 65536.0f
mtc1 $at, $f4
mtc1 $a1, $f6
sw $zero, ($a0)
sw $zero, 0x14($a0)
mul.s $f8, $f6, $f4
mtc1 $a2, $f6
sw $zero, 8($a0)
sw $zero, 4($a0)
sw $zero, 0xC($a0)
sw $zero, 0x10($a0)
sw $zero, 0x20($a0)
trunc.w.s $f10, $f8
mul.s $f8, $f6, $f4
mtc1 $a3, $f6
sw $zero, 0x24($a0)
mfc1 $t1, $f10
sw $zero, 0x28($a0)
sw $zero, 0x2C($a0)
srl $t2, $t1, 0x10
trunc.w.s $f10, $f8
mul.s $f8, $f6, $f4
sll $t0, $t2, 0x10
sw $zero, 0x30($a0)
mfc1 $t3, $f10
sw $zero, 0x34($a0)
srl $t2, $t3, 0x10
trunc.w.s $f10, $f8
or $t0, $t0, $t2
sw $t0, 0x18($a0)
sll $t0, $t1, 0x10
sll $t2, $t3, 0x10
mfc1 $t1, $f10
srl $t2, $t2, 0x10
or $t0, $t0, $t2
sw $t0, 0x38($a0)
srl $t2, $t1, 0x10
sll $t0, $t2, 0x10
addiu $t0, $t0, 1
sw $t0, 0x1C($a0)
lui $t0, 1
ori $t0, $t0, 0
sw $t0, ($a0)
sw $t0, 0x14($a0)
lui $t0, (0x00000001 >> 16)
ori $t0, (0x00000001 & 0xFFFF)
sll $t2, $t1, 0x10
sw $t2, 0x3C($a0)
jr $ra
sw $t0, 8($a0)
END(guTranslate)

53
asm/interrupt.s Normal file
View file

@ -0,0 +1,53 @@
#include "ultra64/asm.h"
#include "ultra64/r4300.h"
#include "ultra64/thread.h"
.set noat
.set noreorder
.section .text
.balign 16
LEAF(__osDisableInt)
lui $t2, %hi(__OSGlobalIntMask)
addiu $t2, $t2, %lo(__OSGlobalIntMask)
lw $t3, ($t2)
andi $t3, $t3, SR_IMASK
mfc0 $t0, C0_SR
li $at, ~SR_IE
and $t1, $t0, $at
mtc0 $t1, C0_SR
andi $v0, $t0, SR_IE
lw $t0, ($t2)
andi $t0, $t0, SR_IMASK
beq $t0, $t3, No_Change_Global_Int
lui $t2, %hi(__osRunningThread)
//! @bug this addiu should be lw, it may never come up in practice as to reach this code
//! the CPU bits of __OSGlobalIntMask must have changed while this function is running.
addiu $t2, $t2, %lo(__osRunningThread)
lw $t1, THREAD_SR($t2)
andi $t2, $t1, SR_IMASK
and $t2, $t2, $t0
li $at, ~SR_IMASK
and $t1, $t1, $at
or $t1, $t1, $t2
li $at, ~SR_IE
and $t1, $t1, $at
mtc0 $t1, C0_SR
nop
nop
No_Change_Global_Int:
jr $ra
nop
END(__osDisableInt)
LEAF(__osRestoreInt)
mfc0 $t0, C0_SR
or $t0, $t0, $a0
mtc0 $t0, C0_SR
nop
nop
jr $ra
nop
END(__osRestoreInt)

6
asm/ipl3.s
View file

@ -1,9 +1,3 @@
.include "macro.inc"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.section .text

10
asm/libm_vals.s
View file

@ -1,13 +1,9 @@
.include "macro.inc"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
#include "ultra64/asm.h"
.section .rodata
.balign 16
glabel __libm_qnan_f
DATA(__libm_qnan_f)
.word 0x7F810000
ENDDATA(__libm_qnan_f)

115
asm/mio0.s
View file

@ -1,62 +1,65 @@
.include "macro.inc"
#include "ultra64/asm.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
glabel Mio0_Decompress
/* 0031B0 800025B0 8C870008 */ lw $a3, 8($a0)
/* 0031B4 800025B4 8C99000C */ lw $t9, 0xc($a0)
/* 0031B8 800025B8 8C980004 */ lw $t8, 4($a0)
/* 0031BC 800025BC 00E43820 */ add $a3, $a3, $a0
/* 0031C0 800025C0 0324C820 */ add $t9, $t9, $a0
/* 0031C4 800025C4 00003025 */ move $a2, $zero
/* 0031C8 800025C8 20840010 */ addi $a0, $a0, 0x10
/* 0031CC 800025CC 0305C020 */ add $t8, $t8, $a1
.L800025D0:
/* 0031D0 800025D0 14C00004 */ bnez $a2, .L800025E4
/* 0031D4 800025D4 00000000 */ nop
/* 0031D8 800025D8 8C880000 */ lw $t0, ($a0)
/* 0031DC 800025DC 24060020 */ li $a2, 32
/* 0031E0 800025E0 20840004 */ addi $a0, $a0, 4
.L800025E4:
/* 0031E4 800025E4 0100482A */ slt $t1, $t0, $zero
/* 0031E8 800025E8 11200006 */ beqz $t1, .L80002604
/* 0031EC 800025EC 00000000 */ nop
/* 0031F0 800025F0 832A0000 */ lb $t2, ($t9)
/* 0031F4 800025F4 23390001 */ addi $t9, $t9, 1
/* 0031F8 800025F8 20A50001 */ addi $a1, $a1, 1
/* 0031FC 800025FC 1000000E */ b .L80002638
/* 003200 80002600 A0AAFFFF */ sb $t2, -1($a1)
.L80002604:
/* 003204 80002604 94EA0000 */ lhu $t2, ($a3)
/* 003208 80002608 20E70002 */ addi $a3, $a3, 2
/* 00320C 8000260C 000A5B02 */ srl $t3, $t2, 0xc
/* 003210 80002610 314A0FFF */ andi $t2, $t2, 0xfff
/* 003214 80002614 1160000D */ beqz $t3, .L8000264C
/* 003218 80002618 00AA4822 */ sub $t1, $a1, $t2
/* 00321C 8000261C 216B0002 */ addi $t3, $t3, 2
.L80002620:
/* 003220 80002620 812AFFFF */ lb $t2, -1($t1)
/* 003224 80002624 216BFFFF */ addi $t3, $t3, -1
/* 003228 80002628 21290001 */ addi $t1, $t1, 1
/* 00322C 8000262C 20A50001 */ addi $a1, $a1, 1
/* 003230 80002630 1560FFFB */ bnez $t3, .L80002620
/* 003234 80002634 A0AAFFFF */ sb $t2, -1($a1)
.L80002638:
/* 003238 80002638 00084040 */ sll $t0, $t0, 1
/* 00323C 8000263C 14B8FFE4 */ bne $a1, $t8, .L800025D0
/* 003240 80002640 20C6FFFF */ addi $a2, $a2, -1
/* 003244 80002644 03E00008 */ jr $ra
/* 003248 80002648 00000000 */ nop
.L8000264C:
/* 00324C 8000264C 932B0000 */ lbu $t3, ($t9)
/* 003250 80002650 23390001 */ addi $t9, $t9, 1
/* 003254 80002654 1000FFF2 */ b .L80002620
/* 003258 80002658 216B0012 */ addi $t3, $t3, 0x12
/* 00325C 8000265C 00000000 */ nop
/**
* void Mio0_Decompress(void* src, void* dst);
*
* Decompress Mio0 chunk
*/
LEAF(Mio0_Decompress)
lw $a3, 8($a0) // compressed offset
lw $t9, 0xC($a0) // uncompressed offset
lw $t8, 4($a0) // decompressed length
add $a3, $a3, $a0 // compressed start
add $t9, $t9, $a0 // uncompressed start
move $a2, $zero // 0
addi $a0, $a0, 0x10 // move past header
add $t8, $t8, $a1 // dst + decompressed length = end
mainloop:
bnez $a2, 1f
nop
lw $t0, ($a0)
li $a2, 32
addi $a0, $a0, 4
1:
slt $t1, $t0, $zero
beqz $t1, read_comp
nop
lb $t2, ($t9) // read 1 byte from uncompressed data
addi $t9, $t9, 1 // advance uncompressed start
addi $a1, $a1, 1
b next_iter
sb $t2, -1($a1) // store uncompressed byte
read_comp:
lhu $t2, ($a3) // read 2 bytes from compressed data
addi $a3, $a3, 2 // advance compressed start
srl $t3, $t2, 0xC
andi $t2, $t2, 0xFFF
beqz $t3, 3f
sub $t1, $a1, $t2
addi $t3, $t3, 2
2:
lb $t2, -1($t1)
addi $t3, $t3, -1
addi $t1, $t1, 1
addi $a1, $a1, 1
bnez $t3, 2b
sb $t2, -1($a1)
next_iter:
sll $t0, $t0, 1
bne $a1, $t8, mainloop // continue until decompressed length is reached
addi $a2, $a2, -1
jr $ra
nop
3:
lbu $t3, ($t9)
addi $t9, $t9, 1
b 2b
addi $t3, $t3, 0x12
END(Mio0_Decompress)

18
asm/osGetCount.s
View file

@ -1,15 +1,15 @@
.include "macro.inc"
#include "ultra64/asm.h"
#include "ultra64/r4300.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
glabel osGetCount
/* 007AA0 80006EA0 40024800 */ mfc0 $v0, $9
/* 007AA4 80006EA4 03E00008 */ jr $ra
/* 007AA8 80006EA8 00000000 */ nop
LEAF(osGetCount)
mfc0 $v0, C0_COUNT
jr $ra
nop
END(osGetCount)

141
asm/osInvalDCache.s
View file

@ -1,61 +1,94 @@
.include "macro.inc"
#include "ultra64/asm.h"
#include "ultra64/r4300.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
glabel osInvalDCache
/* 006E00 80006200 18A0001F */ blez $a1, .L80006280
/* 006E04 80006204 00000000 */ nop
/* 006E08 80006208 240B2000 */ li $t3, 8192
/* 006E0C 8000620C 00AB082B */ sltu $at, $a1, $t3
/* 006E10 80006210 1020001D */ beqz $at, .L80006288
/* 006E14 80006214 00000000 */ nop
/* 006E18 80006218 00804025 */ move $t0, $a0
/* 006E1C 8000621C 00854821 */ addu $t1, $a0, $a1
/* 006E20 80006220 0109082B */ sltu $at, $t0, $t1
/* 006E24 80006224 10200016 */ beqz $at, .L80006280
/* 006E28 80006228 00000000 */ nop
/* 006E2C 8000622C 310A000F */ andi $t2, $t0, 0xf
/* 006E30 80006230 11400007 */ beqz $t2, .L80006250
/* 006E34 80006234 2529FFF0 */ addiu $t1, $t1, -0x10
/* 006E38 80006238 010A4023 */ subu $t0, $t0, $t2
/* 006E3C 8000623C BD150000 */ cache 0x15, ($t0)
/* 006E40 80006240 0109082B */ sltu $at, $t0, $t1
/* 006E44 80006244 1020000E */ beqz $at, .L80006280
/* 006E48 80006248 00000000 */ nop
/* 006E4C 8000624C 25080010 */ addiu $t0, $t0, 0x10
.L80006250:
/* 006E50 80006250 312A000F */ andi $t2, $t1, 0xf
/* 006E54 80006254 11400006 */ beqz $t2, .L80006270
/* 006E58 80006258 00000000 */ nop
/* 006E5C 8000625C 012A4823 */ subu $t1, $t1, $t2
/* 006E60 80006260 BD350010 */ cache 0x15, 0x10($t1)
/* 006E64 80006264 0128082B */ sltu $at, $t1, $t0
/* 006E68 80006268 14200005 */ bnez $at, .L80006280
/* 006E6C 8000626C 00000000 */ nop
.L80006270:
/* 006E70 80006270 BD110000 */ cache 0x11, ($t0)
/* 006E74 80006274 0109082B */ sltu $at, $t0, $t1
/* 006E78 80006278 1420FFFD */ bnez $at, .L80006270
/* 006E7C 8000627C 25080010 */ addiu $t0, $t0, 0x10
.L80006280:
/* 006E80 80006280 03E00008 */ jr $ra
/* 006E84 80006284 00000000 */ nop
/**
* void osInvalDCache(void* vaddr, s32 nbytes);
*
* Invalidates the CPU Data Cache for `nbytes` at `vaddr`.
* The cache is not automatically synced with physical memory, so cache
* lines must be invalidated to ensure old data is not used in place of
* newly available data supplied by an external agent in a DMA operation.
*
* If `vaddr` is not aligned to a cache line boundary, or nbytes is not a
* multiple of the data cache line size (16 bytes) a larger region is
* invalidated.
*
* If the amount to invalidate is at least the data cache size (DCACHE_SIZE),
* the entire data cache is invalidated.
*/
LEAF(osInvalDCache)
// If the amount to invalidate is less than or equal to 0, return immediately
blez $a1, 3f
nop
// If the amount to invalidate is as large as or larger than
// the data cache size, invalidate all
li $t3, DCACHE_SIZE
sltu $at, $a1, $t3
beqz $at, 4f
nop
// Ensure end address doesn't wrap around and end up smaller
// than the start address
move $t0, $a0
addu $t1, $a0, $a1
sltu $at, $t0, $t1
beqz $at, 3f
nop
// Mask start with cache line
andi $t2, $t0, DCACHE_LINEMASK
// If mask is not zero, the start is not cache aligned
beqz $t2, 1f
addiu $t1, $t1, -DCACHE_LINESIZE
// Subtract mask result to align to cache line
subu $t0, $t0, $t2
// Hit-Writeback-Invalidate unaligned part
cache (CACH_PD | C_HWBINV), ($t0)
sltu $at, $t0, $t1
// If that's all there is to do, return early
beqz $at, 3f
nop
addiu $t0, $t0, DCACHE_LINESIZE
1:
// Mask end with cache line
andi $t2, $t1, DCACHE_LINEMASK
// If mask is not zero, the end is not cache aligned
beqz $t2, 1f
nop
// Subtract mask result to align to cache line
subu $t1, $t1, $t2
// Hit-Writeback-Invalidate unaligned part
cache (CACH_PD | C_HWBINV), DCACHE_LINESIZE($t1)
sltu $at, $t1, $t0
// If that's all there is to do, return early
bnez $at, 3f
nop
// Invalidate the rest
1:
// Hit-Invalidate
cache (CACH_PD | C_HINV), ($t0)
sltu $at, $t0, $t1
bnez $at, 1b
addiu $t0, $t0, DCACHE_LINESIZE
3:
jr $ra
nop
.L80006288:
/* 006E88 80006288 3C088000 */ lui $t0, 0x8000
/* 006E8C 8000628C 010B4821 */ addu $t1, $t0, $t3
/* 006E90 80006290 2529FFF0 */ addiu $t1, $t1, -0x10
.L80006294:
/* 006E94 80006294 BD010000 */ cache 1, ($t0)
/* 006E98 80006298 0109082B */ sltu $at, $t0, $t1
/* 006E9C 8000629C 1420FFFD */ bnez $at, .L80006294
/* 006EA0 800062A0 25080010 */ addiu $t0, 0x10
/* 006EA4 800062A4 03E00008 */ jr $ra
/* 006EA8 800062A8 00000000 */ nop
4:
li $t0, K0BASE
addu $t1, $t0, $t3
addiu $t1, $t1, -DCACHE_LINESIZE
5:
// Index-Writeback-Invalidate
cache (CACH_PD | C_IWBINV), ($t0)
sltu $at, $t0, $t1
bnez $at, 5b
addiu $t0, DCACHE_LINESIZE
jr $ra
nop
END(osInvalDCache)

84
asm/osInvalICache.s
View file

@ -1,46 +1,52 @@
.include "macro.inc"
#include "ultra64/asm.h"
#include "ultra64/r4300.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
glabel osInvalICache
/* 006D50 80006150 18A00011 */ blez $a1, .L80006198
/* 006D54 80006154 00000000 */ nop
/* 006D58 80006158 240B4000 */ li $t3, 16384
/* 006D5C 8000615C 00AB082B */ sltu $at, $a1, $t3
/* 006D60 80006160 1020000F */ beqz $at, .L800061A0
/* 006D64 80006164 00000000 */ nop
/* 006D68 80006168 00804025 */ move $t0, $a0
/* 006D6C 8000616C 00854821 */ addu $t1, $a0, $a1
/* 006D70 80006170 0109082B */ sltu $at, $t0, $t1
/* 006D74 80006174 10200008 */ beqz $at, .L80006198
/* 006D78 80006178 00000000 */ nop
/* 006D7C 8000617C 310A001F */ andi $t2, $t0, 0x1f
/* 006D80 80006180 2529FFE0 */ addiu $t1, $t1, -0x20
/* 006D84 80006184 010A4023 */ subu $t0, $t0, $t2
.L80006188:
/* 006D88 80006188 BD100000 */ cache 0x10, ($t0)
/* 006D8C 8000618C 0109082B */ sltu $at, $t0, $t1
/* 006D90 80006190 1420FFFD */ bnez $at, .L80006188
/* 006D94 80006194 25080020 */ addiu $t0, $t0, 0x20
.L80006198:
/* 006D98 80006198 03E00008 */ jr $ra
/* 006D9C 8000619C 00000000 */ nop
LEAF(osInvalICache)
// If the amount to invalidate is less than or equal to 0, return immediately
blez $a1, 2f
nop
// If the amount to invalidate is as large as or larger than
// the instruction cache size, invalidate all
li $t3, ICACHE_SIZE
sltu $at, $a1, $t3
beqz $at, 3f
nop
// ensure end address doesn't wrap around and end up smaller
// than the start address
move $t0, $a0
addu $t1, $a0, $a1
sltu $at, $t0, $t1
beqz $at, 2f
nop
// Mask and subtract to align to cache line
andi $t2, $t0, ICACHE_LINEMASK
addiu $t1, $t1, -ICACHE_LINESIZE
subu $t0, $t0, $t2
1:
cache (CACH_PI | C_HINV), ($t0)
sltu $at, $t0, $t1
bnez $at, 1b
addiu $t0, $t0, ICACHE_LINESIZE
2:
jr $ra
nop
.L800061A0:
/* 006DA0 800061A0 3C088000 */ lui $t0, 0x8000
/* 006DA4 800061A4 010B4821 */ addu $t1, $t0, $t3
/* 006DA8 800061A8 2529FFE0 */ addiu $t1, $t1, -0x20
.L800061AC:
/* 006DAC 800061AC BD000000 */ cache 0, ($t0)
/* 006DB0 800061B0 0109082B */ sltu $at, $t0, $t1
/* 006DB4 800061B4 1420FFFD */ bnez $at, .L800061AC
/* 006DB8 800061B8 25080020 */ addiu $t0, 0x20
/* 006DBC 800061BC 03E00008 */ jr $ra
/* 006DC0 800061C0 00000000 */ nop
3:
li $t0, K0BASE
addu $t1, $t0, $t3
addiu $t1, $t1, -ICACHE_LINESIZE
4:
cache (CACH_PI | C_IINV), ($t0)
sltu $at, $t0, $t1
bnez $at, 4b
addiu $t0, ICACHE_LINESIZE
jr $ra
nop
END(osInvalICache)

59
asm/osMapTLBRdb.s
View file

@ -1,34 +1,37 @@
.include "macro.inc"
#include "ultra64/asm.h"
#include "ultra64/r4300.h"
#include "ultra64/rdb.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
glabel osMapTLBRdb
/* 0086E0 80007AE0 40085000 */ mfc0 $t0, $10
/* 0086E4 80007AE4 2409001F */ li $t1, 31
/* 0086E8 80007AE8 40890000 */ mtc0 $t1, $0
/* 0086EC 80007AEC 40802800 */ mtc0 $zero, $5
/* 0086F0 80007AF0 240A0017 */ li $t2, 23
/* 0086F4 80007AF4 3C09C000 */ lui $t1, 0xc000
/* 0086F8 80007AF8 40895000 */ mtc0 $t1, $10
/* 0086FC 80007AFC 3C098000 */ lui $t1, 0x8000
/* 008700 80007B00 00095982 */ srl $t3, $t1, 6
/* 008704 80007B04 016A5825 */ or $t3, $t3, $t2
/* 008708 80007B08 408B1000 */ mtc0 $t3, $2
/* 00870C 80007B0C 24090001 */ li $t1, 1
/* 008710 80007B10 40891800 */ mtc0 $t1, $3
/* 008714 80007B14 00000000 */ nop
/* 008718 80007B18 42000002 */ tlbwi
/* 00871C 80007B1C 00000000 */ nop
/* 008720 80007B20 00000000 */ nop
/* 008724 80007B24 00000000 */ nop
/* 008728 80007B28 00000000 */ nop
/* 00872C 80007B2C 40885000 */ mtc0 $t0, $10
/* 008730 80007B30 03E00008 */ jr $ra
/* 008734 80007B34 00000000 */ nop
LEAF(osMapTLBRdb)
mfc0 $t0, C0_ENTRYHI
li $t1, NTLBENTRIES
mtc0 $t1, C0_INX
mtc0 $zero, C0_PAGEMASK
li $t2, (TLBLO_UNCACHED | TLBLO_D | TLBLO_V | TLBLO_G)
li $t1, (RDB_BASE_REG & TLBHI_VPN2MASK)
mtc0 $t1, C0_ENTRYHI
// Possible bug? Virtual address instead of physical address
// set as page frame number
li $t1, RDB_BASE_VIRTUAL_ADDR
srl $t3, $t1, TLBLO_PFNSHIFT
or $t3, $t3, $t2
mtc0 $t3, C0_ENTRYLO0
li $t1, TLBLO_G
mtc0 $t1, C0_ENTRYLO1
nop
tlbwi
nop
nop
nop
nop
mtc0 $t0, C0_ENTRYHI
jr $ra
nop
END(osMapTLBRdb)

279
asm/osSetIntMask.s
View file

@ -1,123 +1,168 @@
.include "macro.inc"
#include "ultra64/asm.h"
#include "ultra64/r4300.h"
#include "ultra64/rcp.h"
#include "ultra64/exception.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.section .text
.balign 16
glabel osSetIntMask
/* 005B40 80004F40 400C6000 */ mfc0 $t4, $12
/* 005B44 80004F44 3182FF01 */ andi $v0, $t4, 0xff01
/* 005B48 80004F48 3C088001 */ lui $t0, %hi(__OSGlobalIntMask) # $t0, 0x8001
/* 005B4C 80004F4C 2508AD00 */ addiu $t0, %lo(__OSGlobalIntMask) # addiu $t0, $t0, -0x5300
/* 005B50 80004F50 8D0B0000 */ lw $t3, ($t0)
/* 005B54 80004F54 2401FFFF */ li $at, -1
/* 005B58 80004F58 01614026 */ xor $t0, $t3, $at
/* 005B5C 80004F5C 3108FF00 */ andi $t0, $t0, 0xff00
/* 005B60 80004F60 00481025 */ or $v0, $v0, $t0
/* 005B64 80004F64 3C0AA430 */ lui $t2, %hi(D_A430000C) # $t2, 0xa430
/* 005B68 80004F68 8D4A000C */ lw $t2, %lo(D_A430000C)($t2)
/* 005B6C 80004F6C 11400005 */ beqz $t2, .L80004F84
/* 005B70 80004F70 000B4C02 */ srl $t1, $t3, 0x10
/* 005B74 80004F74 2401FFFF */ li $at, -1
/* 005B78 80004F78 01214826 */ xor $t1, $t1, $at
/* 005B7C 80004F7C 3129003F */ andi $t1, $t1, 0x3f
/* 005B80 80004F80 01495025 */ or $t2, $t2, $t1
.L80004F84:
/* 005B84 80004F84 000A5400 */ sll $t2, $t2, 0x10
/* 005B88 80004F88 004A1025 */ or $v0, $v0, $t2
/* 005B8C 80004F8C 3C01003F */ lui $at, 0x3f
/* 005B90 80004F90 00814024 */ and $t0, $a0, $at
/* 005B94 80004F94 010B4024 */ and $t0, $t0, $t3
/* 005B98 80004F98 000843C2 */ srl $t0, $t0, 0xf
/* 005B9C 80004F9C 3C0A8001 */ lui $t2, %hi(__osRcpImTable)
/* 005BA0 80004FA0 01485021 */ addu $t2, $t2, $t0
/* 005BA4 80004FA4 954A2160 */ lhu $t2, %lo(__osRcpImTable)($t2)
/* 005BA8 80004FA8 3C01A430 */ lui $at, %hi(D_A430000C) # $at, 0xa430
/* 005BAC 80004FAC AC2A000C */ sw $t2, %lo(D_A430000C)($at)
/* 005BB0 80004FB0 3088FF01 */ andi $t0, $a0, 0xff01
/* 005BB4 80004FB4 3169FF00 */ andi $t1, $t3, 0xff00
/* 005BB8 80004FB8 01094024 */ and $t0, $t0, $t1
/* 005BBC 80004FBC 3C01FFFF */ lui $at, (0xFFFF00FF >> 16) # lui $at, 0xffff
/* 005BC0 80004FC0 342100FF */ ori $at, (0xFFFF00FF & 0xFFFF) # ori $at, $at, 0xff
/* 005BC4 80004FC4 01816024 */ and $t4, $t4, $at
/* 005BC8 80004FC8 01886025 */ or $t4, $t4, $t0
/* 005BCC 80004FCC 408C6000 */ mtc0 $t4, $12
/* 005BD0 80004FD0 00000000 */ nop
/* 005BD4 80004FD4 00000000 */ nop
/* 005BD8 80004FD8 03E00008 */ jr $ra
/* 005BDC 80004FDC 00000000 */ nop
.set noat
.set noreorder
.section .rodata
.balign 16
glabel __osRcpImTable
.half 0x0555
.half 0x0556
.half 0x0559
.half 0x055A
.half 0x0565
.half 0x0566
.half 0x0569
.half 0x056A
.half 0x0595
.half 0x0596
.half 0x0599
.half 0x059A
.half 0x05A5
.half 0x05A6
.half 0x05A9
.half 0x05AA
.half 0x0655
.half 0x0656
.half 0x0659
.half 0x065A
.half 0x0665
.half 0x0666
.half 0x0669
.half 0x066A
.half 0x0695
.half 0x0696
.half 0x0699
.half 0x069A
.half 0x06A5
.half 0x06A6
.half 0x06A9
.half 0x06AA
.half 0x0955
.half 0x0956
.half 0x0959
.half 0x095A
.half 0x0965
.half 0x0966
.half 0x0969
.half 0x096A
.half 0x0995
.half 0x0996
.half 0x0999
.half 0x099A
.half 0x09A5
.half 0x09A6
.half 0x09A9
.half 0x09AA
.half 0x0A55
.half 0x0A56
.half 0x0A59
.half 0x0A5A
.half 0x0A65
.half 0x0A66
.half 0x0A69
.half 0x0A6A
.half 0x0A95
.half 0x0A96
.half 0x0A99
.half 0x0A9A
.half 0x0AA5
.half 0x0AA6
.half 0x0AA9
.half 0x0AAA
/**
* LUT to convert between an interrupt mask value and a value for MI_INTR_MASK_REG.
* The interrupt mask value is a single bit 0 = disabled, 1 = enabled, while writes to MI_INTR_MASK_REG has two distinct non-zero
* values for set and clear, hence the need for a conversion step.
*/
DATA(__osRcpImTable)
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_CLR_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_CLR_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_CLR_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_CLR_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_CLR_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_CLR_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
.half MI_INTR_MASK_SET_SP | MI_INTR_MASK_SET_SI | MI_INTR_MASK_SET_AI | MI_INTR_MASK_SET_VI | MI_INTR_MASK_SET_PI | MI_INTR_MASK_SET_DP
ENDDATA(__osRcpImTable)
.section .text
.balign 16
/**
* OSIntMask osSetIntMask(OSIntMask);
*
* Sets the interrupt enable mask for the current thread. External interrupts
* originating either in the CPU or the RCP may be "masked out" so that they
* are not handled. This is sometimes important for critical code sections
* that must not be interrupted.
* Interrupts that are not enabled in the global interrupt mask __OSGlobalIntMask
* cannot be set here. The global interrupt mask is OS-internal and is not
* expected to change during runtime.
* The returned value is the previous interrupt enable mask so that it can be
* restored later.
*
* @bug Some usage of the global interrupt mask is broken both in here and in the
* exception handler routines.
* While a thread is running, the C0_SR interrupt enable bits contain the
* interrupt enable bits for the current thread masked by the global
* interrupt mask. There is an attempt to recover only the original interrupt
* enable bits belonging to the thread itself using the operation
* (SR | ~__OSGlobalIntMask).
* However, this does not work as intended and can cause interrupts to end
* up enabled when not intended to be. The same issue is present for the
* RCP interrupt enable bits in MI_INTR_MASK_REG.
* This does not cause issues in practice as __OSGlobalIntMask is almost always
* OS_IM_ALL, so the operation is usually simply (SR | 0).
*/
LEAF(osSetIntMask)
// Extract interrupt enable bits from current SR
mfc0 $t4, C0_SR
andi $v0, $t4, (SR_IMASK | SR_IE)
// Get value of __OSGlobalIntMask
lui $t0, %hi(__OSGlobalIntMask)
addiu $t0, %lo(__OSGlobalIntMask)
lw $t3, ($t0)
// Bitwise-OR in the disabled CPU bits of __OSGlobalIntMask
li $at, ~0
xor $t0, $t3, $at
andi $t0, $t0, SR_IMASK
or $v0, $v0, $t0
// Fetch MI_INTR_MASK_REG
lui $t2, %hi(PHYS_TO_K1(MI_INTR_MASK_REG))
lw $t2, %lo(PHYS_TO_K1(MI_INTR_MASK_REG))($t2)
// If there are RCP interrupts masked
beqz $t2, 1f
srl $t1, $t3, RCP_IMASKSHIFT
// Bitwise-OR in the disabled RCP bits of __OSGlobalIntMask
li $at, ~0
xor $t1, $t1, $at
andi $t1, $t1, (RCP_IMASK >> RCP_IMASKSHIFT)
or $t2, $t2, $t1
1:
// Shift the RCP bits to not conflict with the CPU bits
sll $t2, $t2, RCP_IMASKSHIFT
// OR the CPU and RCP bits together
or $v0, $v0, $t2
// Extract RCP interrupt enable bits from requested mask and mask with __OSGlobalIntMask
li $at, RCP_IMASK
and $t0, $a0, $at
and $t0, $t0, $t3
// Convert to a value for MI_INTR_MASK_REG and set it
srl $t0, $t0, (RCP_IMASKSHIFT-1)
lui $t2, %hi(__osRcpImTable)
addu $t2, $t2, $t0
lhu $t2, %lo(__osRcpImTable)($t2)
lui $at, %hi(PHYS_TO_K1(MI_INTR_MASK_REG))
sw $t2, %lo(PHYS_TO_K1(MI_INTR_MASK_REG))($at)
// Extract CPU interrupt enable bits from requested mask and mask with __OSGlobalIntMask
andi $t0, $a0, OS_IM_CPU
andi $t1, $t3, SR_IMASK
and $t0, $t0, $t1
li $at, ~SR_IMASK
and $t4, $t4, $at
// Bitwise OR in the remaining bits of SR and set new SR
or $t4, $t4, $t0
mtc0 $t4, C0_SR
nop
nop
jr $ra
nop
END(osSetIntMask)

48
asm/osUnmapTLBAll.s
View file

@ -1,30 +1,30 @@
.include "macro.inc"
#include "ultra64/asm.h"
#include "ultra64/r4300.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
glabel osUnmapTLBAll
/* 006BC0 80005FC0 40085000 */ mfc0 $t0, $10
/* 006BC4 80005FC4 2409001E */ li $t1, 30
/* 006BC8 80005FC8 3C0A8000 */ lui $t2, 0x8000
/* 006BCC 80005FCC 408A5000 */ mtc0 $t2, $10
/* 006BD0 80005FD0 40801000 */ mtc0 $zero, $2
/* 006BD4 80005FD4 40801800 */ mtc0 $zero, $3
.L80005FD8:
/* 006BD8 80005FD8 40890000 */ mtc0 $t1, $0
/* 006BDC 80005FDC 00000000 */ nop
/* 006BE0 80005FE0 42000002 */ tlbwi
/* 006BE4 80005FE4 00000000 */ nop
/* 006BE8 80005FE8 00000000 */ nop
/* 006BEC 80005FEC 2129FFFF */ addi $t1, $t1, -1
/* 006BF0 80005FF0 0521FFF9 */ bgez $t1, .L80005FD8
/* 006BF4 80005FF4 00000000 */ nop
/* 006BF8 80005FF8 40885000 */ mtc0 $t0, $10
/* 006BFC 80005FFC 03E00008 */ jr $ra
/* 006C00 80006000 00000000 */ nop
LEAF(osUnmapTLBAll)
mfc0 $t0, C0_ENTRYHI
li $t1, (NTLBENTRIES - 1)
li $t2, (K0BASE & TLBHI_VPN2MASK)
mtc0 $t2, C0_ENTRYHI
mtc0 $zero, C0_ENTRYLO0
mtc0 $zero, C0_ENTRYLO1
1:
mtc0 $t1, C0_INX
nop
tlbwi
nop
nop
addi $t1, $t1, -1
bgez $t1, 1b
nop
mtc0 $t0, C0_ENTRYHI
jr $ra
nop
END(osUnmapTLBAll)

92
asm/osWritebackDCache.s
View file

@ -1,46 +1,60 @@
.include "macro.inc"
#include "ultra64/asm.h"
#include "ultra64/r4300.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
glabel osWritebackDCache
/* 0052C0 800046C0 18A00011 */ blez $a1, .L80004708
/* 0052C4 800046C4 00000000 */ nop
/* 0052C8 800046C8 240B2000 */ li $t3, 8192
/* 0052CC 800046CC 00AB082B */ sltu $at, $a1, $t3
/* 0052D0 800046D0 1020000F */ beqz $at, .L80004710
/* 0052D4 800046D4 00000000 */ nop
/* 0052D8 800046D8 00804025 */ move $t0, $a0
/* 0052DC 800046DC 00854821 */ addu $t1, $a0, $a1
/* 0052E0 800046E0 0109082B */ sltu $at, $t0, $t1
/* 0052E4 800046E4 10200008 */ beqz $at, .L80004708
/* 0052E8 800046E8 00000000 */ nop
/* 0052EC 800046EC 310A000F */ andi $t2, $t0, 0xf
/* 0052F0 800046F0 2529FFF0 */ addiu $t1, $t1, -0x10
/* 0052F4 800046F4 010A4023 */ subu $t0, $t0, $t2
.L800046F8:
/* 0052F8 800046F8 BD190000 */ cache 0x19, ($t0)
/* 0052FC 800046FC 0109082B */ sltu $at, $t0, $t1
/* 005300 80004700 1420FFFD */ bnez $at, .L800046F8
/* 005304 80004704 25080010 */ addiu $t0, $t0, 0x10
.L80004708:
/* 005308 80004708 03E00008 */ jr $ra
/* 00530C 8000470C 00000000 */ nop
/**
* void osWritebackDCache(void* vaddr, s32 nbytes);
*
* Writes back the contents of the data cache to main memory for `nbytes` at `vaddr`.
* If `nbytes` is as large as or larger than the data cache size, the entire cache is
* written back.
*/
LEAF(osWritebackDCache)
// If the amount to write back is less than or equal to 0, return immediately
blez $a1, .ret
nop
// If the amount to write back is as large as or larger than
// the data cache size, write back all
li $t3, DCACHE_SIZE
sltu $at, $a1, $t3
beqz $at, .all
nop
// ensure end address doesn't wrap around and end up smaller
// than the start address
move $t0, $a0
addu $t1, $a0, $a1
sltu $at, $t0, $t1
beqz $at, .ret
nop
// Mask and subtract to align to cache line
andi $t2, $t0, DCACHE_LINEMASK
addiu $t1, $t1, -DCACHE_LINESIZE
subu $t0, $t0, $t2
1:
cache (CACH_PD | C_HWB), ($t0)
sltu $at, $t0, $t1
bnez $at, 1b
addiu $t0, $t0, DCACHE_LINESIZE
.ret:
jr $ra
nop
.L80004710:
/* 005310 80004710 3C088000 */ lui $t0, 0x8000
/* 005314 80004714 010B4821 */ addu $t1, $t0, $t3
/* 005318 80004718 2529FFF0 */ addiu $t1, $t1, -0x10
.L8000471C:
/* 00531C 8000471C BD010000 */ cache 1, ($t0)
/* 005320 80004720 0109082B */ sltu $at, $t0, $t1
/* 005324 80004724 1420FFFD */ bnez $at, .L8000471C
/* 005328 80004728 25080010 */ addiu $t0, 0x10
/* 00532C 8000472C 03E00008 */ jr $ra
/* 005330 80004730 00000000 */ nop
// same as osWritebackDCacheAll in operation
.all:
li $t0, K0BASE
addu $t1, $t0, $t3
addiu $t1, $t1, -DCACHE_LINESIZE
1:
cache (CACH_PD | C_IWBINV), ($t0)
sltu $at, $t0, $t1
bnez $at, 1b
addiu $t0, DCACHE_LINESIZE
jr $ra
nop
END(osWritebackDCache)

34
asm/osWritebackDCacheAll.s
View file

@ -1,23 +1,23 @@
.include "macro.inc"
#include "ultra64/asm.h"
#include "ultra64/r4300.h"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purpose registers
.set noat
.set noreorder
.section .text
.balign 16
glabel osWritebackDCacheAll
/* B7D630 80106490 3C088000 */ lui $t0, 0x8000
/* B7D634 80106494 240A2000 */ li $t2, 8192
/* B7D638 80106498 010A4821 */ addu $t1, $t0, $t2
/* B7D63C 8010649C 2529FFF0 */ addiu $t1, $t1, -0x10
.L801064A0:
/* B7D640 801064A0 BD010000 */ cache 1, ($t0)
/* B7D644 801064A4 0109082B */ sltu $at, $t0, $t1
/* B7D648 801064A8 1420FFFD */ bnez $at, .L801064A0
/* B7D64C 801064AC 25080010 */ addiu $t0, 0x10
/* B7D650 801064B0 03E00008 */ jr $ra
/* B7D654 801064B4 00000000 */ nop
LEAF(osWritebackDCacheAll)
li $t0, K0BASE
li $t2, DCACHE_SIZE
addu $t1, $t0, $t2
addiu $t1, $t1, -DCACHE_LINESIZE
1:
cache (CACH_PD | C_IWBINV), ($t0)
sltu $at, $t0, $t1
bnez $at, 1b
addiu $t0, DCACHE_LINESIZE
jr $ra
nop
END(osWritebackDCacheAll)

22
asm/parameters.s Normal file
View file

@ -0,0 +1,22 @@
#include "ultra64/asm.h"
.section .text
.macro IPL_SYMBOL name, address, size
.global \name
.set \name, \address
.type \name, @object
.size \name, \size
.endm
IPL_SYMBOL leoBootID, 0x800001A0, 4
IPL_SYMBOL osTvType, 0x80000300, 4
IPL_SYMBOL osRomType, 0x80000304, 4
IPL_SYMBOL osRomBase, 0x80000308, 4
IPL_SYMBOL osResetType, 0x8000030C, 4
IPL_SYMBOL osCicId, 0x80000310, 4
IPL_SYMBOL osVersion, 0x80000314, 4
IPL_SYMBOL osMemSize, 0x80000318, 4
IPL_SYMBOL osAppNMIBuffer, 0x8000031C, 0x40
.fill 0x60

6
include/boot.h Normal file
View file

@ -0,0 +1,6 @@
#ifndef BOOT_H
#define BOOT_H
#define BOOT_STACK_SIZE 0x400
#endif

3
include/functions.h
View file

@ -85,12 +85,9 @@ void osViExtendVStart(u32 arg0);
s32 osRecvMesg(OSMesgQueue* mq, OSMesg* msg, s32 flag);
void __osInitialize_common(void);
void __osInitialize_autodetect(void);
void __osExceptionPreamble(void);
// ? __osException(?);
void __osEnqueueAndYield(OSThread**);
void __osEnqueueThread(OSThread**, OSThread*);
OSThread* __osPopThread(OSThread**);
// ? __osNop(?);
void __osDispatchThread(void);
void __osCleanupThread(void);
void __osDequeueThread(OSThread** queue, OSThread* thread);

85
include/ultra64/asm.h Normal file
View file

@ -0,0 +1,85 @@
#ifndef ASM_H
#define ASM_H
#ifdef __sgi
#define _MIPS_ISA_MIPS1 1
#define _MIPS_ISA_MIPS2 2
#define _MIPS_ISA_MIPS3 3
#define _MIPS_ISA_MIPS4 4
#endif
#ifndef _LANGUAGE_C
#define LEAF(x) \
.balign 4 ;\
.globl x ;\
.type x, @function ;\
x: ;\
.ent x, 0 ;\
.frame $sp, 0, $ra
#define XLEAF(x) \
.balign 4 ;\
.globl x ;\
.type x, @function ;\
x: ;\
.aent x, 0
#define NESTED(x, fsize, ra) \
.globl x ;\
x: ;\
.ent x, 0 ;\
.frame $sp, fsize, ra
#define XNESTED(x) \
.globl x ;\
x: ;\
.aent x, 0
#define END(x) \
.size x, . - x ;\
.end x
#define IMPORT(x, size) \
.extern x, size
#define EXPORT(x) \
.globl x ;\
x:
#define DATA(x) \
.balign 4 ;\
.globl x ;\
.type x, @object ;\
x:
#define ENDDATA(x) \
.size x, . - x
#endif
/**
* Stack Alignment
*/
#if (_MIPS_SIM == _ABIO32)
#define NARGSAVE 4 // space for 4 args must be allocated
#define ALSZ (8-1)
#define ALMASK ~(8-1)
#elif (_MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64)
#define NARGSAVE 0 // no caller responsibilities
#define ALSZ (16-1)
#define ALMASK ~(16-1)
#endif
#define FRAMESZ(size) (((size) + ALSZ) & ALMASK)
/**
* Register Size
*/
#if (_MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2)
#define SZREG 4
#elif (_MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4)
#define SZREG 8
#endif
#endif

21
include/ultra64/exception.h
View file

@ -1,10 +1,9 @@
#ifndef ULTRA64_EXCEPTION_H
#define ULTRA64_EXCEPTION_H
#include "types.h"
// Interrupt masks
#define OS_IM_NONE 0x00000001
#define OS_IM_RCP 0x00000401
#define OS_IM_SW1 0x00000501
#define OS_IM_SW2 0x00000601
#define OS_IM_CART 0x00000C01
@ -24,6 +23,13 @@
#define RCP_IMASK 0x003F0000
#define RCP_IMASKSHIFT 16
// OSHWIntr values
#define OS_INTR_CART 1
#ifdef _LANGUAGE_C
#include "types.h"
typedef u32 OSIntMask;
typedef u32 OSHWIntr;
@ -42,4 +48,15 @@ void __osResetGlobalIntMask(OSHWIntr mask);
extern __osHwInt __osHwIntTable[];
#else
// __osHwInt struct member offsets
#define HWINT_CALLBACK 0x00
#define HWINT_SP 0x04
// __osHwInt struct size
#define HWINT_SIZE 0x8
#endif
#endif

25
include/ultra64/message.h
View file

@ -1,14 +1,9 @@
#ifndef ULTRA64_MESSAGE_H
#define ULTRA64_MESSAGE_H
#include "thread.h"
#define OS_MESG_NOBLOCK 0
#define OS_MESG_BLOCK 1
typedef void* OSMesg;
typedef u32 OSEvent;
#define OS_NUM_EVENTS 15
#define OS_EVENT_SW1 0 /* CPU SW1 interrupt */
@ -27,6 +22,13 @@ typedef u32 OSEvent;
#define OS_EVENT_THREADSTATUS 13 /* CPU thread status: used by rmon */
#define OS_EVENT_PRENMI 14 /* Pre NMI interrupt */
#ifdef _LANGUAGE_C
#include "thread.h"
typedef void* OSMesg;
typedef u32 OSEvent;
typedef struct OSMesgQueue {
/* 0x00 */ OSThread* mtqueue;
/* 0x04 */ OSThread* fullqueue;
@ -43,4 +45,17 @@ typedef struct OSMesgQueue {
#define MQ_IS_EMPTY(mq) (MQ_GET_COUNT(mq) == 0)
#define MQ_IS_FULL(mq) (MQ_GET_COUNT(mq) >= (mq)->msgCount)
#else
// OSMesgQueue struct member offsets
#define MQ_MTQUEUE 0x00
#define MQ_FULLQUEUE 0x04
#define MQ_VALIDCOUNT 0x08
#define MQ_FIRST 0x0C
#define MQ_MSGCOUNT 0x10
#define MQ_MSG 0x14
#endif
#endif

62
include/ultra64/rcp.h
View file

@ -1,7 +1,9 @@
#ifndef ULTRA64_RCP_H
#define ULTRA64_RCP_H
#ifdef _LANGUAGE_C
#define HW_REG(reg, type) *(volatile type*)((reg) | 0xA0000000)
#endif
#define AI_DRAM_ADDR_REG 0x04500000
#define AI_LEN_REG 0x04500004
@ -20,7 +22,7 @@
#define VI_WIDTH_REG 0x04400008
#define VI_H_WIDTH_REG VI_WIDTH_REG
#define VI_INTR_REG 0x0440000C
#define VI_V_INTER_REG VI_H_WIDTH_REG
#define VI_V_INTER_REG VI_INTR_REG
#define VI_CURRENT_REG 0x04400010
#define VI_V_CURRENT_LINE_REG VI_CURRENT_REG
#define VI_BURST_REG 0x04400014
@ -63,21 +65,24 @@
#define PI_BSD_DOM2_PGS_REG 0x0460002C //PI dom2 page size
#define PI_BSD_DOM2_RLS_REG 0x04600030 //PI dom2 release
#define PI_STATUS_BUSY 0x1
#define PI_STATUS_IOBUSY 0x2
#define PI_STATUS_ERROR 0x4
// PI_STATUS (read) bits
#define PI_STATUS_BUSY (1 << 0)
#define PI_STATUS_IOBUSY (1 << 1)
#define PI_STATUS_ERROR (1 << 2)
#define PI_STATUS_RESET_CONTROLLER 0x1
#define PI_STATUS_CLEAR_INTR 0x2
// PI_STATUS (write) bits
#define PI_STATUS_RESET (1 << 0)
#define PI_STATUS_CLR_INTR (1 << 1)
#define SI_DRAM_ADDR_REG 0x04800000
#define SI_PIF_ADDR_RD64B_REG 0x04800004
#define SI_PIF_ADDR_WR64B_REG 0x04800010
#define SI_STATUS_REG 0x04800018
#define SI_STATUS_DMA_BUSY 0x1
#define SI_STATUS_IO_READ_BUSY 0x2
#define SI_STATUS_DMA_ERROR 0x8
// SI_STATUS (read) bits
#define SI_STATUS_DMA_BUSY (1 << 0)
#define SI_STATUS_IO_READ_BUSY (1 << 1)
#define SI_STATUS_DMA_ERROR (1 << 3)
#define SI_STATUS_INTERRUPT (1 << 12)
#define PIF_RAM_START 0x1FC007C0
@ -88,6 +93,45 @@
#define MI_INTR_REG 0x04300008
#define MI_INTR_MASK_REG 0x0430000C
// MI_INIT_MODE_REG bits (write)
#define MI_CLR_INIT (1 << 7)
#define MI_SET_INIT (1 << 8)
#define MI_CLR_EBUS (1 << 9)
#define MI_SET_EBUS (1 << 10)
#define MI_CLR_DP_INTR (1 << 11)
#define MI_CLR_RDRAM (1 << 12)
#define MI_SET_RDRAM (1 << 13)
// MI_INTR_REG bits
#define MI_INTR_SP (1 << 0)
#define MI_INTR_SI (1 << 1)
#define MI_INTR_AI (1 << 2)
#define MI_INTR_VI (1 << 3)
#define MI_INTR_PI (1 << 4)
#define MI_INTR_DP (1 << 5)
// MI_INTR_MASK_REG masks (read)
#define MI_INTR_MASK_SP 0x01
#define MI_INTR_MASK_SI 0x02
#define MI_INTR_MASK_AI 0x04
#define MI_INTR_MASK_VI 0x08
#define MI_INTR_MASK_PI 0x10
#define MI_INTR_MASK_DP 0x20
// MI_INTR_MASK_REG masks (write)
#define MI_INTR_MASK_CLR_SP 0x0001
#define MI_INTR_MASK_SET_SP 0x0002
#define MI_INTR_MASK_CLR_SI 0x0004
#define MI_INTR_MASK_SET_SI 0x0008
#define MI_INTR_MASK_CLR_AI 0x0010
#define MI_INTR_MASK_SET_AI 0x0020
#define MI_INTR_MASK_CLR_VI 0x0040
#define MI_INTR_MASK_SET_VI 0x0080
#define MI_INTR_MASK_CLR_PI 0x0100
#define MI_INTR_MASK_SET_PI 0x0200
#define MI_INTR_MASK_CLR_DP 0x0400
#define MI_INTR_MASK_SET_DP 0x0800
#define VI_NTSC_CLOCK 48681812 /* Hz = 48.681812 MHz */
#define VI_PAL_CLOCK 49656530 /* Hz = 49.656530 MHz */
#define VI_MPAL_CLOCK 48628316 /* Hz = 48.628316 MHz */

82
include/ultra64/rdb.h Normal file
View file

@ -0,0 +1,82 @@
#ifndef ULTRA64_RDB_H
#define ULTRA64_RDB_H
/* U64 side address */
#define RDB_BASE_REG 0xC0000000
#define RDB_WRITE_INTR_REG (RDB_BASE_REG + 0x8)
#define RDB_READ_INTR_REG (RDB_BASE_REG + 0xC)
#define RDB_BASE_VIRTUAL_ADDR 0x80000000
/* packet type Have six bits, so can have up to 63 types */
#define RDB_TYPE_INVALID 0
#define RDB_TYPE_GtoH_PRINT 1
#define RDB_TYPE_GtoH_FAULT 2
#define RDB_TYPE_GtoH_LOG_CT 3
#define RDB_TYPE_GtoH_LOG 4
#define RDB_TYPE_GtoH_READY_FOR_DATA 5
#define RDB_TYPE_GtoH_DATA_CT 6
#define RDB_TYPE_GtoH_DATA 7
#define RDB_TYPE_GtoH_DEBUG 8
#define RDB_TYPE_GtoH_RAMROM 9
#define RDB_TYPE_GtoH_DEBUG_DONE 10
#define RDB_TYPE_GtoH_DEBUG_READY 11
#define RDB_TYPE_GtoH_KDEBUG 12
#define RDB_TYPE_GtoH_PROF_DATA 22
#define RDB_TYPE_HtoG_LOG_DONE 13
#define RDB_TYPE_HtoG_DEBUG 14
#define RDB_TYPE_HtoG_DEBUG_CT 15
#define RDB_TYPE_HtoG_DATA 16
#define RDB_TYPE_HtoG_DATA_DONE 17
#define RDB_TYPE_HtoG_REQ_RAMROM 18
#define RDB_TYPE_HtoG_FREE_RAMROM 19
#define RDB_TYPE_HtoG_KDEBUG 20
#define RDB_TYPE_HtoG_PROF_SIGNAL 21
#define RDB_PROF_ACK_SIG 1
#define RDB_PROF_FLUSH_SIG 2
#define PROF_BLOCK_SIZE 2048
#define RDB_LOG_MAX_BLOCK_SIZE 0x8000
#define RDB_DATA_MAX_BLOCK_SIZE 0x8000
/* GIO side address */
#define GIO_RDB_BASE_REG 0xBF480000
#define GIO_RDB_WRITE_INTR_REG (GIO_RDB_BASE_REG + 0x8)
#define GIO_RDB_READ_INTR_REG (GIO_RDB_BASE_REG + 0xC)
/* minor device number */
#define GIO_RDB_PRINT_MINOR 1
#define GIO_RDB_DEBUG_MINOR 2
/* interrupt bit */
#define GIO_RDB_WRITE_INTR_BIT 0x80000000
#define GIO_RDB_READ_INTR_BIT 0x40000000
/* debug command */
#define DEBUG_COMMAND_NULL 0
#define DEBUG_COMMAND_MEMORY 1
#define DEBUG_COMMAND_REGISTER 2
#define DEBUG_COMMAND_INVALID 255
/* debug state */
#define DEBUG_STATE_NULL 0
#define DEBUG_STATE_RECEIVE 1
#define DEBUG_STATE_INVALID 255
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
#include "types.h"
/* Structure for debug port */
typedef struct {
u32 type : 6; /* 0: invalid, 1: print, 2: debug */
u32 length : 2; /* 1, 2, or 3 */
char buf[3]; /* character buffer */
} rdbPacket;
#endif
#endif

76
include/ultra64/thread.h
View file

@ -1,8 +1,6 @@
#ifndef ULTRA64_THREAD_H
#define ULTRA64_THREAD_H
#include "types.h"
#define OS_PRIORITY_MAX 255
#define OS_PRIORITY_VIMGR 254
#define OS_PRIORITY_RMON 250
@ -22,6 +20,10 @@
#define OS_FLAG_CPU_BREAK 1
#define OS_FLAG_FAULT 2
#ifdef _LANGUAGE_C
#include "types.h"
typedef s32 OSPri;
typedef s32 OSId;
@ -69,4 +71,74 @@ typedef struct {
OSPri priority;
} __OSThreadTail; // size = 0x8
#else
// OSThread struct member offsets
#define THREAD_NEXT 0x00
#define THREAD_PRI 0x04
#define THREAD_QUEUE 0x08
#define THREAD_TLNEXT 0x0C
#define THREAD_STATE 0x10
#define THREAD_FLAGS 0x12
#define THREAD_ID 0x14
#define THREAD_FP 0x18
#define THREAD_PROFILE 0x1C
#define THREAD_CONTEXT 0x20
#define THREAD_AT (THREAD_CONTEXT + 0x000)
#define THREAD_V0 (THREAD_CONTEXT + 0x008)
#define THREAD_V1 (THREAD_CONTEXT + 0x010)
#define THREAD_A0 (THREAD_CONTEXT + 0x018)
#define THREAD_A1 (THREAD_CONTEXT + 0x020)
#define THREAD_A2 (THREAD_CONTEXT + 0x028)
#define THREAD_A3 (THREAD_CONTEXT + 0x030)
#define THREAD_T0 (THREAD_CONTEXT + 0x038)
#define THREAD_T1 (THREAD_CONTEXT + 0x040)
#define THREAD_T2 (THREAD_CONTEXT + 0x048)
#define THREAD_T3 (THREAD_CONTEXT + 0x050)
#define THREAD_T4 (THREAD_CONTEXT + 0x058)
#define THREAD_T5 (THREAD_CONTEXT + 0x060)
#define THREAD_T6 (THREAD_CONTEXT + 0x068)
#define THREAD_T7 (THREAD_CONTEXT + 0x070)
#define THREAD_S0 (THREAD_CONTEXT + 0x078)
#define THREAD_S1 (THREAD_CONTEXT + 0x080)
#define THREAD_S2 (THREAD_CONTEXT + 0x088)
#define THREAD_S3 (THREAD_CONTEXT + 0x090)
#define THREAD_S4 (THREAD_CONTEXT + 0x098)
#define THREAD_S5 (THREAD_CONTEXT + 0x0A0)
#define THREAD_S6 (THREAD_CONTEXT + 0x0A8)
#define THREAD_S7 (THREAD_CONTEXT + 0x0B0)
#define THREAD_T8 (THREAD_CONTEXT + 0x0B8)
#define THREAD_T9 (THREAD_CONTEXT + 0x0C0)
#define THREAD_GP (THREAD_CONTEXT + 0x0C8)
#define THREAD_SP (THREAD_CONTEXT + 0x0D0)
#define THREAD_S8 (THREAD_CONTEXT + 0x0D8)
#define THREAD_RA (THREAD_CONTEXT + 0x0E0)
#define THREAD_LO (THREAD_CONTEXT + 0x0E8)
#define THREAD_HI (THREAD_CONTEXT + 0x0F0)
#define THREAD_SR (THREAD_CONTEXT + 0x0F8)
#define THREAD_PC (THREAD_CONTEXT + 0x0FC)
#define THREAD_CAUSE (THREAD_CONTEXT + 0x100)
#define THREAD_BADVADDR (THREAD_CONTEXT + 0x104)
#define THREAD_RCP (THREAD_CONTEXT + 0x108)
#define THREAD_FPCSR (THREAD_CONTEXT + 0x10C)
#define THREAD_FP0 (THREAD_CONTEXT + 0x110)
#define THREAD_FP2 (THREAD_CONTEXT + 0x118)
#define THREAD_FP4 (THREAD_CONTEXT + 0x120)
#define THREAD_FP6 (THREAD_CONTEXT + 0x128)
#define THREAD_FP8 (THREAD_CONTEXT + 0x130)
#define THREAD_FP10 (THREAD_CONTEXT + 0x138)
#define THREAD_FP12 (THREAD_CONTEXT + 0x140)
#define THREAD_FP14 (THREAD_CONTEXT + 0x148)
#define THREAD_FP16 (THREAD_CONTEXT + 0x150)
#define THREAD_FP18 (THREAD_CONTEXT + 0x158)
#define THREAD_FP20 (THREAD_CONTEXT + 0x160)
#define THREAD_FP22 (THREAD_CONTEXT + 0x168)
#define THREAD_FP24 (THREAD_CONTEXT + 0x170)
#define THREAD_FP26 (THREAD_CONTEXT + 0x178)
#define THREAD_FP28 (THREAD_CONTEXT + 0x180)
#define THREAD_FP30 (THREAD_CONTEXT + 0x188)
#endif
#endif

2
include/variables.h
View file

@ -10,7 +10,7 @@ extern u32 osTvType;
extern u32 osRomBase;
extern u32 osResetType;
extern u32 osMemSize;
extern u8 osAppNmiBuffer[0x40];
extern u8 osAppNMIBuffer[0x40];
extern u8 D_80009320[];
extern u8 D_800093F0[];

2
include/z64.h
View file

@ -1748,7 +1748,7 @@ typedef struct {
/* 0x04 */ u32 resetCount;
/* 0x08 */ OSTime duration;
/* 0x10 */ OSTime resetTime;
} PreNmiBuff; // size = 0x18 (actually osAppNmiBuffer is 0x40 bytes large but the rest is unused)
} PreNmiBuff; // size = 0x18 (actually osAppNMIBuffer is 0x40 bytes large but the rest is unused)
typedef struct {
/* 0x00 */ s16 unk_00;

4
spec
View file

@ -38,6 +38,7 @@ beginseg
include "build/src/libultra/os/dequeuethread.o"
include "build/src/libultra/os/destroythread.o"
include "build/asm/bzero.o"
include "build/asm/parameters.o"
include "build/src/libultra/os/createthread.o"
include "build/asm/__osSetSR.o"
include "build/asm/__osGetSR.o"
@ -77,8 +78,7 @@ beginseg
include "build/asm/__osSetCompare.o"
include "build/asm/bcopy.o"
include "build/src/libultra/os/resetglobalintmask.o"
include "build/asm/__osDisableInt.o"
include "build/asm/__osRestoreInt.o"
include "build/asm/interrupt.o"
include "build/src/libultra/io/vimodentsclan1.o"
include "build/src/libultra/io/vimodempallan1.o"
include "build/src/libultra/io/vi.o"

3
src/boot/boot_main.c
View file

@ -1,10 +1,11 @@
#include "global.h"
#include "boot.h"
StackEntry sBootThreadInfo;
OSThread sIdleThread;
STACK(sIdleThreadStack, 0x400);
StackEntry sIdleThreadInfo;
STACK(sBootThreadStack, 0x400);
STACK(sBootThreadStack, BOOT_STACK_SIZE);
void cleararena(void) {
bzero(_dmadataSegmentStart, osMemSize - OS_K0_TO_PHYSICAL(_dmadataSegmentStart));

2
src/code/main.c
View file

@ -46,7 +46,7 @@ void Main(void* arg) {
osSyncPrintf("mainproc 実行開始\n"); // "Start running"
gScreenWidth = SCREEN_WIDTH;
gScreenHeight = SCREEN_HEIGHT;
gAppNmiBufferPtr = (PreNmiBuff*)osAppNmiBuffer;
gAppNmiBufferPtr = (PreNmiBuff*)osAppNMIBuffer;
PreNmiBuff_Init(gAppNmiBufferPtr);
Fault_Init();
SysCfb_Init(0);

5
src/libultra/io/cartrominit.c
View file

@ -27,8 +27,9 @@ OSPiHandle* osCartRomInit(void) {
__CartRomHandle.speed = 0;
bzero(&__CartRomHandle.transferInfo, sizeof(__OSTranxInfo));
while (status = HW_REG(PI_STATUS_REG, u32), status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {
;
status = HW_REG(PI_STATUS_REG, u32);
while (status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {
status = HW_REG(PI_STATUS_REG, u32);
}
lastLatency = HW_REG(PI_BSD_DOM1_LAT_REG, u32);

6
src/libultra/io/devmgr.c
View file

@ -28,7 +28,7 @@ void __osDevMgrMain(void* arg) {
phi_s2 = ((transfer->transferMode == 2) && (ioMesg->piHandle->transferInfo.cmdType == 0)) ? 1 : 0;
osRecvMesg(arg0->acccessQueue, &sp6C, OS_MESG_BLOCK);
__osResetGlobalIntMask(0x00100401);
__osResetGlobalIntMask(OS_IM_PI);
__osEPiRawWriteIo(ioMesg->piHandle, 0x05000510, transfer->bmCtlShadow | 0x80000000);
while (true) {
@ -43,8 +43,8 @@ void __osDevMgrMain(void* arg) {
__osEPiRawWriteIo(ioMesg->piHandle, 0x05000510, transfer->bmCtlShadow | 0x1000000);
}
block->errStatus = 4;
HW_REG(PI_STATUS_REG, u32) = PI_STATUS_CLEAR_INTR;
__osSetGlobalIntMask(0x00100C01);
HW_REG(PI_STATUS_REG, u32) = PI_STATUS_CLR_INTR;
__osSetGlobalIntMask(OS_IM_CART | OS_IM_PI);
}
osSendMesg(ioMesg->hdr.retQueue, (OSMesg)ioMesg, OS_MESG_NOBLOCK);

5
src/libultra/io/driverominit.c
View file

@ -22,8 +22,9 @@ OSPiHandle* osDriveRomInit(void) {
__DriveRomHandle.speed = 0;
bzero(&__DriveRomHandle.transferInfo, sizeof(__OSTranxInfo));
while (status = HW_REG(PI_STATUS_REG, u32), status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {
;
status = HW_REG(PI_STATUS_REG, u32);
while (status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {
status = HW_REG(PI_STATUS_REG, u32);
}
HW_REG(PI_BSD_DOM1_LAT_REG, u32) = 0xFF;

5
src/libultra/io/epirawdma.c
View file

@ -4,8 +4,9 @@ s32 __osEPiRawStartDma(OSPiHandle* handle, s32 direction, u32 cartAddr, void* dr
s32 status;
OSPiHandle* curHandle;
while (status = HW_REG(PI_STATUS_REG, u32), status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {
;
status = HW_REG(PI_STATUS_REG, u32);
while (status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {
status = HW_REG(PI_STATUS_REG, u32);
}
if (__osCurrentHandle[handle->domain]->type != handle->type) {

5
src/libultra/io/epirawread.c
View file

@ -4,8 +4,9 @@ s32 __osEPiRawReadIo(OSPiHandle* handle, u32 devAddr, u32* data) {
s32 status;
OSPiHandle* curHandle;
while (status = HW_REG(PI_STATUS_REG, u32), status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {
;
status = HW_REG(PI_STATUS_REG, u32);
while (status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {
status = HW_REG(PI_STATUS_REG, u32);
}
if (__osCurrentHandle[handle->domain]->type != handle->type) {

5
src/libultra/io/epirawwrite.c
View file

@ -4,8 +4,9 @@ s32 __osEPiRawWriteIo(OSPiHandle* handle, u32 devAddr, u32 data) {
s32 status;
OSPiHandle* curHandle;
while (status = HW_REG(PI_STATUS_REG, u32), status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {
;
status = HW_REG(PI_STATUS_REG, u32);
while (status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {
status = HW_REG(PI_STATUS_REG, u32);
}
if (__osCurrentHandle[handle->domain]->type != handle->type) {

3
src/libultra/io/pirawdma.c
View file

@ -1,8 +1,9 @@
#include "global.h"
s32 __osPiRawStartDma(s32 dir, u32 cartAddr, void* dramAddr, size_t size) {
register s32 status = HW_REG(PI_STATUS_REG, u32);
s32 status;
status = HW_REG(PI_STATUS_REG, u32);
while (status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {
status = HW_REG(PI_STATUS_REG, u32);
}

3
src/libultra/os/createthread.c
View file

@ -1,4 +1,5 @@
#include "global.h"
#include "ultra64/asm.h"
__OSThreadTail __osThreadTail = { NULL, OS_PRIORITY_THREADTAIL };
OSThread* __osRunQueue = (OSThread*)&__osThreadTail;
@ -16,7 +17,7 @@ void osCreateThread(OSThread* thread, OSId id, void (*entry)(void*), void* arg,
thread->queue = NULL;
thread->context.pc = (u32)entry;
thread->context.a0 = arg;
thread->context.sp = (u64)(s32)sp - 16;
thread->context.sp = (u64)(s32)sp - FRAMESZ(SZREG * NARGSAVE);
thread->context.ra = __osCleanupThread;
mask = OS_IM_ALL;

4
src/libultra/os/initialize.c
View file

@ -7,6 +7,8 @@ typedef struct {
u32 ins_0C; // nop
} struct_exceptionPreamble;
void __osExceptionPreamble(void);
u64 osClockRate = OS_CLOCK_RATE;
s32 osViClock = VI_NTSC_CLOCK;
u32 __osShutdown = 0;
@ -58,7 +60,7 @@ void __osInitialize_common(void) {
osClockRate = (u64)((osClockRate * 3ll) / 4ull);
if (!osResetType) {
bzero(osAppNmiBuffer, sizeof(osAppNmiBuffer));
bzero(osAppNMIBuffer, sizeof(osAppNMIBuffer));
}
if (osTvType == OS_TV_PAL) {

2
src/libultra/os/resetglobalintmask.c
View file

@ -3,6 +3,6 @@
void __osResetGlobalIntMask(OSHWIntr mask) {
register u32 prevInt = __osDisableInt();
__OSGlobalIntMask &= ~(mask & ~0x401);
__OSGlobalIntMask &= ~(mask & ~OS_IM_RCP);
__osRestoreInt(prevInt);
}

52
undefined_syms.txt
View file

@ -1,55 +1,3 @@
// libultra OS symbols
osTvType = 0x80000300;
osRomBase = 0x80000308;
osResetType = 0x8000030C;
osMemSize = 0x80000318;
osAppNmiBuffer = 0x8000031C;
// OS hardware registers
D_A4040004 = 0xA4040004;
D_A4040008 = 0xA4040008;
D_A404000C = 0xA404000C;
D_A4040010 = 0xA4040010;
D_A4300008 = 0xA4300008;
D_A430000C = 0xA430000C;
D_A4400004 = 0xA4400004;
D_A4400008 = 0xA4400008;
D_A440000C = 0xA440000C;
D_A4400010 = 0xA4400010;
D_A4400014 = 0xA4400014;
D_A4400018 = 0xA4400018;
D_A440001C = 0xA440001C;
D_A4400020 = 0xA4400020;
D_A4400024 = 0xA4400024;
D_A4400028 = 0xA4400028;
D_A440002C = 0xA440002C;
D_A4400030 = 0xA4400030;
D_A4400034 = 0xA4400034;
D_A4500004 = 0xA4500004;
D_A4500008 = 0xA4500008;
D_A450000C = 0xA450000C;
D_A4500010 = 0xA4500010;
D_A4500014 = 0xA4500014;
D_A4600004 = 0xA4600004;
D_A4600005 = 0xA4600005;
D_A4600006 = 0xA4600006;
D_A4600007 = 0xA4600007;
D_A4600008 = 0xA4600008;
D_A460000C = 0xA460000C;
D_A4600010 = 0xA4600010;
D_A4600014 = 0xA4600014;
D_A4600018 = 0xA4600018;
D_A460001C = 0xA460001C;
D_A4600020 = 0xA4600020;
D_A4600024 = 0xA4600024;
D_A4600028 = 0xA4600028;
D_A460002C = 0xA460002C;
D_A4600030 = 0xA4600030;
D_A4800000 = 0xA4800000; // SI_DRAM_ADDR_REG
D_A4800004 = 0xA4800004; // SI_PIF_ADDR_RD64B_REG
D_A4800010 = 0xA4800010; // SI_PIF_ADDR_WR64B_REG
D_A4800018 = 0xA4800018; // SI_STATUS_REG
// z_kankyo, z_demo_kankyo, z_en_viewer, z_object_kankyo, z_eff_ss_dead_dd
D_01000000 = 0x01000000;