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Author SHA1 Message Date
Veselin Georgiev
decba3e728 Simplify Bulldozer detection; differentiate Bulldozer<->Vishera. 
Also add two tests:
- AMD FX-8150 - which is decoded as 'Bulldozer X4'
- AMD FX-9590 - which is decoted as 'Vishera X4'
 2014-07-23 22:13:37 +03:00
Veselin Georgiev
5052ad4d1f Fixed a detection for Turion Griffin - it's ext_family is not 23, it's 17. 
Also, the sse-width guesswork seems to handle this (wrong) Griffin ext_family
explicitly, so fix it there as well.

Seems that members of ext_family 20 (AMD Fusion based APUs) also are 64-bit,
but they have the authoritative sse width detection bit, so we don't need
to handle them explicitly here.
 2014-07-23 22:06:11 +03:00
Veselin Georgiev
f5ab18506f Fix CPU speed detection for Bulldozer and related cores. 
It seems that our SSE-based speed test is 1 IPC (instructions per clock)
on all current CPUs, and 1.4 IPC on the Bulldozer, which leads to its
result being 40% too high. Correct that in the function.
 2014-07-23 21:29:34 +03:00
Veselin Georgiev
f883e2b592 Add recognition support for Haswell i3, i5 and i7. 
Add a test based on a Haswell i3 (Core i3-4130).
 2014-07-18 21:00:48 +03:00
Veselin Georgiev
551aff201b When creating a tarball, include the small tests now instead of tests_stash.txt 2014-07-16 10:29:58 +03:00
Veselin Georgiev
5661455ad2 Add the m4/ dir to ignore. 2014-07-16 10:29:46 +03:00
Veselin Georgiev
989ea9f586 Delete unused old test data/utils. 2014-07-16 10:11:28 +03:00
Veselin Georgiev
f6acf1b634 Refactor "make test" as well. 2014-07-16 10:10:51 +03:00
Veselin Georgiev
019170b65f Refactor the tests: put each test case in a separate file 
Instead of one big pile of tests in tests_stash.txt, keep each CPU
example raw data/parsed data in a file, ordered in a tree by
manufacturer and microarchitecture. The 64 .test files have been
extracted from tests_stash.txt. The add_test script is changed to
create_test and it doesn't append to test_stash.txt, instead it
spits out data to be saved in a .test file.

run_tests.py is not refactored yet, to be done in a subsequent commit.
 2014-07-15 19:59:35 +03:00
Veselin Georgiev
3c9aa04f13 Rename: add_test.py -> create_test.py 2014-07-15 17:56:16 +03:00
Veselin Georgiev
fbed394404 Change add_test.py to output the concatenated raw/report to stdout. 
Instead of appending it to test_stash.
 2014-07-15 17:55:39 +03:00
Veselin Georgiev
0f17a01e9c Add .gitignore. 2014-07-14 17:58:11 +03:00
Veselin Georgiev
f750dde2c0 Fixed issue #4: Advanced Power Management Features 
- Move detection of constant_tsc to common; it is spec'd in Intel docs
- Fix broken interpretation of EAX in leaf 80000000h: it shows max
  800000xx-value, not max xx-value. This causes, for example, to seek
  for extended features on Pentium II, where the extended leafs aren't
  supported by the CPU at all.
  This is only in common feature detection. AMD detection is fine.
- Add detection of a few new features in AMD leaf 80000007h: cbp (core
  performance boost), aperfmperf (APERF/MPERF MSRs supported),
  pfi (processor feedback interface) and pa (processor accumulator).

"make test" is broken right now, to be fixed in a subsequent commit.
 2014-06-30 03:07:33 +03:00
Veselin Georgiev
798bcc80b2 Remove a space, which causes "make consistency" to frown. 2014-06-30 02:36:33 +03:00
Veselin Georgiev
2914256486 Update ChangeLog; bump the version to 0.2.1 everywhere. 
Previously, 0.2.1 was mentioned in libcpuid.h, but this was not,
actually, in effect; it wasn't mentioned in autoconf and Visual Studio
project files. Also, cpuid_lib_version() still returned "0.2.0".
 2014-06-25 14:15:53 +03:00
Veselin Georgiev
23c629295a Add *.sln, *.vcproj files to automake for "make dist" to work. 
The .am files contained obsolete data (to include libcpuid.sln/libcpuid.vcproj
in a dist). These files are now in libcpuid_vc71.* and libcpuid_vc9.* flavours,
thus this change. "make dist" now works.
 2014-06-25 13:54:41 +03:00
Veselin Georgiev
c5b459c5b2 Fix issue #2: There is no configure binary and get some statements while building it. 
There's no reason to keep a configure binary in source control. I added the
necessary steps to create it in the README.
 2014-06-25 13:48:32 +03:00
Veselin Georgiev
20632054d6 Add support for Atom Pineview. 2014-06-23 23:41:02 +03:00
Veselin Georgiev
45651ef7bc Merge 141243f from http://github.com/eloaders/libcpuid 
This adds support for x2apic detection. This is not a direct merge, since

- the feature is spelled as 'x2apic' instead of 'x2APIC', for consistency with other flags;
- tests are added
- the id of the feature is moved to the end of the cpu_feature_t enum, for binary
  compatibility.
 2014-06-22 21:00:18 +03:00
Veselin Georgiev
0f90f77910 Fixed a crash with gcc-4.6.3 in 32-bit mode. The compiler aggressively optimizes exec_cpuid(), making the stack layout not exactly what the assembly expects. Rearranging instructions seems to fix things. The 64-bit changes aren't tested, though. 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@110 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2013-01-18 22:32:44 +00:00
Veselin Georgiev
b175d4d6df VS 2002 also doesn't support long long natively (thanks to Andras Kenez for the pointer) 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@109 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2012-09-19 16:53:09 +00:00
Veselin Georgiev
18d2b9b075 Updated checking scripts 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@108 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2012-09-09 22:29:12 +00:00
Veselin Georgiev
f385bac458 Added support for Intel Atom Cedarview 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@107 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2012-09-09 22:28:55 +00:00
Veselin Georgiev
b65ac8c8e6 Changed code generation to Multithreaded DLL 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@106 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2012-08-26 20:29:44 +00:00
Veselin Georgiev
767c09c57b Ported to Microsoft Visual C 6.0 
It requires MSVC 6.0 with SP5 and Processor Pack 5 installed (for SSE instruction support).

git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@105 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2012-08-25 23:14:59 +00:00
Veselin Georgiev
1344ec1a81 Added support for detecting the following processors: The newer 6 and 8-core Sandy Bridges (termed Sandy Bridge-E), Ivy Bridge, AMD Magny-Cours. Added support for detecting the rdrand instruction. Added tests. 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@104 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2012-05-26 13:00:04 +00:00
Veselin Georgiev
61cd70d90a Proper detection for the Bulldozer. It reports itself as having 8 cores. 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@103 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-10-14 09:49:52 +00:00
Veselin Georgiev
23dac9da66 Version of the Windows build upped to 0.2.0 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@102 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-10-14 03:02:50 +00:00
Veselin Georgiev
9fafda1bed Added support for Sandy-bridge based celerons 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@101 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-10-13 22:46:42 +00:00
Veselin Georgiev
8413e8969a Fixed bogus llano detection, added detection for Bulldozer. Not tested, since I don't have an engineering sample:) 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@100 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-10-11 17:39:29 +00:00
Veselin Georgiev
62605fffd8 Added a test with a Zacate CPU. Also, fixed the add_test script 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@99 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-10-11 17:33:30 +00:00
Veselin Georgiev
42fc8b4654 Modified the test-stash and the testing code, so that it is aware of the SSE unit size functionality. Also, added support for detecting AMD Llano/Brazos CPUs 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@98 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-10-11 17:26:00 +00:00
Veselin Georgiev
fead3f21e3 Use -sse-size instead of --sse_size, to be consistent 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@97 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-10-11 16:59:26 +00:00
Veselin Georgiev
3623c5639d Added SSE unit size detection, based on the AMD extended leaf 1a, bit 0. Added a field in cpu_id_t to specify SSE unit size. Also added a hints array, similar to the flags array, which will hold various detection-specific hints. The only currently present hint is about the way the SSE unit size is inferred - whether it is based on the old CPU family/model guesswork (which fails for the AMD Brazos-based cores). Also, added the features XOP, FMA4, TBM and F16C. Changed the library version due to breaking binary compatibility. 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@96 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-10-11 16:38:41 +00:00
Veselin Georgiev
2f949b18d9 Support for 2MB L2 Cache Yorkfield added. Also, made the logic a bit more foolproof by adding explicit core count for those Yorkfields. 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@95 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-01-16 01:11:00 +00:00
Veselin Georgiev
c3d236ec86 Bumped the version to 0.1.4 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@94 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-01-14 05:28:31 +00:00
Veselin Georgiev
49c474f74d Support for Sandy Bridge (Core i7) processors 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@93 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-01-13 18:01:51 +00:00
Veselin Georgiev
166445dbd0 Added Celeron Wolfdale (45nm-based 1MB cache C2D CPU) 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@92 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-01-13 13:34:13 +00:00
Veselin Georgiev
27e7508e7d Support for Arrandale i7s 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@91 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-01-13 13:12:21 +00:00
Veselin Georgiev
f398770f79 Implemented busy_sse_loop for win32. Need to do for x64 though. 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@90 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-01-10 13:37:51 +00:00
Veselin Georgiev
f1c250d6cf Support for Lynnfield i7s, and better detection of Athlon Propus. Also, added newer Athlon II X3s (Rana) 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@89 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-10-15 08:37:54 +00:00
Veselin Georgiev
6a7854f3b4 Support for Gulftown (westmere-based) Intels, and for AMD X6 (Thuban). Also differentiated the Thuban-derived X4s (Zosma) which I suppose also have ext model 10, but this needs to be verified. 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@88 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-10-13 11:59:46 +00:00
Veselin Georgiev
d520a37569 Support for Core i5/i3. The matchtables now have a column for L3 cache 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@87 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-10-13 09:18:07 +00:00
Veselin Georgiev
e28b38aa1e The previous fix was bogus on the i7, so now it is fixed to what the previous value was 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@86 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-04-20 10:22:10 +00:00
Veselin Georgiev
75934f2538 An erorrneous commit was reverted 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@85 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-04-20 10:18:53 +00:00
Veselin Georgiev
23b5b71856 Another minor fix 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@84 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-04-20 10:17:21 +00:00
Veselin Georgiev
a7a45d8efb A small correction 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@83 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-04-20 10:03:03 +00:00
Veselin Georgiev
b922a5b29c A small correction to account for the non-loop instructions in busy_sse_loop() 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@82 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-04-20 09:59:12 +00:00
Veselin Georgiev
4802081283 Apple's GCC wasn't very happy with "eax" in the assembly block operands. However, changing to "a" fixes it 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@81 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-04-20 09:52:24 +00:00
Veselin Georgiev
75c7ba17d5 Preliminary code to detect SSE width for proper clock detection with cpu_clock_by_ic() 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@80 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-04-20 09:43:17 +00:00