Improved parsing of brand strings for both Pineview and Cedarview
Atoms.
Add tests for both the Pineview Atom, and also Broadwell-E
(forgotten in a previous commit).
The presence of RTM was previously incorrectly attributed to a Skylake
or later only CPUs. Broadwells have this as well, so the detected
intel_code_t for Broadwell-E was wrong (it was CORE_HASWELL*).
The new project files are for Microsoft Visual Studio 2010.
The configurations now support building both 32- and 64-bit targets,
and the "Release DLL" target is supported much like in the vc71 project.
The output layout is as follows:
32-bit, Debug static library goes to libcpuid/x32/Debug
32-bit, Release static library goes to libcpuid/x32/Release
32-bit, DLL (only release) goes to libcpuid/x32/ReleaseDLL. It includes
the .dll and the export library .lib as well.
64-bit DLL goes to libcpuid/x64/ReleaseDLL.
and so forth.
The test is a snapshot of a Haswell i7 (a.k.a. "Crystalwell") core.
This is the only test in the test DB right now which has lines for
L4 cache size, associativity and cacheline size different than "-1".
Also update create_test.py to accommodate for the new fields.
It returns 0x7FFFFFFF instead of 0x3FFFFFFF
0x3FFFFFFF is a 29-bit value, but become a 36-bit value when multiplied by 100, causing a value out-of-range
recog_intel.c:589:22: warning: implicit conversion from enumeration type 'enum _common_codes_t' to different enumeration type 'intel_code_t' (aka 'enum _intel_code_t')
recog_amd.c:449:9: warning: implicit conversion from enumeration type 'enum _common_codes_t' to different enumeration type 'amd_code_t' (aka 'enum _amd_code_t')
* Add AMD and Intel doc links
* Use 'return' only if there is no error; on error, the end-function 'return CPU_INVALID_VALUE' is used
* Add more comments about MSRs
* Simplify a lot of things
* Avoid cpu_rdmsr_range() to override cpu_rdmsr() error
* Remove int casting in cpu_msrinfo()
This is a backwards-incompatible binary change, which increases
sizeof(cpu_raw_data_t). Specifically, the cpu_raw_data_t::intel_fn4
array is increased from 4 to 8 elements, because on recent Hasells
(Crystalwell) there is a Level 4 cache, which should be encoded in
CPUID eax=4 ecx=4. However, we were only storing levels for eax=4
for ecx <= 3. Thus the raw data didn't have the relevant info.
There will be further changes to this, specifically to store
and print the level 4 cache in cpuid_tool.
