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Author SHA1 Message Date
Veselin Georgiev
8db3b8d2d3
Merge pull request #142 from ClickHouse-Extras/fix-tsan 
Fix TSan report
 2020-05-11 09:10:48 +03:00
alexey-milovidov
a9fe7b6aca
Update cpuid_main.c 2020-05-11 00:26:23 +03:00
Xorg
ef8986407f DB: add Ivy Bridge-E (Xeon) 2020-05-10 17:02:45 +00:00
Xorg
fb1deb1fef Tests: update all tests to add fields for L1I 2020-05-10 17:02:45 +00:00
Xorg
e592a83278 Tests: update to add L1I information 
Related to 25d0614811
Dump of Core i5 520m from CPU-X#119
 2020-05-10 17:02:45 +00:00
Xorg
25d0614811
Add L1 Instruction Cache information 
Some CPUs does not have the same associativity for L1D and L1I, as reported in X0rg/CPU-X#119
It adds l1_instruction_assoc and l1_instruction_cacheline in cpu_id_t
To avoid confusing, also adds l1_data_assoc and l1_data_cacheline
l1_assoc and l1_cacheline are leave untouched for backward compatibility
 2020-05-10 11:49:02 +02:00
Xorg
21e4b1f48e
Ignore .vscode directory 
Yes, 0b05f45e03 was about VS Code
 2020-05-09 22:50:16 +02:00
Xorg
6b5a1f5ea6
Tests: add amd_fn8000001dh subleaf 
See e562798cec
 2020-05-09 22:48:07 +02:00
Xorg
3a346d4d72
Tests: parse subleafs in convert_instlatx64 
Also, it adds 0xffffffff when data is not available, so all lines are presents
 2020-05-09 22:46:13 +02:00
Xorg
e562798cec
Re-fix L3 cache associativity detection on AMD Zen 2 CPUs 
Previous commit: 848394ee46
 2020-05-09 22:39:42 +02:00
Alexey Milovidov
6f8449d88e Applied a patch from @tavplubix 2020-05-09 21:07:16 +03:00
Xorg
b23145144f
Use constant for registers name 
It helps when reading technical documentation and it avoids 'magic values'
 2020-05-09 18:17:50 +02:00
Xorg
0b05f45e03
Remove all trailling spaces 
It is annoying with some text editors
 2020-05-09 17:34:07 +02:00
Xorg
d317e1504f
DB: fix Rome extended model 2020-05-09 15:59:28 +02:00
Xorg
c854176478
DB: add Renoir APUs 2020-05-09 15:57:56 +02:00
Xorg
8720a71b35
Tests: add Core i5 8250U 
Related to X0rg/CPU-X#129
 2020-05-09 14:46:59 +02:00
Xorg
edee5aba6f
DB: add Ice Lake CPUs 2020-05-09 14:46:48 +02:00
Xorg
b0f615527f
DB: add Comet Lake CPUs 2020-05-09 14:32:56 +02:00
Xorg
20100f3faf
DB: add Coffee Lake Refresh 
It differs from Coffee Lake by stepping
Core i5 9400 and 9500 will still be detected as Coffee Lake because it only differs by revision...
 2020-05-09 14:08:12 +02:00
Xorg
eda4204787
DB: add Coffee Lake-U 
It differs from Kaby Lake-U by stepping
 2020-05-09 13:46:50 +02:00
Xorg
faf958c3c9
DB: add Cannon Lake CPUs 2020-05-09 13:28:11 +02:00
Xorg
af5019acec
DB: clarify Intel Generations 2020-05-09 13:02:26 +02:00
Veselin Georgiev
9d22c61611
Merge pull request #141 from X0rg/master 
Fixes for AMD Zen 2 CPUs
 2020-05-04 21:35:42 +03:00
Xorg
46e86331bb
tests: remove duplicate addresses in RAW part 2020-05-03 17:12:33 +02:00
Xorg
afbd7ae56d
tests: fix convert_instlatx64 tool 2020-05-03 17:09:54 +02:00
Xorg
848394ee46
Fix L3 cache associativity detection on AMD Zen 2 CPUs 2020-05-03 17:07:43 +02:00
Veselin Georgiev
f2ab8b7ef2
Merge pull request #139 from kreuzerkrieg/Fix_Win_x64_Build 
Fix Win64 build
 2020-02-12 00:11:27 +02:00
kreuzerkrieg
f729a74b41 Fix CMake 2020-02-11 12:29:31 +02:00
Veselin Georgiev
5f6a9bf5b0
Merge pull request #138 from kreuzerkrieg/AddCMake 
Add CMake support
 2020-02-06 11:22:54 +02:00
kreuzerkrieg
9eacb1a36e Add CMake 2020-02-06 11:12:29 +02:00
kreuzerkrieg
12de298ff7 Add CMake 2020-02-06 10:32:25 +02:00
Veselin Georgiev
7b360635aa
Merge pull request #137 from eloaders/master 
DB: Add Threadripper (Castle Peak)
 2020-01-02 21:12:19 +02:00
eloaders
5f7f3c26cc DB: Add Threadripper (Castle Peak) 2019-12-31 10:58:20 +01:00
Veselin Georgiev
a7d14afb61
Merge pull request #132 from enzo1982/arch 
Fix compilation on non-x86/ARM architectures.
 2019-10-29 22:07:32 +02:00
Veselin Georgiev
37fabe8dd8
Merge pull request #131 from enzo1982/haiku 
Add support for get_total_cpus on Haiku.
 2019-10-29 22:06:30 +02:00
Robert Kausch
67d18833c4 Fix compilation on non-x86/ARM architectures. 2019-10-29 20:49:08 +01:00
Robert Kausch
2159f73eaa Add support for get_total_cpus on Haiku. 2019-10-29 20:38:55 +01:00
Veselin Georgiev
69ed754010
Merge pull request #130 from sunweaver/pr/some-typo-fixes 
Some typo fixes in human readable text.
 2019-10-01 18:06:45 +03:00
Mike Gabriel
47418f1e71 Some typo fixes in human readable text. 2019-10-01 13:04:01 +02:00
Veselin Georgiev
f6e4e23796 Add Xeon CLX (Cascade lake-based) using data from PR #129 
Kudos to Leslie-Fang for providing it!
 2019-08-09 11:18:20 +03:00
Veselin Georgiev
c4c86835a0
Merge pull request #129 from Leslie-Fang/master 
add support to feature intel avx512_vnni
 2019-08-09 11:12:03 +03:00
Leslie-Fang
8f91df526d add support to feature intel avx512_vnni 2019-08-08 22:06:23 +08:00
Veselin Georgiev
88d98cedd3
Merge pull request #127 from fastogt/master 
AARCH64 stub
 2019-07-14 21:38:31 +03:00
topilski
b2e5b6ae2e AARCH64 stub 2019-07-13 21:10:34 +03:00
Veselin Georgiev
96810180a0
Merge pull request #126 from X0rg/master 
Fix for Zen 2
 2019-07-12 11:20:06 +03:00
Xorg
eeec951534 Ignore convert_instlatx64 binary 2019-07-11 22:49:29 +02:00
Xorg
848354a3f1 Tests: Add more Matisse CPUs 2019-07-11 22:49:08 +02:00
Xorg
bf7f57f519 Fix SSE unit size for Zen 2 CPUs 
Related to #125
 2019-07-11 22:29:27 +02:00
Veselin Georgiev
ab3bc3defe
Merge pull request #125 from X0rg/master 
More test files for AMD Zen CPUs
 2019-07-11 08:34:24 +03:00
Xorg
5aedd53624 Add more test files for AMD Zen CPUs 
Dumps found on http://instlatx64.atw.hu/
 2019-07-07 20:03:45 +02:00