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Author SHA1 Message Date
Veselin Georgiev
db6f3abc9a Merge pull request #34 from wdlkmpx/master 
Fix issue with HyperThreading status in old cpus
 2016-04-25 01:51:24 +03:00
Veselin Georgiev
b1fb7f0d85 Merge pull request #33 from x64architecture/master 
Fix AMD Feature Detection And Associativity Table
 2016-04-25 01:46:29 +03:00
wdlkmpx
f26c1151f0 Fix issue with HyperThreading status in old cpus 
Early P4 processors come with the HT flag, but that feature
is not enabled.

This makes it work the way it should.
 2016-04-24 17:28:16 +00:00
wdlkmpx
fa9640b3a2 tests: add p4 celeron willamette-128 
1.8GHz
Specs:
http://www.cpu-world.com/CPUs/Celeron/Intel-Celeron%201800%20-%20RK80531RC033128%20(BX80531P180G128).html
 2016-04-24 17:26:44 +00:00
wdlkmpx
75c3c36cbb tests: add intel p4 prescott with HT enabled 
This is from a Pentium 4 Prescott 3.20GHz processor
Specs:
http://www.cpu-world.com/CPUs/Pentium_4/Intel-Pentium%204%203.2%20GHz%20-%20RK80546PG0881M%20(BX80546PG3200E).html
 2016-04-24 17:26:03 +00:00
Kurt Cancemi
dea8a6006a Fix tests 2016-04-24 00:27:42 -04:00
Kurt Cancemi
5ca7b2deee AMD associativity table Dh should contain 96 not 92 2016-04-24 00:26:00 -04:00
Kurt Cancemi
6ea1d4c8e2 Fix PCLMULQDQ, SSE4.1, MOVBE and RDRAND detection on AMD processors 2016-04-24 00:24:31 -04:00
wdlkmpx
eb6f1a2b9a More precise descriptions for some old processors 
PII Celeron:
Model 5 = Celeron Covington = PII Deschutes
Model 6 = Celeron Mendocino = PII Dixon

PII Xeon:
Model 3 = Xeon ???? = PII Xeon (Klamath)
Model 5 = Xeon Drake = PII Deschutes
Model 6 = Xeon ???? = PII Xeon (Dixon)

PIII Celeron:
PIII Celeron (XX) = PIII (XX)

PIII Xeon:
Model 7 = Xeon Tanner = PIII Katmai
Model 8,10 = Xeon Cascades = PIII Coppermine
Model 11 = Xeon ??? = PIII Xeon (Tualatin)

Signed-off-by: Veselin Georgiev <anrieff@gmail.com>
 2016-04-20 01:36:58 +03:00
Veselin Georgiev
b8fe2a57cf Update Readme.md with details about testing. 2016-04-19 13:38:41 +03:00
Veselin Georgiev
d46ca6eacd Merge pull request #30 from wdlkmpx/master 
Pentium D: more precise descriptions
 2016-04-19 13:20:02 +03:00
wdlkmpx
5f420362c6 P4 Celeron: more precise descriptions 
According to wikipedia, cpu-world and some cpu-z screenshots, these processors
do have a code name and it's willamette, northwood, prescott or cedar mill

Signed-off-by: Veselin Georgiev <anrieff@gmail.com>
 2016-04-19 00:57:11 +03:00
wdlkmpx
0dc6edf925 Pentium D: more precise descriptions 
Basically:
Model = 4 -> Smithfield
Model = 6 -> Presler

Download this 16 cpu-z screenshots to verify (1.5mb):
http://s000.tinyupload.com/index.php?file_id=54246820652929080678
 2016-04-18 19:29:09 +00:00
Veselin Georgiev
13f382725b Fix 'make test' failing without any really wrong tests. 
The reason was that the invocation of the cpuid_tool through the makefile
was using LD_LIBRARY_PATH=. to force link&use of the latest-build libcpuid
library. This doesn't seem to work, so using LD_PRELOAD to explicitly load
libcpuid.so into cpuid_tool.

The committed approach of course doesn't work on Mac OS X, where
make test-old should be used.
 2016-03-10 02:44:17 +02:00
Veselin Georgiev
281d4720d4 Fix issue #28: Windows Build error 
msrdriver.c was forgotten from Makefile.am, under the assumption that
autotools are used under *nix only. This is not true, as one could use
MinGW or cygwin.
 2016-03-10 01:14:37 +02:00
Veselin Georgiev
d954213667 Speed up "make test" (around 5 times). 
The reason for the apparent slowness was that the "cpuid_tool" that
was being called from run_tests.py is actually a shell script - a
wrapper, installed by libtool. The script was heavy enough to cause
substantial overhead. Just bypassing it (by using the real
cpuid_tool binary) reduced "make test" running time from 4.1 to 0.7s
on my machine.

It is a bit hacky, though, so "make test-old" is retained, which
uses the old invocation.
 2016-01-17 03:49:05 +02:00
Veselin Georgiev
76f461de59 Fix "make test" when the builddir != srcdir. 2016-01-17 03:37:23 +02:00
Veselin Georgiev
870c4b72ae Merge pull request #27 from x64architecture/master 
Fix X2APIC, AES, XSAVE and OSXSAVE feature detection on AMD processors
 2016-01-17 03:04:05 +02:00
Kurt Cancemi
c5493f8008 Fix tests 2016-01-16 10:55:08 -05:00
Kurt Cancemi
c694397d33 Fix X2APIC, AES, XSAVE and OSXSAVE feature detection on AMD processors 2016-01-16 10:53:28 -05:00
Veselin Georgiev
78fef29bd6 Merge pull request #26 from X0rg/request 
Recognize more AMD Trinity CPUs
 2016-01-03 11:47:13 +02:00
Xorg
c1707401e5 Recognize more AMD Trinity CPUs 2016-01-02 18:45:33 +01:00
Veselin Georgiev
7c52fba506 Fix errors and warnings on Windows (tested using MSVC 2003). 2015-11-30 13:47:40 +02:00
Veselin Georgiev
535ec64dd9 Add ucbench to the users list. 2015-11-04 01:35:06 +02:00
Veselin Georgiev
8b64940a0a Convert README to markdown. 
The old file is only kept as required by autotools.
 2015-11-04 01:31:23 +02:00
Veselin Georgiev
0f679a589f Update readme, include "users" info as suggested in issue #24. 2015-11-04 01:31:23 +02:00
Veselin Georgiev
8c7b2fef63 Bump the version to 0.2.2 (and briefly describe changes since 2012). 2015-11-04 01:31:22 +02:00
Veselin Georgiev
9ce5e51cee Add cpuid_get_vendor() function to exports. 2015-10-17 03:05:45 +03:00
Veselin Georgiev
6b09bceb66 Implement cpu_msr_driver_open_core() on Mac OS X and Windows (dummies). 
On Windows, we don't have the API that Linux provides, which can be used
to query MSRs of particular CPU cores. However, the same behaviour can be
emulated. Say that the driver handle object also stores 'dedicated thread
index'. When you call 'cpu_msr_driver_open()', this index is set to -1,
so further API functions do not force which core should be executing
RDMSR code. I.e. "I don't care on which core I run".
However, if this is non-negative number, the subsequent
functions like cpu_rdmsr() are forced to pass through this core by
using temporary affinity mask.
 2015-10-17 03:00:58 +03:00
Veselin Georgiev
3b713ff7a2 Update cpuid_tool to print the new supported MSR info. 2015-10-16 03:07:55 +03:00
Veselin Georgiev
53fe741649 Update errors list; add error messages which had no text description. 2015-10-16 03:07:24 +03:00
Veselin Georgiev
08615d76fe Merge pull request #22 from X0rg/pull_request 
Some new features for function cpu_msrinfo()
 2015-10-16 02:16:35 +03:00
Xorg
d0bb9f1249 Make some functions private 
This commit is to complete commit 7df646a2749f6ef942f9684d66fee14614a74314.
 2015-10-15 16:40:16 +02:00
Xorg
b1cff440b7 Remove cpu_vendor() function, replaced by cpuid_get_vendor() function 2015-10-15 16:40:16 +02:00
Xorg
a853fcd25b Split cpuid_basic_identify() function and add cpuid_get_vendor() function 
These changes are needed to improve cpu_vendor() function. Discussion about these changes come from here (french forum): https://forums.archlinux.fr/viewtopic.php?f=18&t=15973&e=1&view=unread#p147593
The original patch, written by Benjamin ROBIN, is available here: http://pastebin.com/5BHUiCB1
 2015-10-15 16:40:16 +02:00
Xorg
32ddb7d734 Improve code readability since recent changes in function cpu_msrinfo() 2015-10-12 15:58:11 +02:00
Xorg
11b51a105c Implement INFO_TEMPERATURE for Intel in cpu_msrinfo() 2015-10-06 15:39:51 +02:00
Xorg
f11a5b6d16 Modify INFO_MAX_MULTIPLIER for Intel in cpu_msrinfo() 2015-10-06 15:39:51 +02:00
Xorg
ce6ba819f9 Modify INFO_CUR_MULTIPLIER for Intel in cpu_msrinfo() 2015-10-06 15:39:51 +02:00
Xorg
42e8d6f019 Add INFO_BCLK in cpu_msrinfo() 2015-10-06 15:39:51 +02:00
Xorg
fc72fdee74 Add INFO_VOLTAGE in cpu_msrinfo() 2015-10-06 15:39:51 +02:00
Xorg
36f24eae94 Import some functions from i7z 
Get_Bits_Value() is renamed in get_bits_value(), imported from
 5023138d7c/helper_functions.c (L48)
get_msr_value() is renamed in cpu_rdmsr_range(), imported from
 5023138d7c/helper_functions.c (L234)
 2015-10-06 15:39:23 +02:00
Xorg
6c8dfd306f Add function cpu_vendor() to define vendor-specific code 2015-10-06 15:39:23 +02:00
Xorg
79fcdba98e Add function cpu_msr_driver_open_core() 
This function is similar to cpu_msr_driver_open(), but with core number as parameter
For Linux, core number was always 0. To be able to get all core temp/voltage, we need to set the core number.
 2015-10-06 15:39:03 +02:00
Veselin Georgiev
4e3b633bee Fix tests due to X0rg's codename changes. 2015-09-13 18:38:59 +03:00
Veselin Georgiev
4a72a734aa Correctly recognize Sandy Bridge-E Xeons. 
They have L3 cache, and the detection code incorrectly assumed this is a Xeon
Irwindale variant due to an old and no longer valid classification check.
Correctly handle the XEON_IRWIN subcode and add an entry in the matchtable
to fix Sandy Bridge-E Xeon.
 2015-09-13 18:36:23 +03:00
Xorg
f642b79047 Add support for newer Intel CPUs 2015-09-13 18:21:53 +03:00
Xorg
80e6bca100 Some restructuring for Intel Nehalem CPUs and newer 2015-09-13 18:13:43 +03:00
Xorg
505102370b Add support for more AMD CPUs 2015-09-13 18:13:43 +03:00
Veselin Georgiev
153a6a7c7d Add support for detecting Xeon Ivy Bridge. 
Based on report #7 from the sourceforge bugtrack page.
 2015-09-03 09:33:38 +03:00