If a RAW dump is containing for instance 256 logical CPUs (2 sockets with 64 cores and SMT), they should not be considered as a 128 cores CPU with SMT.
* Set CMAKE_C_FLAGS_DEBUG to display warnings during build
CI workflows are reporting warnings. Adding more C flags here help to avoid that.
* Add new types
* Add set_cpu_affinity function
* Add cpu_identify_all function
* Add cpu_request_core_type function
* Add cpuid_get_all_raw_data, cpuid_serialize_all_raw_data and cpuid_deserialize_all_raw_data functions
* Detect hybrid architecture for Intel CPUs
* Update cpuid_tool to detect all CPU logical cores
* Rename tests subdirectories for Intel Core
* Update all tests
Since e4309a6c4bc3ad875711a1599cba01a205b3103e, new fields are reported by cpuid_tool
* Add Intel Alder Lake
Fix#157
* Remove convert_instlatx64.c
This tool is not useful anymore because the cpuid_deserialize_raw_data_internal() function can natively parse them since 5667e1401c
* Fix affinity_mask computation
* Define _GNU_SOURCE in configure.ac
Forgotten in 4f80964db5
* Use dynamic raw array in cpu_raw_data_array_t
* Add cpu_affinity_mask_t type
* Improve set_cpu_affinity function
- Print a warning if logical CPU number is not supported on operating system
- Return a boolean value in case of success instead of an integer
* Improve cpu_identify_all and cpu_request_core_type functions
* Use dynamic array for cpu_types in system_id_t
This commit also adds cleanups, fixes and consistency
* Tests: update Ryzen 5 Matisse with all CPU cores
* Add affinity_mask_str_r function and address other comments
- Fixed cpuid_grow_raw_data_array and cpu_raw_data_array_t.logical_cpu_t with the correct type
- Added a note about hard limit of cpu_raw_data_array_t
- Fixed a typo in cpuid_deserialize_raw_data_internal
* Fix build on Windows
Result before this patch:
Checking enum `cpu_feature_t': 113 elements; max size (CPU_FLAGS_MAX=128)... OK
Checking enum `cpu_hint_t': 1 elements; max size (CPU_HINTS_MAX=16)... OK
Checking enum `cpu_sgx_feature_t': 2 elements; max size (SGX_FLAGS_MAX=14)... OK
Finding features:
..Mismatch - cpuid_main.c:688 - `AVX512VNNI' vs `avx512_vnni'
..Mismatch - cpuid_main.c:689 - `AVX512VBMI' vs `avx512_vbmi'
..Mismatch - cpuid_main.c:690 - `AVX512VBMI2' vs `avx512_vbmi2'
cpuid_main.c: 113 features described
Found 113 total features and 113 named features
Checking whether all features have detection code... FAILED:
..No detection code for CPU_FEATURE_SSE5
Some CPUs does not have the same associativity for L1D and L1I, as reported in X0rg/CPU-X#119
It adds l1_instruction_assoc and l1_instruction_cacheline in cpu_id_t
To avoid confusing, also adds l1_data_assoc and l1_data_cacheline
l1_assoc and l1_cacheline are leave untouched for backward compatibility
Add support for detecting RDSEED and ADX instructions.
Use RDSEED instead of RTM to ascertain that the CPU is
Broadwell or later in recog_intel.c. This fixes
detection discrepancies on Linux, where RTM is not
made available (I guess there's no kernel support for it).
The two new flags are also now detected in the Broadwell
and Skylake tests. Update them as well.
Initial commit adding support for detection of SGX. Not tested yet.
Increment version number due to binary incompatibility of the
sizes of cpu_raw_data_t and cpu_id_t.
This is a backwards-incompatible binary change, which increases
sizeof(cpu_raw_data_t). Specifically, the cpu_raw_data_t::intel_fn4
array is increased from 4 to 8 elements, because on recent Hasells
(Crystalwell) there is a Level 4 cache, which should be encoded in
CPUID eax=4 ecx=4. However, we were only storing levels for eax=4
for ecx <= 3. Thus the raw data didn't have the relevant info.
There will be further changes to this, specifically to store
and print the level 4 cache in cpuid_tool.
- Expose intel_code_t and amd_code_t enums - they are no longer
limited to just recog_{intel,amd}.c.
- Add libcpuid_internal.h lists those enums and provides the,
cpu_ident_internal() function, which is the same as cpu_identify(),
but also has a third parameter - a internal_id_info_t structure,
which holds detection internals.
All of this is intended to be used in rdmsr, which needs to know
specifics on what CPU it is running.
- Detect AVX and AVX2 on both Intel and AMD CPUs
- Detect BMI1 and BMI2 instruction sets (BMI2 is only on Haswell, BMI1 is
also present on Bulldozers).
- Fix tests to reflect changes.
Previously the detection only tested this AMD CPUs and the table check was
only present in recog_amd.c
Thanks to Andrew Roberts for reporting this issue!
Remove the line with the build date of the library from the
raw serialized file format. It doesn't help anything and it
bothers the openSUSE packaging guys. Having the current
date into a binary triggers a warning:
"Current date containing causes unnecessary package
republishing."
Confirmed that "strings libcpuid.a | grep 2014" no longer
contains the current date.
Also, the sse-width guesswork seems to handle this (wrong) Griffin ext_family
explicitly, so fix it there as well.
Seems that members of ext_family 20 (AMD Fusion based APUs) also are 64-bit,
but they have the authoritative sse width detection bit, so we don't need
to handle them explicitly here.
- Move detection of constant_tsc to common; it is spec'd in Intel docs
- Fix broken interpretation of EAX in leaf 80000000h: it shows max
800000xx-value, not max xx-value. This causes, for example, to seek
for extended features on Pentium II, where the extended leafs aren't
supported by the CPU at all.
This is only in common feature detection. AMD detection is fine.
- Add detection of a few new features in AMD leaf 80000007h: cbp (core
performance boost), aperfmperf (APERF/MPERF MSRs supported),
pfi (processor feedback interface) and pa (processor accumulator).
"make test" is broken right now, to be fixed in a subsequent commit.
This adds support for x2apic detection. This is not a direct merge, since
- the feature is spelled as 'x2apic' instead of 'x2APIC', for consistency with other flags;
- tests are added
- the id of the feature is moved to the end of the cpu_feature_t enum, for binary
compatibility.