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122 commits

Author SHA1 Message Date
Xorg
73c33ced4a
Add get_error function for internal use
Sometimes, the _libcpuid_errno value needs to be returned
2022-09-25 10:22:22 +02:00
Xorg
10b4e46179
Fix typo in variable name 2022-09-25 10:11:39 +02:00
Xorg
871840f8e5
Fix cpuid_serialize_raw_data_internal when no filename is provided 2022-09-24 18:57:35 +02:00
Xorg
49cb8703ca
Typo (RAW to raw) 2022-09-23 18:44:38 +02:00
Xorg
dc406c4de1
Do not print the same message twice when reading a raw CPUID dump 2022-09-23 18:44:11 +02:00
Xorg
3ed66b7613
Treat others CPU packages as different CPU types
If a RAW dump is containing for instance 256 logical CPUs (2 sockets with 64 cores and SMT), they should not be considered as a 128 cores CPU with SMT.
2022-09-22 21:50:08 +02:00
Xorg
6b742be8cb Add cache instances field in cpu_id_t and system_id_t 2022-09-22 17:49:38 +02:00
Umio Yasuno
2ec692b579 Fix null pointer dereference in cpuid_deserialize_raw_data_internal 2022-09-20 18:34:46 +02:00
Xorg
ff5aafb5f4 Detect Virtual Machine
Fix #90
2022-09-18 10:26:02 +02:00
Xorg
2b8023f733
Support for hybrid CPU (#166)
* Set CMAKE_C_FLAGS_DEBUG to display warnings during build

CI workflows are reporting warnings. Adding more C flags here help to avoid that.

* Add new types

* Add set_cpu_affinity function

* Add cpu_identify_all function

* Add cpu_request_core_type function

* Add cpuid_get_all_raw_data, cpuid_serialize_all_raw_data and cpuid_deserialize_all_raw_data functions

* Detect hybrid architecture for Intel CPUs

* Update cpuid_tool to detect all CPU logical cores

* Rename tests subdirectories for Intel Core

* Update all tests

Since e4309a6c4bc3ad875711a1599cba01a205b3103e, new fields are reported by cpuid_tool

* Add Intel Alder Lake

Fix #157

* Remove convert_instlatx64.c

This tool is not useful anymore because the cpuid_deserialize_raw_data_internal() function can natively parse them since 5667e1401c

* Fix affinity_mask computation

* Define _GNU_SOURCE in configure.ac

Forgotten in 4f80964db5

* Use dynamic raw array in cpu_raw_data_array_t

* Add cpu_affinity_mask_t type

* Improve set_cpu_affinity function

- Print a warning if logical CPU number is not supported on operating system
- Return a boolean value in case of success instead of an integer

* Improve cpu_identify_all and cpu_request_core_type functions

* Use dynamic array for cpu_types in system_id_t

This commit also adds cleanups, fixes and consistency

* Tests: update Ryzen 5 Matisse with all CPU cores

* Add affinity_mask_str_r function and address other comments

- Fixed cpuid_grow_raw_data_array and cpu_raw_data_array_t.logical_cpu_t with the correct type
- Added a note about hard limit of cpu_raw_data_array_t
- Fixed a typo in cpuid_deserialize_raw_data_internal

* Fix build on Windows
2022-09-15 18:37:08 +02:00
emixa-d
bca7a19279
Report memory allocation failures without segfaulting. (#160) 2022-01-23 02:38:40 +02:00
Xorg
9abab57bdc
Fix code consistency
Result before this patch:

Checking enum `cpu_feature_t': 113 elements; max size (CPU_FLAGS_MAX=128)... OK
Checking enum `cpu_hint_t': 1 elements; max size (CPU_HINTS_MAX=16)... OK
Checking enum `cpu_sgx_feature_t': 2 elements; max size (SGX_FLAGS_MAX=14)... OK
Finding features:
..Mismatch - cpuid_main.c:688 - `AVX512VNNI' vs `avx512_vnni'
..Mismatch - cpuid_main.c:689 - `AVX512VBMI' vs `avx512_vbmi'
..Mismatch - cpuid_main.c:690 - `AVX512VBMI2' vs `avx512_vbmi2'
  cpuid_main.c: 113 features described
Found 113 total features and 113 named features
Checking whether all features have detection code... FAILED:
..No detection code for CPU_FEATURE_SSE5
2020-05-23 18:24:30 +02:00
Xorg
180154f03d
Detect AVX512VBMI and AVX512VBMI2 features on Intel CPUs
More information: https://en.wikichip.org/wiki/x86/avx-512
Resolve #134
2020-05-18 22:05:01 +02:00
Xorg
4b06a9a23e
Detect ABM feature on Intel CPUs
Resolve #144
2020-05-18 21:11:01 +02:00
Xorg
9419c573ca
Detect RDSEED/ADX/SHA_NI features on AMD CPUs
These x86 instruction set extensions are present since Zen micro-architecture
Resolve #145
2020-05-18 21:05:20 +02:00
Veselin Georgiev
8db3b8d2d3
Merge pull request #142 from ClickHouse-Extras/fix-tsan
Fix TSan report
2020-05-11 09:10:48 +03:00
alexey-milovidov
a9fe7b6aca
Update cpuid_main.c 2020-05-11 00:26:23 +03:00
Xorg
25d0614811
Add L1 Instruction Cache information
Some CPUs does not have the same associativity for L1D and L1I, as reported in X0rg/CPU-X#119
It adds l1_instruction_assoc and l1_instruction_cacheline in cpu_id_t
To avoid confusing, also adds l1_data_assoc and l1_data_cacheline
l1_assoc and l1_cacheline are leave untouched for backward compatibility
2020-05-10 11:49:02 +02:00
Xorg
e562798cec
Re-fix L3 cache associativity detection on AMD Zen 2 CPUs
Previous commit: 848394ee46
2020-05-09 22:39:42 +02:00
Alexey Milovidov
6f8449d88e Applied a patch from @tavplubix 2020-05-09 21:07:16 +03:00
Xorg
b23145144f
Use constant for registers name
It helps when reading technical documentation and it avoids 'magic values'
2020-05-09 18:17:50 +02:00
Xorg
0b05f45e03
Remove all trailling spaces
It is annoying with some text editors
2020-05-09 17:34:07 +02:00
Robert Kausch
2159f73eaa Add support for get_total_cpus on Haiku. 2019-10-29 20:38:55 +01:00
Leslie-Fang
8f91df526d add support to feature intel avx512_vnni 2019-08-08 22:06:23 +08:00
hygonsoc
8c0a01890c Add Hygon Dhyana detect support
Signed-off-by: hygonsoc <hygonsoc@gmail.com>
2019-04-13 23:08:03 +08:00
Veselin Georgiev
e36a08deb9 Fixed issue #76: Skylake Core i5 badly recognized
Add support for detecting RDSEED and ADX instructions.
Use RDSEED instead of RTM to ascertain that the CPU is
Broadwell or later in recog_intel.c. This fixes
detection discrepancies on Linux, where RTM is not
made available (I guess there's no kernel support for it).

The two new flags are also now detected in the Broadwell
and Skylake tests. Update them as well.
2016-10-25 05:16:44 +03:00
Veselin Georgiev
4cf8cfa862 Related to issue #67: Information about the availability of SGX
Initial commit adding support for detection of SGX. Not tested yet.
Increment version number due to binary incompatibility of the
sizes of cpu_raw_data_t and cpu_id_t.
2016-10-03 13:07:22 +03:00
Xorg
4b4b49b288 Fix build on GhostBSD 10.3 2016-09-22 17:11:47 +02:00
Veselin Georgiev
3f51d3ca25 Add detection of L4 cache. 2016-06-09 15:42:57 +03:00
Veselin Georgiev
c31b5c0ae8 Add up to 8 entries for CPUID leaf 04; push version to 0.3.0.
This is a backwards-incompatible binary change, which increases
sizeof(cpu_raw_data_t). Specifically, the cpu_raw_data_t::intel_fn4
array is increased from 4 to 8 elements, because on recent Hasells
(Crystalwell) there is a Level 4 cache, which should be encoded in
CPUID eax=4 ecx=4. However, we were only storing levels for eax=4
for ecx <= 3. Thus the raw data didn't have the relevant info.

There will be further changes to this, specifically to store
and print the level 4 cache in cpuid_tool.
2016-06-03 04:35:01 +03:00
Veselin Georgiev
a2550463a9 Reorganize library a bit.
- Expose intel_code_t and amd_code_t enums - they are no longer
  limited to just recog_{intel,amd}.c.
- Add libcpuid_internal.h lists those enums and provides the,
  cpu_ident_internal() function, which is the same as cpu_identify(),
  but also has a third parameter - a internal_id_info_t structure,
  which holds detection internals.

All of this is intended to be used in rdmsr, which needs to know
specifics on what CPU it is running.
2016-06-03 03:30:36 +03:00
Veselin Georgiev
7c7a0fea8b Merge pull request #43 from X0rg/master
Changes for MSR
2016-05-19 22:09:51 +01:00
Veselin Georgiev
7b9fe29cef Support for Skylake.
- Detection of hle, rtm, avx512* and sha-ni instructions
- Detection for Skylake
- Add test with Skylake i5
2016-05-19 01:37:45 +03:00
Xorg
c9926ab6f7 Imrove cpu_rdmsr_range(), make header similar to cpu_rdmsr() 2016-05-18 14:59:55 +02:00
Kurt Cancemi
6ea1d4c8e2 Fix PCLMULQDQ, SSE4.1, MOVBE and RDRAND detection on AMD processors 2016-04-24 00:24:31 -04:00
Kurt Cancemi
c694397d33 Fix X2APIC, AES, XSAVE and OSXSAVE feature detection on AMD processors 2016-01-16 10:53:28 -05:00
Veselin Georgiev
53fe741649 Update errors list; add error messages which had no text description. 2015-10-16 03:07:24 +03:00
Xorg
a853fcd25b Split cpuid_basic_identify() function and add cpuid_get_vendor() function
These changes are needed to improve cpu_vendor() function. Discussion about these changes come from here (french forum): https://forums.archlinux.fr/viewtopic.php?f=18&t=15973&e=1&view=unread#p147593
The original patch, written by Benjamin ROBIN, is available here: http://pastebin.com/5BHUiCB1
2015-10-15 16:40:16 +02:00
Veselin Georgiev
046d2ca2ab Better support for AVX, AVX2, BMI1 and BMI2 instruction set detection.
- Detect AVX and AVX2 on both Intel and AMD CPUs
- Detect BMI1 and BMI2 instruction sets (BMI2 is only on Haswell, BMI1 is
  also present on Bulldozers).
- Fix tests to reflect changes.
2015-04-16 20:54:37 +03:00
Robert Kausch
f7e6c6b274 Add cpuid_get_total_cpus to allow getting the total number of CPUs on systems without CPUID. 2014-09-27 17:46:19 +03:00
Robert Kausch
72d49bdd6f Add support for get_total_cpus on *BSD and Solaris. 2014-09-27 17:46:19 +03:00
Veselin Georgiev
fa2083a992 Add support for detecting AVX2. Confirmed to detect on Haswell i3. 2014-09-24 00:03:11 +03:00
Veselin Georgiev
fc4ff90ea8 Recognize presence of RDTSCP on Intel CPUs as well.
Previously the detection only tested this AMD CPUs and the table check was
only present in recog_amd.c

Thanks to Andrew Roberts for reporting this issue!
2014-09-23 15:11:00 +03:00
Veselin Georgiev
9b949d1dff Fixed issue #6: file-contains-current-date
Remove the line with the build date of the library from the
raw serialized file format. It doesn't help anything and it
bothers the openSUSE packaging guys. Having the current
date into a binary triggers a warning:

"Current date containing causes unnecessary package
republishing."

Confirmed that "strings libcpuid.a | grep 2014" no longer
contains the current date.
2014-08-04 14:02:35 +03:00
Veselin Georgiev
5052ad4d1f Fixed a detection for Turion Griffin - it's ext_family is not 23, it's 17.
Also, the sse-width guesswork seems to handle this (wrong) Griffin ext_family
explicitly, so fix it there as well.

Seems that members of ext_family 20 (AMD Fusion based APUs) also are 64-bit,
but they have the authoritative sse width detection bit, so we don't need
to handle them explicitly here.
2014-07-23 22:06:11 +03:00
Veselin Georgiev
f883e2b592 Add recognition support for Haswell i3, i5 and i7.
Add a test based on a Haswell i3 (Core i3-4130).
2014-07-18 21:00:48 +03:00
Veselin Georgiev
f750dde2c0 Fixed issue #4: Advanced Power Management Features
- Move detection of constant_tsc to common; it is spec'd in Intel docs
- Fix broken interpretation of EAX in leaf 80000000h: it shows max
  800000xx-value, not max xx-value. This causes, for example, to seek
  for extended features on Pentium II, where the extended leafs aren't
  supported by the CPU at all.
  This is only in common feature detection. AMD detection is fine.
- Add detection of a few new features in AMD leaf 80000007h: cbp (core
  performance boost), aperfmperf (APERF/MPERF MSRs supported),
  pfi (processor feedback interface) and pa (processor accumulator).

"make test" is broken right now, to be fixed in a subsequent commit.
2014-06-30 03:07:33 +03:00
Veselin Georgiev
798bcc80b2 Remove a space, which causes "make consistency" to frown. 2014-06-30 02:36:33 +03:00
Veselin Georgiev
45651ef7bc Merge 141243f from http://github.com/eloaders/libcpuid
This adds support for x2apic detection. This is not a direct merge, since

- the feature is spelled as 'x2apic' instead of 'x2APIC', for consistency with other flags;
- tests are added
- the id of the feature is moved to the end of the cpu_feature_t enum, for binary
  compatibility.
2014-06-22 21:00:18 +03:00
Veselin Georgiev
1344ec1a81 Added support for detecting the following processors: The newer 6 and 8-core Sandy Bridges (termed Sandy Bridge-E), Ivy Bridge, AMD Magny-Cours. Added support for detecting the rdrand instruction. Added tests.
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@104 3b4be424-7ac5-41d7-8526-f4ddcb85d872
2012-05-26 13:00:04 +00:00