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178 commits

Author SHA1 Message Date
Xorg
cbaa02a966
DB: add Rembrandt 2022-08-28 11:22:03 +02:00
Xorg
ecd45bb276
Tests: add more Zen2 tests from InstLatx64 2022-02-06 11:52:55 +01:00
Xorg
5ce462c32c
DB: add Lucienne
https://en.wikichip.org/wiki/amd/cores/lucienne
Fix X0rg/CPU-X#209
2022-02-06 11:29:46 +01:00
Xorg
0f1ad69145
DB: add Tiger Lake
https://en.wikipedia.org/wiki/Tiger_Lake
Related to X0rg/CPU-X#198
2021-05-26 06:57:04 +02:00
Xorg
1843292dba
Tests: fix truncation warnings in convert_instlatx64 2021-03-20 18:14:06 +01:00
Xorg
167d059a6b
DB: add Rocket Lake
https://en.wikichip.org/wiki/intel/microarchitectures/rocket_lake
InstLatx64/InstLatx64@1bbddafe7b
2021-03-20 17:24:58 +01:00
Xorg
c8238acd0a
DB: add Milan
https://en.wikichip.org/wiki/amd/cores/milan
InstLatx64/InstLatx64@2dc186e948
2021-03-20 17:10:07 +01:00
Xorg
d97618ab4f
Tests: fix --create argument in convert_instlatx64 tool 2021-01-31 15:26:13 +01:00
Xorg
08b4b6e41b
DB: add Cezanne
Tests extracted from InstLatx64/InstLatx64@002ce3c923
2021-01-31 15:24:39 +01:00
Xorg
4382796761
DB: add Xeon E3 1275
Score for entry 'Bloomfield (Xeon)' is 10 with this CPU
So it does not match with entry 'Sandy Bridge (Xeon)' (also score 10)
Adding this new entry increase score to 12, and fixing this issue

Close X0rg/CPU-X#182
2021-01-28 20:24:06 +01:00
Xorg
9468598740
Tests: add Core i5 8265U (Whiskey Lake-U)
See f61e3f80db
2021-01-12 19:48:38 +01:00
Xorg
d60503c211
Tests: fix path for cpuid_tool
When we use CMake, the 'cpuid_tool' binary is in the 'build' directory
2020-11-14 13:45:15 +01:00
Xorg
04c3ebe0e9
DB: add Vermeer
https://en.wikichip.org/wiki/amd/cores/vermeer
Test file converted from http://users.atw.hu/instlatx64/AuthenticAMD/AuthenticAMD0A20F10_K19_Vermeer_CPUID1.txt
2020-11-14 13:45:15 +01:00
Xorg
98c9b6ff53
DB: add Gemini Lake
https://en.wikichip.org/wiki/intel/cores/gemini_lake
Reported in X0rg/CPU-X#164
2020-11-14 13:45:15 +01:00
Xorg
672720c501
DB: add Comet Lake-U
https://en.wikipedia.org/wiki/Comet_Lake_(microprocessor)#U-series_(Medium_power)
Reported in X0rg/CPU-X#162
2020-11-14 13:45:14 +01:00
Xorg
4846161cfc
DB: add Kaby Lake-G
https://en.wikichip.org/wiki/intel/cores/kaby_lake_g
Test file converted from http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel00906E9_KabylakeG_CPUID.txt
2020-11-14 13:45:14 +01:00
Xorg
77dfe98a4c
DB: add Kaby Lake Refresh
https://en.wikichip.org/wiki/intel/cores/kaby_lake_r
Core i5 8250U was detected as Coffee Lake wrongly.
Reported in X0rg/CPU-X#161
2020-11-14 13:45:14 +01:00
Veselin Georgiev
52c5f505cf Related to c2645d0. Convert all python scripts to Python 3.
As stated in discussion, Python 2 is actively being deprecated
and the fix is easy, almost automatic.
2020-05-28 19:57:30 +03:00
Xorg
9abab57bdc
Fix code consistency
Result before this patch:

Checking enum `cpu_feature_t': 113 elements; max size (CPU_FLAGS_MAX=128)... OK
Checking enum `cpu_hint_t': 1 elements; max size (CPU_HINTS_MAX=16)... OK
Checking enum `cpu_sgx_feature_t': 2 elements; max size (SGX_FLAGS_MAX=14)... OK
Finding features:
..Mismatch - cpuid_main.c:688 - `AVX512VNNI' vs `avx512_vnni'
..Mismatch - cpuid_main.c:689 - `AVX512VBMI' vs `avx512_vbmi'
..Mismatch - cpuid_main.c:690 - `AVX512VBMI2' vs `avx512_vbmi2'
  cpuid_main.c: 113 features described
Found 113 total features and 113 named features
Checking whether all features have detection code... FAILED:
..No detection code for CPU_FEATURE_SSE5
2020-05-23 18:24:30 +02:00
Xorg
7c7fd3b565
CMake: fix build on Windows 2020-05-22 22:06:34 +02:00
Xorg
1a00dac1ee
tests: fix unused-result warning in convert_instlatx64 tool 2020-05-21 19:00:26 +02:00
Xorg
7179a7b103
CMake: fix Unix install and format 2020-05-21 18:43:34 +02:00
Xorg
180154f03d
Detect AVX512VBMI and AVX512VBMI2 features on Intel CPUs
More information: https://en.wikichip.org/wiki/x86/avx-512
Resolve #134
2020-05-18 22:05:01 +02:00
Xorg
4b06a9a23e
Detect ABM feature on Intel CPUs
Resolve #144
2020-05-18 21:11:01 +02:00
Xorg
9419c573ca
Detect RDSEED/ADX/SHA_NI features on AMD CPUs
These x86 instruction set extensions are present since Zen micro-architecture
Resolve #145
2020-05-18 21:05:20 +02:00
Xorg
ef8986407f DB: add Ivy Bridge-E (Xeon) 2020-05-10 17:02:45 +00:00
Xorg
fb1deb1fef Tests: update all tests to add fields for L1I 2020-05-10 17:02:45 +00:00
Xorg
e592a83278 Tests: update to add L1I information
Related to 25d0614811
Dump of Core i5 520m from CPU-X#119
2020-05-10 17:02:45 +00:00
Xorg
6b5a1f5ea6
Tests: add amd_fn8000001dh subleaf
See e562798cec
2020-05-09 22:48:07 +02:00
Xorg
3a346d4d72
Tests: parse subleafs in convert_instlatx64
Also, it adds 0xffffffff when data is not available, so all lines are presents
2020-05-09 22:46:13 +02:00
Xorg
0b05f45e03
Remove all trailling spaces
It is annoying with some text editors
2020-05-09 17:34:07 +02:00
Xorg
8720a71b35
Tests: add Core i5 8250U
Related to X0rg/CPU-X#129
2020-05-09 14:46:59 +02:00
Veselin Georgiev
9d22c61611
Merge pull request #141 from X0rg/master
Fixes for AMD Zen 2 CPUs
2020-05-04 21:35:42 +03:00
Xorg
46e86331bb
tests: remove duplicate addresses in RAW part 2020-05-03 17:12:33 +02:00
Xorg
afbd7ae56d
tests: fix convert_instlatx64 tool 2020-05-03 17:09:54 +02:00
Xorg
848394ee46
Fix L3 cache associativity detection on AMD Zen 2 CPUs 2020-05-03 17:07:43 +02:00
eloaders
5f7f3c26cc DB: Add Threadripper (Castle Peak) 2019-12-31 10:58:20 +01:00
Veselin Georgiev
f6e4e23796 Add Xeon CLX (Cascade lake-based) using data from PR #129
Kudos to Leslie-Fang for providing it!
2019-08-09 11:18:20 +03:00
Veselin Georgiev
96810180a0
Merge pull request #126 from X0rg/master
Fix for Zen 2
2019-07-12 11:20:06 +03:00
Xorg
848354a3f1 Tests: Add more Matisse CPUs 2019-07-11 22:49:08 +02:00
Xorg
bf7f57f519 Fix SSE unit size for Zen 2 CPUs
Related to #125
2019-07-11 22:29:27 +02:00
Veselin Georgiev
ab3bc3defe
Merge pull request #125 from X0rg/master
More test files for AMD Zen CPUs
2019-07-11 08:34:24 +03:00
Xorg
5aedd53624 Add more test files for AMD Zen CPUs
Dumps found on http://instlatx64.atw.hu/
2019-07-07 20:03:45 +02:00
Xorg
081c354d17 DB: Add AMD Ryzen 3000 2019-07-07 19:38:46 +02:00
hygonsoc
9f0012b74b add Hygon Dhyana C86 7seris test file
Signed-off-by: hygonsoc <hygonsoc@gmail.com>
2019-04-13 23:08:41 +08:00
Xorg
3a8343c77c Fix Ryzen core count calculation
Close X0rg/CPU-X#86
2018-11-03 21:30:01 +01:00
Xorg
7358232cc4 DB: Add Kaby Lake-U 2018-09-23 22:06:53 +02:00
Xorg
218015a983 Tests: Add Pentium 4405U 2018-08-08 15:02:08 +02:00
Xorg
9c382e33b3 DB: Add Skylake-X CPUs 2018-08-08 14:51:38 +02:00
Xorg
c2645d0dff Force Python 2.7 in all Python scripts
/usr/bin/python is Python 3.7 on Arch Linux, so it doesn't work
2018-08-08 13:54:14 +02:00
Veselin Georgiev
45d04a9e4a Fix P-III Celeron misdetected as plain P-III (misreport id #8)
Reported via http://libcpuid.sourceforge.net/bugreport.php
The test in particular has no brand string, which was causing the
misdetection (as is the case with a lot of other models, libcpuid
relies on accurate brand string being programmed by the BIOS in
order to do the detection).

The actual CPU was a Pentium-III based Celeron (SL54Q), but it
was detected as "Pentium III (Coppermine)".

A bit of historical trivia: for the related Tualatin models, if
the BIOS doesn't enter a brand string, there might be NO WAY to
tell a regular P-3 and a P-3 Celeron apart: P-3s have variants
with 256KiB and 512KiB L2 cache, while the Celerons are 256 KiB, so
a 256KiB regular P3 is no different than its corresponding Celeron.
Only the FSB is different, but there's no way to detect this via
CPUID.

For the Coppermines its an easier case: Celerons are always 128KiB,
and Pentia are 256KiB, so I've added this distinction in the tables.
2018-05-02 11:05:25 +03:00
anonymous
a9c739d312 virtual machine test 2018-04-21 01:00:30 +00:00
Xorg
f1e1ad58e7 DB: Add Raven Ridge APUs and Threadripper CPUs 2018-03-20 19:52:40 +01:00
Veselin Georgiev
f178de98f3 Fix issue #104: Intel Coffee Lake and Kaby Lake
Add support for detecting Coffee Lake i[357]s. Test included.
Thanks to @X0rg for reporting and to @exdeus for the raw cpu data.

The detection here relies on Kaby and Coffee lakes having different
number of cores for the equivalent brand:

i3: 2 cores in Kaby, 4 in Coffee
i5 and i7: 4 cores in Kaby, 6 in Coffee.
2018-02-04 13:37:36 +02:00
Veselin Georgiev
2f4c21e3a7 Fixed issue #103: Intel Xeon Scalable not recognised "code name".
Table entry added, test added, thanks to @phprus for reporting.
2018-01-28 02:06:37 +02:00
Veselin Georgiev
94507ded22 Fixed issue #86: AMD Ryzen support
Also add a test of Ryzen 7 (1800X).
2017-03-20 02:28:28 +02:00
Xorg
bb4141a25a Enforce Python 2.7 in tests 2017-03-12 09:34:26 +01:00
Veselin Georgiev
86bf8e8269 Fixed issue #81: Misdiagnosis microarchitecture for i3-3220T
It's a mystery to me why this CPU doesn't have RdRand.
A quick-n-dirty workaround is inserted to fix that.
2017-02-10 03:48:00 +02:00
Veselin Georgiev
e36a08deb9 Fixed issue #76: Skylake Core i5 badly recognized
Add support for detecting RDSEED and ADX instructions.
Use RDSEED instead of RTM to ascertain that the CPU is
Broadwell or later in recog_intel.c. This fixes
detection discrepancies on Linux, where RTM is not
made available (I guess there's no kernel support for it).

The two new flags are also now detected in the Broadwell
and Skylake tests. Update them as well.
2016-10-25 05:16:44 +03:00
Veselin Georgiev
3f38efb6c9 Fixed issue #54: Intel Atom N450 not recognised properly
Improved parsing of brand strings for both Pineview and Cedarview
Atoms.

Add tests for both the Pineview Atom, and also Broadwell-E
(forgotten in a previous commit).
2016-08-24 15:06:40 +03:00
Veselin Georgiev
87f3052a7b Add a test with L4 cache (courtesy of @phprus).
The test is a snapshot of a Haswell i7 (a.k.a. "Crystalwell") core.
This is the only test in the test DB right now which has lines for
L4 cache size, associativity and cacheline size different than "-1".

Also update create_test.py to accommodate for the new fields.
2016-07-07 00:53:03 +03:00
Veselin Georgiev
f52c02d394 Update all tests: add fields for L4 cache size, assoc. and line size. 2016-07-07 00:44:45 +03:00
Veselin Georgiev
7b9fe29cef Support for Skylake.
- Detection of hle, rtm, avx512* and sha-ni instructions
- Detection for Skylake
- Add test with Skylake i5
2016-05-19 01:37:45 +03:00
Veselin Georgiev
3a977a4f99 Add detection support for the AMD TBM instructions. Update Vishera test. 2016-05-19 01:37:45 +03:00
wdlkmpx
be254c30ef Add 2 Intel P4 tests / Rename some tests/codenames
Rename some codenames to keep things tidy
2016-05-17 13:08:16 +03:00
wdlkmpx
061bd5986c Ability to display AMD brand code
So that it's easier to test and debug

Also added AMD Champlain mobile
Processor: AMD Athlon(tm) II P320 Dual-Core Processor
2016-05-11 21:21:02 +00:00
wdlkmpx
7aa3155fc5 Add Arrandale mobile
Processor: Intel(R) Pentium(R) CPU        P6100  @ 2.00GHz
2016-05-07 19:43:33 +00:00
wdlkmpx
4047785e97 Recognize Dual Core (Penryn) and more Core2 processors
By adding a new entry to the match table

There's also a new test:
 Intel Pentium Dual-Core Mobile T4500
 Specs:
 http://www.cpu-world.com/CPUs/Pentium_Dual-Core/Intel-Pentium%20Dual-Core%20Mobile%20T4500%20AW80577GG0521MA.html
2016-04-28 00:28:07 +00:00
Veselin Georgiev
db6f3abc9a Merge pull request #34 from wdlkmpx/master
Fix issue with HyperThreading status in old cpus
2016-04-25 01:51:24 +03:00
wdlkmpx
f26c1151f0 Fix issue with HyperThreading status in old cpus
Early P4 processors come with the HT flag, but that feature
is not enabled.

This makes it work the way it should.
2016-04-24 17:28:16 +00:00
wdlkmpx
fa9640b3a2 tests: add p4 celeron willamette-128
1.8GHz
Specs:
http://www.cpu-world.com/CPUs/Celeron/Intel-Celeron%201800%20-%20RK80531RC033128%20(BX80531P180G128).html
2016-04-24 17:26:44 +00:00
wdlkmpx
75c3c36cbb tests: add intel p4 prescott with HT enabled
This is from a Pentium 4 Prescott 3.20GHz processor
Specs:
http://www.cpu-world.com/CPUs/Pentium_4/Intel-Pentium%204%203.2%20GHz%20-%20RK80546PG0881M%20(BX80546PG3200E).html
2016-04-24 17:26:03 +00:00
Kurt Cancemi
dea8a6006a Fix tests 2016-04-24 00:27:42 -04:00
wdlkmpx
5f420362c6 P4 Celeron: more precise descriptions
According to wikipedia, cpu-world and some cpu-z screenshots, these processors
do have a code name and it's willamette, northwood, prescott or cedar mill

Signed-off-by: Veselin Georgiev <anrieff@gmail.com>
2016-04-19 00:57:11 +03:00
Veselin Georgiev
13f382725b Fix 'make test' failing without any really wrong tests.
The reason was that the invocation of the cpuid_tool through the makefile
was using LD_LIBRARY_PATH=. to force link&use of the latest-build libcpuid
library. This doesn't seem to work, so using LD_PRELOAD to explicitly load
libcpuid.so into cpuid_tool.

The committed approach of course doesn't work on Mac OS X, where
make test-old should be used.
2016-03-10 02:44:17 +02:00
Kurt Cancemi
c5493f8008 Fix tests 2016-01-16 10:55:08 -05:00
Veselin Georgiev
4e3b633bee Fix tests due to X0rg's codename changes. 2015-09-13 18:38:59 +03:00
Veselin Georgiev
153a6a7c7d Add support for detecting Xeon Ivy Bridge.
Based on report #7 from the sourceforge bugtrack page.
2015-09-03 09:33:38 +03:00
Veselin Georgiev
812b89bcb8 'make test' ported to run on Python 2.5 as well. 2015-04-20 17:22:11 +03:00
Veselin Georgiev
94fc6ae36a Modify the table matcher a bit. Put some weights on the different fields.
Priously all fields in the matchtable were treated equal in importance.
With this change, the cache size a taken with half the weight in the decision.

Also add detection entries for some more recent Haswells, and the respective
tests. These are an i5 Haswell from a Mac Book Pro, and a i7 Haswel from
Thinkpad T540.
2015-04-17 01:21:30 +03:00
Veselin Georgiev
046d2ca2ab Better support for AVX, AVX2, BMI1 and BMI2 instruction set detection.
- Detect AVX and AVX2 on both Intel and AMD CPUs
- Detect BMI1 and BMI2 instruction sets (BMI2 is only on Haswell, BMI1 is
  also present on Bulldozers).
- Fix tests to reflect changes.
2015-04-16 20:54:37 +03:00
Veselin Georgiev
fa2083a992 Add support for detecting AVX2. Confirmed to detect on Haswell i3. 2014-09-24 00:03:11 +03:00
Veselin Georgiev
ce02f0bc96 Fix broken tests, where rdtscp in recent Intel chips is missing.
As described in previous commit.
2014-09-23 15:21:02 +03:00
Veselin Georgiev
a716585cc0 Add to makefile: "make fix-tests" to fix failing tests.
The last change to flags detection caused a bunch of tests to fail.
The reason is that they are bogus, all recent Intel chips don't have
RDTSCP indicated in the test files, whereas they have it in reality.
I figured it will be easier to add "--fix" option to run_tests.py,
rather than fixing each testfile by hand.

This is also extended in the Makefile:

"make test" runs the tests and reports discrepancies.
"make fix-tests" fixes any offending tests. This blindly assumes that
libcpuid is sane.
2014-09-23 15:20:27 +03:00
Veselin Georgiev
ece31fb8d3 Add a test for Atom N2800 (codename Cedarview). 2014-08-20 11:25:52 +03:00
Veselin Georgiev
d80ae596ab Fix bogus tests in the Atom category
- Atom Dual-core (Diamondville) is renamed to just Atom (Diamondville)
- The test with Atom D425 is named "Pineview", while the one with
  Atom D525 was incorrectly named "Cedarview". Moving the latter to
  atom-pineview-2.test and fixing its codename.
2014-08-20 11:22:25 +03:00
Veselin Georgiev
b183a2d2f8 Magny-cours is still K10, so move the test to the proper dir. 2014-07-23 22:30:52 +03:00
Veselin Georgiev
decba3e728 Simplify Bulldozer detection; differentiate Bulldozer<->Vishera.
Also add two tests:
- AMD FX-8150 - which is decoded as 'Bulldozer X4'
- AMD FX-9590 - which is decoted as 'Vishera X4'
2014-07-23 22:13:37 +03:00
Veselin Georgiev
f883e2b592 Add recognition support for Haswell i3, i5 and i7.
Add a test based on a Haswell i3 (Core i3-4130).
2014-07-18 21:00:48 +03:00
Veselin Georgiev
551aff201b When creating a tarball, include the small tests now instead of tests_stash.txt 2014-07-16 10:29:58 +03:00
Veselin Georgiev
989ea9f586 Delete unused old test data/utils. 2014-07-16 10:11:28 +03:00
Veselin Georgiev
f6acf1b634 Refactor "make test" as well. 2014-07-16 10:10:51 +03:00
Veselin Georgiev
019170b65f Refactor the tests: put each test case in a separate file
Instead of one big pile of tests in tests_stash.txt, keep each CPU
example raw data/parsed data in a file, ordered in a tree by
manufacturer and microarchitecture. The 64 .test files have been
extracted from tests_stash.txt. The add_test script is changed to
create_test and it doesn't append to test_stash.txt, instead it
spits out data to be saved in a .test file.

run_tests.py is not refactored yet, to be done in a subsequent commit.
2014-07-15 19:59:35 +03:00
Veselin Georgiev
3c9aa04f13 Rename: add_test.py -> create_test.py 2014-07-15 17:56:16 +03:00
Veselin Georgiev
fbed394404 Change add_test.py to output the concatenated raw/report to stdout.
Instead of appending it to test_stash.
2014-07-15 17:55:39 +03:00
Veselin Georgiev
20632054d6 Add support for Atom Pineview. 2014-06-23 23:41:02 +03:00
Veselin Georgiev
45651ef7bc Merge 141243f from http://github.com/eloaders/libcpuid
This adds support for x2apic detection. This is not a direct merge, since

- the feature is spelled as 'x2apic' instead of 'x2APIC', for consistency with other flags;
- tests are added
- the id of the feature is moved to the end of the cpu_feature_t enum, for binary
  compatibility.
2014-06-22 21:00:18 +03:00
Veselin Georgiev
f385bac458 Added support for Intel Atom Cedarview
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@107 3b4be424-7ac5-41d7-8526-f4ddcb85d872
2012-09-09 22:28:55 +00:00
Veselin Georgiev
1344ec1a81 Added support for detecting the following processors: The newer 6 and 8-core Sandy Bridges (termed Sandy Bridge-E), Ivy Bridge, AMD Magny-Cours. Added support for detecting the rdrand instruction. Added tests.
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@104 3b4be424-7ac5-41d7-8526-f4ddcb85d872
2012-05-26 13:00:04 +00:00
Veselin Georgiev
9fafda1bed Added support for Sandy-bridge based celerons
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@101 3b4be424-7ac5-41d7-8526-f4ddcb85d872
2011-10-13 22:46:42 +00:00