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Author SHA1 Message Date
Veselin Georgiev
87f3052a7b Add a test with L4 cache (courtesy of @phprus). 
The test is a snapshot of a Haswell i7 (a.k.a. "Crystalwell") core.
This is the only test in the test DB right now which has lines for
L4 cache size, associativity and cacheline size different than "-1".

Also update create_test.py to accommodate for the new fields.
 2016-07-07 00:53:03 +03:00
Veselin Georgiev
f52c02d394 Update all tests: add fields for L4 cache size, assoc. and line size. 2016-07-07 00:44:45 +03:00
Veselin Georgiev
7b9fe29cef Support for Skylake. 
- Detection of hle, rtm, avx512* and sha-ni instructions
- Detection for Skylake
- Add test with Skylake i5
 2016-05-19 01:37:45 +03:00
Veselin Georgiev
3a977a4f99 Add detection support for the AMD TBM instructions. Update Vishera test. 2016-05-19 01:37:45 +03:00
wdlkmpx
be254c30ef Add 2 Intel P4 tests / Rename some tests/codenames 
Rename some codenames to keep things tidy
 2016-05-17 13:08:16 +03:00
wdlkmpx
061bd5986c Ability to display AMD brand code 
So that it's easier to test and debug

Also added AMD Champlain mobile
Processor: AMD Athlon(tm) II P320 Dual-Core Processor
 2016-05-11 21:21:02 +00:00
wdlkmpx
7aa3155fc5 Add Arrandale mobile 
Processor: Intel(R) Pentium(R) CPU        P6100  @ 2.00GHz
 2016-05-07 19:43:33 +00:00
wdlkmpx
4047785e97 Recognize Dual Core (Penryn) and more Core2 processors 
By adding a new entry to the match table

There's also a new test:
 Intel Pentium Dual-Core Mobile T4500
 Specs:
 http://www.cpu-world.com/CPUs/Pentium_Dual-Core/Intel-Pentium%20Dual-Core%20Mobile%20T4500%20AW80577GG0521MA.html
 2016-04-28 00:28:07 +00:00
Veselin Georgiev
db6f3abc9a Merge pull request #34 from wdlkmpx/master 
Fix issue with HyperThreading status in old cpus
 2016-04-25 01:51:24 +03:00
wdlkmpx
f26c1151f0 Fix issue with HyperThreading status in old cpus 
Early P4 processors come with the HT flag, but that feature
is not enabled.

This makes it work the way it should.
 2016-04-24 17:28:16 +00:00
wdlkmpx
fa9640b3a2 tests: add p4 celeron willamette-128 
1.8GHz
Specs:
http://www.cpu-world.com/CPUs/Celeron/Intel-Celeron%201800%20-%20RK80531RC033128%20(BX80531P180G128).html
 2016-04-24 17:26:44 +00:00
wdlkmpx
75c3c36cbb tests: add intel p4 prescott with HT enabled 
This is from a Pentium 4 Prescott 3.20GHz processor
Specs:
http://www.cpu-world.com/CPUs/Pentium_4/Intel-Pentium%204%203.2%20GHz%20-%20RK80546PG0881M%20(BX80546PG3200E).html
 2016-04-24 17:26:03 +00:00
Kurt Cancemi
dea8a6006a Fix tests 2016-04-24 00:27:42 -04:00
wdlkmpx
5f420362c6 P4 Celeron: more precise descriptions 
According to wikipedia, cpu-world and some cpu-z screenshots, these processors
do have a code name and it's willamette, northwood, prescott or cedar mill

Signed-off-by: Veselin Georgiev <anrieff@gmail.com>
 2016-04-19 00:57:11 +03:00
Veselin Georgiev
13f382725b Fix 'make test' failing without any really wrong tests. 
The reason was that the invocation of the cpuid_tool through the makefile
was using LD_LIBRARY_PATH=. to force link&use of the latest-build libcpuid
library. This doesn't seem to work, so using LD_PRELOAD to explicitly load
libcpuid.so into cpuid_tool.

The committed approach of course doesn't work on Mac OS X, where
make test-old should be used.
 2016-03-10 02:44:17 +02:00
Kurt Cancemi
c5493f8008 Fix tests 2016-01-16 10:55:08 -05:00
Veselin Georgiev
4e3b633bee Fix tests due to X0rg's codename changes. 2015-09-13 18:38:59 +03:00
Veselin Georgiev
153a6a7c7d Add support for detecting Xeon Ivy Bridge. 
Based on report #7 from the sourceforge bugtrack page.
 2015-09-03 09:33:38 +03:00
Veselin Georgiev
812b89bcb8 'make test' ported to run on Python 2.5 as well. 2015-04-20 17:22:11 +03:00
Veselin Georgiev
94fc6ae36a Modify the table matcher a bit. Put some weights on the different fields. 
Priously all fields in the matchtable were treated equal in importance.
With this change, the cache size a taken with half the weight in the decision.

Also add detection entries for some more recent Haswells, and the respective
tests. These are an i5 Haswell from a Mac Book Pro, and a i7 Haswel from
Thinkpad T540.
 2015-04-17 01:21:30 +03:00
Veselin Georgiev
046d2ca2ab Better support for AVX, AVX2, BMI1 and BMI2 instruction set detection. 
- Detect AVX and AVX2 on both Intel and AMD CPUs
- Detect BMI1 and BMI2 instruction sets (BMI2 is only on Haswell, BMI1 is
  also present on Bulldozers).
- Fix tests to reflect changes.
 2015-04-16 20:54:37 +03:00
Veselin Georgiev
fa2083a992 Add support for detecting AVX2. Confirmed to detect on Haswell i3. 2014-09-24 00:03:11 +03:00
Veselin Georgiev
ce02f0bc96 Fix broken tests, where rdtscp in recent Intel chips is missing. 
As described in previous commit.
 2014-09-23 15:21:02 +03:00
Veselin Georgiev
a716585cc0 Add to makefile: "make fix-tests" to fix failing tests. 
The last change to flags detection caused a bunch of tests to fail.
The reason is that they are bogus, all recent Intel chips don't have
RDTSCP indicated in the test files, whereas they have it in reality.
I figured it will be easier to add "--fix" option to run_tests.py,
rather than fixing each testfile by hand.

This is also extended in the Makefile:

"make test" runs the tests and reports discrepancies.
"make fix-tests" fixes any offending tests. This blindly assumes that
libcpuid is sane.
 2014-09-23 15:20:27 +03:00
Veselin Georgiev
ece31fb8d3 Add a test for Atom N2800 (codename Cedarview). 2014-08-20 11:25:52 +03:00
Veselin Georgiev
d80ae596ab Fix bogus tests in the Atom category 
- Atom Dual-core (Diamondville) is renamed to just Atom (Diamondville)
- The test with Atom D425 is named "Pineview", while the one with
  Atom D525 was incorrectly named "Cedarview". Moving the latter to
  atom-pineview-2.test and fixing its codename.
 2014-08-20 11:22:25 +03:00
Veselin Georgiev
b183a2d2f8 Magny-cours is still K10, so move the test to the proper dir. 2014-07-23 22:30:52 +03:00
Veselin Georgiev
decba3e728 Simplify Bulldozer detection; differentiate Bulldozer<->Vishera. 
Also add two tests:
- AMD FX-8150 - which is decoded as 'Bulldozer X4'
- AMD FX-9590 - which is decoted as 'Vishera X4'
 2014-07-23 22:13:37 +03:00
Veselin Georgiev
f883e2b592 Add recognition support for Haswell i3, i5 and i7. 
Add a test based on a Haswell i3 (Core i3-4130).
 2014-07-18 21:00:48 +03:00
Veselin Georgiev
551aff201b When creating a tarball, include the small tests now instead of tests_stash.txt 2014-07-16 10:29:58 +03:00
Veselin Georgiev
989ea9f586 Delete unused old test data/utils. 2014-07-16 10:11:28 +03:00
Veselin Georgiev
f6acf1b634 Refactor "make test" as well. 2014-07-16 10:10:51 +03:00
Veselin Georgiev
019170b65f Refactor the tests: put each test case in a separate file 
Instead of one big pile of tests in tests_stash.txt, keep each CPU
example raw data/parsed data in a file, ordered in a tree by
manufacturer and microarchitecture. The 64 .test files have been
extracted from tests_stash.txt. The add_test script is changed to
create_test and it doesn't append to test_stash.txt, instead it
spits out data to be saved in a .test file.

run_tests.py is not refactored yet, to be done in a subsequent commit.
 2014-07-15 19:59:35 +03:00
Veselin Georgiev
3c9aa04f13 Rename: add_test.py -> create_test.py 2014-07-15 17:56:16 +03:00
Veselin Georgiev
fbed394404 Change add_test.py to output the concatenated raw/report to stdout. 
Instead of appending it to test_stash.
 2014-07-15 17:55:39 +03:00
Veselin Georgiev
20632054d6 Add support for Atom Pineview. 2014-06-23 23:41:02 +03:00
Veselin Georgiev
45651ef7bc Merge 141243f from http://github.com/eloaders/libcpuid 
This adds support for x2apic detection. This is not a direct merge, since

- the feature is spelled as 'x2apic' instead of 'x2APIC', for consistency with other flags;
- tests are added
- the id of the feature is moved to the end of the cpu_feature_t enum, for binary
  compatibility.
 2014-06-22 21:00:18 +03:00
Veselin Georgiev
f385bac458 Added support for Intel Atom Cedarview 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@107 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2012-09-09 22:28:55 +00:00
Veselin Georgiev
1344ec1a81 Added support for detecting the following processors: The newer 6 and 8-core Sandy Bridges (termed Sandy Bridge-E), Ivy Bridge, AMD Magny-Cours. Added support for detecting the rdrand instruction. Added tests. 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@104 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2012-05-26 13:00:04 +00:00
Veselin Georgiev
9fafda1bed Added support for Sandy-bridge based celerons 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@101 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-10-13 22:46:42 +00:00
Veselin Georgiev
62605fffd8 Added a test with a Zacate CPU. Also, fixed the add_test script 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@99 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-10-11 17:33:30 +00:00
Veselin Georgiev
42fc8b4654 Modified the test-stash and the testing code, so that it is aware of the SSE unit size functionality. Also, added support for detecting AMD Llano/Brazos CPUs 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@98 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-10-11 17:26:00 +00:00
Veselin Georgiev
2f949b18d9 Support for 2MB L2 Cache Yorkfield added. Also, made the logic a bit more foolproof by adding explicit core count for those Yorkfields. 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@95 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-01-16 01:11:00 +00:00
Veselin Georgiev
49c474f74d Support for Sandy Bridge (Core i7) processors 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@93 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-01-13 18:01:51 +00:00
Veselin Georgiev
166445dbd0 Added Celeron Wolfdale (45nm-based 1MB cache C2D CPU) 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@92 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-01-13 13:34:13 +00:00
Veselin Georgiev
27e7508e7d Support for Arrandale i7s 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@91 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2011-01-13 13:12:21 +00:00
Veselin Georgiev
f1c250d6cf Support for Lynnfield i7s, and better detection of Athlon Propus. Also, added newer Athlon II X3s (Rana) 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@89 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-10-15 08:37:54 +00:00
Veselin Georgiev
6a7854f3b4 Support for Gulftown (westmere-based) Intels, and for AMD X6 (Thuban). Also differentiated the Thuban-derived X4s (Zosma) which I suppose also have ext model 10, but this needs to be verified. 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@88 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-10-13 11:59:46 +00:00
Veselin Georgiev
d520a37569 Support for Core i5/i3. The matchtables now have a column for L3 cache 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@87 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2010-10-13 09:18:07 +00:00
Veselin Georgiev
3578314b9b Added support for Athlon II Propus 
git-svn-id: https://svn.code.sf.net/p/libcpuid/code/HEAD/libcpuid@67 3b4be424-7ac5-41d7-8526-f4ddcb85d872
 2009-09-24 20:39:04 +00:00