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Author SHA1 Message Date
anonymous
d35968e8b7 suggested corrections - argument order & removal of ? 2018-04-23 17:19:24 +00:00
anonymous
53bcf98c0f Merge http://github.com/themusicgod1/libcpuid 2018-04-21 23:19:26 -04:00
anonymous
d9c4769c44 fixed lintian errors - changed section, fixed doxygen building of manpage 2018-04-21 23:18:19 -04:00
anonymous
a9c739d312 virtual machine test 2018-04-21 01:00:30 +00:00
Veselin Georgiev
aa28586183 Fix issue #108: Hints for building on NetBSD 
Add @brucelilly's suggestions to the Readme
 2018-04-16 10:45:15 +03:00
Veselin Georgiev
e93afea7f2
Merge pull request #106 from X0rg/master 
DB: Add Raven Ridge APUs and Threadripper CPUs
 2018-03-21 00:08:29 +02:00
Xorg
f1e1ad58e7 DB: Add Raven Ridge APUs and Threadripper CPUs 2018-03-20 19:52:40 +01:00
Veselin Georgiev
f178de98f3 Fix issue #104: Intel Coffee Lake and Kaby Lake 
Add support for detecting Coffee Lake i[357]s. Test included.
Thanks to @X0rg for reporting and to @exdeus for the raw cpu data.

The detection here relies on Kaby and Coffee lakes having different
number of cores for the equivalent brand:

i3: 2 cores in Kaby, 4 in Coffee
i5 and i7: 4 cores in Kaby, 6 in Coffee.
 2018-02-04 13:37:36 +02:00
Veselin Georgiev
2f4c21e3a7 Fixed issue #103: Intel Xeon Scalable not recognised "code name". 
Table entry added, test added, thanks to @phprus for reporting.
 2018-01-28 02:06:37 +02:00
Veselin Georgiev
2f1031543c Fix issue #101: Package should not use obsolete m4 macros 2017-10-23 16:59:57 +03:00
Veselin Georgiev
57298c650c Merge pull request #93 from X0rg/master 
Fixes for #91
 2017-05-04 13:36:19 +01:00
Xorg
dd702cd253 RDMSR: enhance AMD APUs detection 
As suggested in #91
 2017-05-04 07:32:02 +02:00
Xorg
f8c7ee44e0 RDMSR: Use SVI2 step for AMD family 15h model 10h and above 2017-05-04 07:22:33 +02:00
Veselin Georgiev
98661492af Related to #91: Make bits available in libcpuid_internal.h 
Along with some interop changes, as the Intel/AMD bits were sometimes
very similar or totally coinciding.
 2017-05-04 03:51:41 +03:00
Veselin Georgiev
a196e8d1bf Related to #91: Add detection of AMD APUs. 
It is very simple detection - if the brand string contains " APU ",
the _APU_ bit in amd_code_and_bits_t::bits is set.

Simplify one other line as well.
 2017-05-04 03:37:09 +03:00
Xorg
5a02be091a RDMSR: use double instead of uint64_t for AMD CPU multipliers 
Multipliers can be a decimal number, like 7.5x
 2017-04-30 21:08:15 +02:00
Xorg
84f95c8ad0 RDMSR: fix VID range for AMD family 15h and above 
Fix #91
 2017-04-30 20:21:31 +02:00
Xorg
58b8eabd7c RDMSR: fix multipliers computed by get_amd_multipliers() 
This change should affect only 15h family
Fix #91
 2017-04-30 19:17:32 +02:00
Veselin Georgiev
b0cc93a253 Merge pull request #92 from X0rg/master 
AMD Ryzen support (RDMSR)
 2017-04-26 15:50:02 +01:00
Xorg
6574ce29e8 RDMSR: add Ryzen support 
Close #86
 2017-04-26 15:40:46 +02:00
Veselin Georgiev
b9a85805d2 Add "Multiprecision Computing Toolbox for MATLAB" to libcpuid users. 
As suggested in issue #89.
 2017-04-04 17:31:03 +03:00
Veselin Georgiev
8fe734c493 Fix previous commit based on comments in issue #89 thread. 
This should be correct now.
 2017-04-04 06:18:47 +03:00
Veselin Georgiev
88483aaba0 Possibly fix #89: Build failes with MSVC 
Fix non-C89 constructs. Not really verified to compile fine on MSVC,
since I don't have one right now, but will check later.
 2017-04-03 13:24:57 +03:00
Veselin Georgiev
94507ded22 Fixed issue #86: AMD Ryzen support 
Also add a test of Ryzen 7 (1800X).
 2017-03-20 02:28:28 +02:00
Veselin Georgiev
779b403aa0 Matchtable refactoring for AMD (see previous commit). 2017-03-20 01:47:28 +02:00
Veselin Georgiev
8179882abb Major refactoring of the Intel match tables. 
There were a lot of instances where there was additional code
written to detect certain features from the brand string
(e.g., does it have "Core (TM)"? if it has, does it have "i3"?).
It makes sense to only write code for detecting these features
in isolation, preventing the exponential blowup of possible
intel_code_t values (e.g. previously there were enum values
for CORE_{,IVY,HASWELL,BROADWELL,SKYLAKE}{,M}{3,5,7} - almost
20 separate enums items; these can now be expressed with the
respective bits (CORE_, _I_, _M_, _3, _5 and _7).

The change in matchtables is the addition of an extra field
after brand_code: it is called model_bits. The bits for each
vendor is defined in the beginning of recog_<<vendor>>.c

This is the first part of the overhaul, which handles the bits
detection and proper matchtables for Intel. Refactoring of
AMD detection code coming next...
 2017-03-20 01:01:22 +02:00
Veselin Georgiev
037245032e Merge pull request #88 from X0rg/master 
Update CPUs database
 2017-03-15 12:23:24 +00:00
Xorg
bb4141a25a Enforce Python 2.7 in tests 2017-03-12 09:34:26 +01:00
Xorg
803a062479 Doesn't specify l2_cache value for Llano CPUs and newer 2017-03-12 09:32:28 +01:00
Xorg
8f94a9d88a Partially revert 9f391244bc about Skylake Core i[357] changes 2017-03-12 09:29:49 +01:00
Xorg
76d5892bbe Reorganise AMD CPUs/APUs by family, fix wrong extended family 2017-03-11 19:19:58 +01:00
Xorg
9f391244bc Recognise more Intel CPUs, fix Skylake detection 2017-03-11 16:55:19 +01:00
Xorg
d212585d51 Align some misaligned brackets in databases 2017-03-11 15:44:40 +01:00
Veselin Georgiev
3272be1d21 Add comment about cpu_msrinfo() being not-threadsafe. 2017-03-04 20:22:13 +02:00
Veselin Georgiev
2a2d43b9a3 Merge pull request #87 from X0rg/master 
Fixes related to #84
 2017-03-04 18:18:56 +00:00
Xorg
45158da967 RDMSR: fix wrong values after using cpu_msr_driver_close() 2017-03-04 19:06:27 +01:00
Xorg
660cde12c7 cpuid_tool: fix multipliers format since 6ae7e344be 2017-03-04 19:04:17 +01:00
Veselin Georgiev
1e597b9d25 Merge pull request #85 from X0rg/master 
Fixes for #84
 2017-03-04 16:19:25 +00:00
Xorg
e5193b0163 RDMSR: fix last P-state calculation with AMD CPUs 2017-03-04 16:40:46 +01:00
Xorg
6ae7e344be cpuid_tool: fix output with --rdmsr option 2017-03-04 14:34:38 +01:00
Veselin Georgiev
c96ae6f8fc Merge pull request #83 from X0rg/master 
Various changes for RDMSR
 2017-02-15 01:44:51 +00:00
Xorg
eac52e7f04 RDMSR: fix bus speed computing with AMD CPUs 2017-02-12 21:51:04 +01:00
Xorg
09a75e95f2 RDMSR: fix returned value on NULL handler 
It should return CPU_INVALID_VALUE on error, not ERR_HANDLE
 2017-02-12 20:17:56 +01:00
Xorg
e7bfcc3651 RDMSR: add an internal structure to pass arguments 2017-02-12 20:17:56 +01:00
Xorg
d5c892e002 RDMSR: fix cpu_msrinfo() function with AMD CPUs 2017-02-12 20:17:51 +01:00
Veselin Georgiev
0cb7023828 Merge pull request #82 from X0rg/master 
Add a switch to cpuid_tool to dump MSR values to a file.

This is very similar to the --save=... feature.
 2017-02-10 01:55:05 +00:00
Veselin Georgiev
86bf8e8269 Fixed issue #81: Misdiagnosis microarchitecture for i3-3220T 
It's a mystery to me why this CPU doesn't have RdRand.
A quick-n-dirty workaround is inserted to fix that.
 2017-02-10 03:48:00 +02:00
Xorg
9b038c94c4 Add a msr_serialize_raw_data() function 2017-02-09 20:55:28 +01:00
Veselin Georgiev
fa87a5e183 Fixed issue #78: date in changelog is wrong 2016-11-13 02:54:52 +02:00
Veselin Georgiev
e36a08deb9 Fixed issue #76: Skylake Core i5 badly recognized 
Add support for detecting RDSEED and ADX instructions.
Use RDSEED instead of RTM to ascertain that the CPU is
Broadwell or later in recog_intel.c. This fixes
detection discrepancies on Linux, where RTM is not
made available (I guess there's no kernel support for it).

The two new flags are also now detected in the Broadwell
and Skylake tests. Update them as well.
 2016-10-25 05:16:44 +03:00