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46 commits

Author SHA1 Message Date
Xorg
7ab6b3273c
DB: add AMD custom APU for Steam Deck
Fix X0rg/CPU-X#236
2022-09-27 20:19:12 +02:00
Xorg
3ed66b7613
Treat others CPU packages as different CPU types
If a RAW dump is containing for instance 256 logical CPUs (2 sockets with 64 cores and SMT), they should not be considered as a 128 cores CPU with SMT.
2022-09-22 21:50:08 +02:00
Xorg
1a0eb95d02
DB: add more AMD Kabini 2022-09-22 20:54:25 +02:00
Xorg
f23a2e3a41
DB: add AMD Steppe Eagle 2022-09-22 20:46:36 +02:00
Xorg
e591e52245
DB: add AMD Beema 2022-09-22 20:46:23 +02:00
Xorg
a3b9b7a798
DB: add AMD Abu Dhabi 2022-09-22 20:27:08 +02:00
Xorg
401a56e4cb
DB: add AMD Interlagos 2022-09-22 20:26:55 +02:00
Xorg
ee97ed213a
DB: rename AMD Bulldozer to Zambezi 2022-09-22 20:17:33 +02:00
Xorg
a98817b804
DB: add AMD Bald Eagle 2022-09-22 20:10:36 +02:00
Xorg
5b8d89a37d
Tests: replace converted RAW dumps from instlatx64 to AIDA64 format
Since 2b8023f733 and 6b742be8cb, it makes sense to update these tests to add:
- RAW CPUID for all CPU cores
- Number of caches instances
2022-09-22 19:36:48 +02:00
Xorg
6b742be8cb Add cache instances field in cpu_id_t and system_id_t 2022-09-22 17:49:38 +02:00
Xorg
0c9ef3249c Decode deterministic cache info for AMD CPUs too
Since Zen-based CPUs, cpu_id_t::l3_cache is the size of the total L3 cache for the whole chip, while cpu_id_t::l1_cache and cpu_id_t::l2_cache are size for each instances.
This change provide L3 cache size per instance.
2022-09-22 17:49:38 +02:00
Xorg
b1732e4785
Tests: minor fixes
Since ff5aafb5f4, xeon-scalable-4114.test and qemu.test are failling because RAW came from a VM.
Since 2b8023f733, godavari-x4.test is failling due to the merge after 9710e7c0ba
2022-09-20 06:58:32 +02:00
Xorg
2b8023f733
Support for hybrid CPU (#166)
* Set CMAKE_C_FLAGS_DEBUG to display warnings during build

CI workflows are reporting warnings. Adding more C flags here help to avoid that.

* Add new types

* Add set_cpu_affinity function

* Add cpu_identify_all function

* Add cpu_request_core_type function

* Add cpuid_get_all_raw_data, cpuid_serialize_all_raw_data and cpuid_deserialize_all_raw_data functions

* Detect hybrid architecture for Intel CPUs

* Update cpuid_tool to detect all CPU logical cores

* Rename tests subdirectories for Intel Core

* Update all tests

Since e4309a6c4bc3ad875711a1599cba01a205b3103e, new fields are reported by cpuid_tool

* Add Intel Alder Lake

Fix #157

* Remove convert_instlatx64.c

This tool is not useful anymore because the cpuid_deserialize_raw_data_internal() function can natively parse them since 5667e1401c

* Fix affinity_mask computation

* Define _GNU_SOURCE in configure.ac

Forgotten in 4f80964db5

* Use dynamic raw array in cpu_raw_data_array_t

* Add cpu_affinity_mask_t type

* Improve set_cpu_affinity function

- Print a warning if logical CPU number is not supported on operating system
- Return a boolean value in case of success instead of an integer

* Improve cpu_identify_all and cpu_request_core_type functions

* Use dynamic array for cpu_types in system_id_t

This commit also adds cleanups, fixes and consistency

* Tests: update Ryzen 5 Matisse with all CPU cores

* Add affinity_mask_str_r function and address other comments

- Fixed cpuid_grow_raw_data_array and cpu_raw_data_array_t.logical_cpu_t with the correct type
- Added a note about hard limit of cpu_raw_data_array_t
- Fixed a typo in cpuid_deserialize_raw_data_internal

* Fix build on Windows
2022-09-15 18:37:08 +02:00
Xorg
9710e7c0ba
DB: add AMD Athlon Godavari
Fix X0rg/CPU-X#232
2022-09-07 18:37:14 +02:00
Xorg
660126c55d
Tests: add AMD A10 Pro-7350B (Kaveri) from InstLatx64 2022-08-28 11:42:25 +02:00
Xorg
ca0327d621
DB: add Warhol 2022-08-28 11:41:28 +02:00
Xorg
cbaa02a966
DB: add Rembrandt 2022-08-28 11:22:03 +02:00
Xorg
ecd45bb276
Tests: add more Zen2 tests from InstLatx64 2022-02-06 11:52:55 +01:00
Xorg
5ce462c32c
DB: add Lucienne
https://en.wikichip.org/wiki/amd/cores/lucienne
Fix X0rg/CPU-X#209
2022-02-06 11:29:46 +01:00
Xorg
c8238acd0a
DB: add Milan
https://en.wikichip.org/wiki/amd/cores/milan
InstLatx64/InstLatx64@2dc186e948
2021-03-20 17:10:07 +01:00
Xorg
08b4b6e41b
DB: add Cezanne
Tests extracted from InstLatx64/InstLatx64@002ce3c923
2021-01-31 15:24:39 +01:00
Xorg
04c3ebe0e9
DB: add Vermeer
https://en.wikichip.org/wiki/amd/cores/vermeer
Test file converted from http://users.atw.hu/instlatx64/AuthenticAMD/AuthenticAMD0A20F10_K19_Vermeer_CPUID1.txt
2020-11-14 13:45:15 +01:00
Xorg
9419c573ca
Detect RDSEED/ADX/SHA_NI features on AMD CPUs
These x86 instruction set extensions are present since Zen micro-architecture
Resolve #145
2020-05-18 21:05:20 +02:00
Xorg
fb1deb1fef Tests: update all tests to add fields for L1I 2020-05-10 17:02:45 +00:00
Xorg
6b5a1f5ea6
Tests: add amd_fn8000001dh subleaf
See e562798cec
2020-05-09 22:48:07 +02:00
Veselin Georgiev
9d22c61611
Merge pull request #141 from X0rg/master
Fixes for AMD Zen 2 CPUs
2020-05-04 21:35:42 +03:00
Xorg
46e86331bb
tests: remove duplicate addresses in RAW part 2020-05-03 17:12:33 +02:00
Xorg
848394ee46
Fix L3 cache associativity detection on AMD Zen 2 CPUs 2020-05-03 17:07:43 +02:00
eloaders
5f7f3c26cc DB: Add Threadripper (Castle Peak) 2019-12-31 10:58:20 +01:00
Xorg
848354a3f1 Tests: Add more Matisse CPUs 2019-07-11 22:49:08 +02:00
Xorg
bf7f57f519 Fix SSE unit size for Zen 2 CPUs
Related to #125
2019-07-11 22:29:27 +02:00
Xorg
5aedd53624 Add more test files for AMD Zen CPUs
Dumps found on http://instlatx64.atw.hu/
2019-07-07 20:03:45 +02:00
Xorg
081c354d17 DB: Add AMD Ryzen 3000 2019-07-07 19:38:46 +02:00
Xorg
3a8343c77c Fix Ryzen core count calculation
Close X0rg/CPU-X#86
2018-11-03 21:30:01 +01:00
Xorg
f1e1ad58e7 DB: Add Raven Ridge APUs and Threadripper CPUs 2018-03-20 19:52:40 +01:00
Veselin Georgiev
94507ded22 Fixed issue #86: AMD Ryzen support
Also add a test of Ryzen 7 (1800X).
2017-03-20 02:28:28 +02:00
Veselin Georgiev
f52c02d394 Update all tests: add fields for L4 cache size, assoc. and line size. 2016-07-07 00:44:45 +03:00
Veselin Georgiev
3a977a4f99 Add detection support for the AMD TBM instructions. Update Vishera test. 2016-05-19 01:37:45 +03:00
wdlkmpx
061bd5986c Ability to display AMD brand code
So that it's easier to test and debug

Also added AMD Champlain mobile
Processor: AMD Athlon(tm) II P320 Dual-Core Processor
2016-05-11 21:21:02 +00:00
Kurt Cancemi
dea8a6006a Fix tests 2016-04-24 00:27:42 -04:00
Kurt Cancemi
c5493f8008 Fix tests 2016-01-16 10:55:08 -05:00
Veselin Georgiev
046d2ca2ab Better support for AVX, AVX2, BMI1 and BMI2 instruction set detection.
- Detect AVX and AVX2 on both Intel and AMD CPUs
- Detect BMI1 and BMI2 instruction sets (BMI2 is only on Haswell, BMI1 is
  also present on Bulldozers).
- Fix tests to reflect changes.
2015-04-16 20:54:37 +03:00
Veselin Georgiev
b183a2d2f8 Magny-cours is still K10, so move the test to the proper dir. 2014-07-23 22:30:52 +03:00
Veselin Georgiev
decba3e728 Simplify Bulldozer detection; differentiate Bulldozer<->Vishera.
Also add two tests:
- AMD FX-8150 - which is decoded as 'Bulldozer X4'
- AMD FX-9590 - which is decoted as 'Vishera X4'
2014-07-23 22:13:37 +03:00
Veselin Georgiev
019170b65f Refactor the tests: put each test case in a separate file
Instead of one big pile of tests in tests_stash.txt, keep each CPU
example raw data/parsed data in a file, ordered in a tree by
manufacturer and microarchitecture. The 64 .test files have been
extracted from tests_stash.txt. The add_test script is changed to
create_test and it doesn't append to test_stash.txt, instead it
spits out data to be saved in a .test file.

run_tests.py is not refactored yet, to be done in a subsequent commit.
2014-07-15 19:59:35 +03:00